1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 EXTERNDEF SmiPFHandler:PROC
22 EXTERNDEF gSmiMtrrs:QWORD
23 EXTERNDEF gcSmiIdtr:FWORD
24 EXTERNDEF gcSmiGdtr:FWORD
29 NullSeg DQ 0 ; reserved by architecture
37 ProtModeCodeSeg32 LABEL QWORD
44 ProtModeSsSeg32 LABEL QWORD
79 ; TSS Segment for X64 specially
81 DW TSS_DESC_SIZE ; LimitLow
89 GDT_SIZE = $ - offset NullSeg
91 ; Create TSS Descriptor just after GDT
92 TssDescriptor LABEL BYTE
109 DW 0 ; I/O Map Base Address
110 TSS_DESC_SIZE = $ - offset TssDescriptor
113 ; This structure serves as a template for all processors.
127 DQ 0 ; fixed in InitializeMpServiceData()
133 PSD_SIZE = $ - offset gcPsd
136 ; CODE & DATA segments for SMM runtime
138 CODE_SEL = offset CodeSeg64 - offset NullSeg
139 DATA_SEL = offset DataSeg32 - offset NullSeg
140 CODE32_SEL = offset CodeSeg32 - offset NullSeg
142 gcSmiGdtr LABEL FWORD
146 gcSmiIdtr LABEL FWORD
153 ; Here is the IDT. There are 32 (not 255) entries in it since only processor
154 ; generated exceptions will be handled.
159 DW CODE_SEL ; Segment selector
161 DB 8eh ; Interrupt Gate, Present
167 IDT_SIZE = (offset _SmiIDTEnd - offset _SmiIDT)
171 ;------------------------------------------------------------------------------
172 ; _SmiExceptionEntryPoints is the collection of exception entry points followed
173 ; by a common exception handler.
175 ; Stack frame would be as follows as specified in IA32 manuals:
177 ; +---------------------+ <-- 16-byte aligned ensured by processor
179 ; +---------------------+
181 ; +---------------------+
183 ; +---------------------+
185 ; +---------------------+
187 ; +---------------------+
189 ; +---------------------+
191 ; +---------------------+
193 ; +---------------------+ <-- RBP, 16-byte aligned
195 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
196 ;------------------------------------------------------------------------------
197 PageFaultIdtHandlerSmmProfile PROC
198 push 0eh ; Page Fault
199 test spl, 8 ; odd multiple of 8 => ErrCode present
201 push [rsp] ; duplicate INT# if no ErrCode
202 mov qword ptr [rsp + 8], 0
208 ; Since here the stack pointer is 16-byte aligned, so
209 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
213 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
214 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
227 push qword ptr [rbp + 48] ; RSP
228 push qword ptr [rbp] ; RBP
232 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
233 movzx rax, word ptr [rbp + 56]
235 movzx rax, word ptr [rbp + 32]
247 push qword ptr [rbp + 24]
249 ;; UINT64 Gdtr[2], Idtr[2];
263 push qword ptr [rbp + 40]
265 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
281 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
295 ;; FX_SAVE_STATE_X64 FxSaveState;
299 db 0fh, 0aeh, 00000111y ;fxsave [rdi]
301 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
304 ;; UINT32 ExceptionData;
305 push qword ptr [rbp + 16]
307 ;; call into exception handler
309 mov rax, SmiPFHandler
311 ;; Prepare parameter and call
314 ; Per X64 calling convention, allocate maximum parameter stack space
315 ; and make sure RSP is 16-byte aligned
323 ;; UINT64 ExceptionData;
326 ;; FX_SAVE_STATE_X64 FxSaveState;
329 db 0fh, 0aeh, 00001110y ; fxrstor [rsi]
332 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
333 ;; Skip restoration of DRx registers to support debuggers
334 ;; that set breakpoints in interrupt/exception context
337 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
340 add rsp, 8 ; not for Cr1
351 pop qword ptr [rbp + 40]
354 ;; UINT64 Gdtr[2], Idtr[2];
355 ;; Best not let anyone mess with these particular registers...
359 pop qword ptr [rbp + 24]
361 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
363 ; mov gs, rax ; not for gs
365 ; mov fs, rax ; not for fs
366 ; (X64 will not use fs and gs, so we do not restore it)
371 pop qword ptr [rbp + 32] ; for cs
372 pop qword ptr [rbp + 56] ; for ss
374 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
375 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
378 add rsp, 8 ; not for rbp
379 pop qword ptr [rbp + 48] ; for rsp
395 ; Enable TF bit after page fault handler runs
396 bts dword ptr [rsp + 40], 8 ;RFLAGS
399 add rsp, 16 ; skip INT# & ErrCode
401 PageFaultIdtHandlerSmmProfile ENDP
403 InitializeIDTSmmStackGuard PROC
405 ; If SMM Stack Guard feature is enabled, set the IST field of
406 ; the interrupt gate for Page Fault Exception to be 1
408 lea rax, _SmiIDT + 14 * 16
409 mov byte ptr [rax + 4], 1
411 InitializeIDTSmmStackGuard ENDP