1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 extern ASM_PFX(SmiPFHandler)
22 extern ASM_PFX(gSmiMtrrs)
24 global ASM_PFX(gcSmiIdtr)
25 global ASM_PFX(gcSmiGdtr)
30 NullSeg: DQ 0 ; reserved by architecture
80 ; TSS Segment for X64 specially
82 DW TSS_DESC_SIZE ; LimitLow
90 GDT_SIZE equ $ - NullSeg
92 ; Create TSS Descriptor just after GDT
110 DW 0 ; I/O Map Base Address
111 TSS_DESC_SIZE equ $ - TssDescriptor
114 ; This structure serves as a template for all processors.
128 DQ 0 ; fixed in InitializeMpServiceData()
133 DQ ASM_PFX(gSmiMtrrs)
134 PSD_SIZE equ $ - ASM_PFX(gcPsd)
137 ; CODE & DATA segments for SMM runtime
139 CODE_SEL equ CodeSeg64 - NullSeg
140 DATA_SEL equ DataSeg32 - NullSeg
141 CODE32_SEL equ CodeSeg32 - NullSeg
152 ; Here is the IDT. There are 32 (not 255) entries in it since only processor
153 ; generated exceptions will be handled.
158 DW CODE_SEL ; Segment selector
160 DB 0x8e ; Interrupt Gate, Present
166 IDT_SIZE equ _SmiIDTEnd - _SmiIDT
171 ;------------------------------------------------------------------------------
172 ; _SmiExceptionEntryPoints is the collection of exception entrypoints followed
173 ; by a common exception handler.
175 ; Stack frame would be as follows as specified in IA32 manuals:
177 ; +---------------------+ <-- 16-byte aligned ensured by processor
179 ; +---------------------+
181 ; +---------------------+
183 ; +---------------------+
185 ; +---------------------+
187 ; +---------------------+
189 ; +---------------------+
191 ; +---------------------+
193 ; +---------------------+ <-- RBP, 16-byte aligned
195 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
196 ;------------------------------------------------------------------------------
197 global ASM_PFX(PageFaultIdtHandlerSmmProfile)
198 ASM_PFX(PageFaultIdtHandlerSmmProfile):
199 push 0xe ; Page Fault
200 test spl, 8 ; odd multiple of 8 => ErrCode present
202 push qword [rsp] ; duplicate INT# if no ErrCode
203 mov qword [rsp + 8], 0
209 ; Since here the stack pointer is 16-byte aligned, so
210 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
214 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
215 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
228 push qword [rbp + 48] ; RSP
229 push qword [rbp] ; RBP
233 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
234 movzx rax, word [rbp + 56]
236 movzx rax, word [rbp + 32]
248 push qword [rbp + 24]
250 ;; UINT64 Gdtr[2], Idtr[2];
264 push qword [rbp + 40]
266 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
282 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
296 ;; FX_SAVE_STATE_X64 FxSaveState;
300 db 0xf, 0xae, 00000111y ;fxsave [rdi]
302 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
305 ;; UINT32 ExceptionData;
306 push qword [rbp + 16]
308 ;; call into exception handler
310 mov rax, ASM_PFX(SmiPFHandler)
312 ;; Prepare parameter and call
315 ; Per X64 calling convention, allocate maximum parameter stack space
316 ; and make sure RSP is 16-byte aligned
324 ;; UINT64 ExceptionData;
327 ;; FX_SAVE_STATE_X64 FxSaveState;
330 db 0xf, 0xae, 00001110y ; fxrstor [rsi]
333 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
334 ;; Skip restoration of DRx registers to support debuggers
335 ;; that set breakpoints in interrupt/exception context
338 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
341 add rsp, 8 ; not for Cr1
355 ;; UINT64 Gdtr[2], Idtr[2];
356 ;; Best not let anyone mess with these particular registers...
362 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
364 ; mov gs, rax ; not for gs
366 ; mov fs, rax ; not for fs
367 ; (X64 will not use fs and gs, so we do not restore it)
372 pop qword [rbp + 32] ; for cs
373 pop qword [rbp + 56] ; for ss
375 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
376 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
379 add rsp, 8 ; not for rbp
380 pop qword [rbp + 48] ; for rsp
396 ; Enable TF bit after page fault handler runs
397 bts dword [rsp + 40], 8 ;RFLAGS
400 add rsp, 16 ; skip INT# & ErrCode
403 global ASM_PFX(InitializeIDTSmmStackGuard)
404 ASM_PFX(InitializeIDTSmmStackGuard):
406 ; If SMM Stack Guard feature is enabled, set the IST field of
407 ; the interrupt gate for Page Fault Exception to be 1
409 lea rax, [_SmiIDT + 14 * 16]
410 mov byte [rax + 4], 1