1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 extern ASM_PFX(SmiPFHandler)
23 global ASM_PFX(gcSmiIdtr)
24 global ASM_PFX(gcSmiGdtr)
29 NullSeg: DQ 0 ; reserved by architecture
79 ; TSS Segment for X64 specially
81 DW TSS_DESC_SIZE ; LimitLow
89 GDT_SIZE equ $ - NullSeg
91 ; Create TSS Descriptor just after GDT
109 DW 0 ; I/O Map Base Address
110 TSS_DESC_SIZE equ $ - TssDescriptor
113 ; This structure serves as a template for all processors.
127 DQ 0 ; fixed in InitializeMpServiceData()
133 PSD_SIZE equ $ - ASM_PFX(gcPsd)
136 ; CODE & DATA segments for SMM runtime
138 CODE_SEL equ CodeSeg64 - NullSeg
139 DATA_SEL equ DataSeg32 - NullSeg
140 CODE32_SEL equ CodeSeg32 - NullSeg
153 ;------------------------------------------------------------------------------
154 ; _SmiExceptionEntryPoints is the collection of exception entrypoints followed
155 ; by a common exception handler.
157 ; Stack frame would be as follows as specified in IA32 manuals:
159 ; +---------------------+ <-- 16-byte aligned ensured by processor
161 ; +---------------------+
163 ; +---------------------+
165 ; +---------------------+
167 ; +---------------------+
169 ; +---------------------+
171 ; +---------------------+
173 ; +---------------------+
175 ; +---------------------+ <-- RBP, 16-byte aligned
177 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
178 ;------------------------------------------------------------------------------
179 global ASM_PFX(PageFaultIdtHandlerSmmProfile)
180 ASM_PFX(PageFaultIdtHandlerSmmProfile):
181 push 0xe ; Page Fault
182 test spl, 8 ; odd multiple of 8 => ErrCode present
184 push qword [rsp] ; duplicate INT# if no ErrCode
185 mov qword [rsp + 8], 0
191 ; Since here the stack pointer is 16-byte aligned, so
192 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
196 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
197 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
210 push qword [rbp + 48] ; RSP
211 push qword [rbp] ; RBP
215 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
216 movzx rax, word [rbp + 56]
218 movzx rax, word [rbp + 32]
230 push qword [rbp + 24]
232 ;; UINT64 Gdtr[2], Idtr[2];
246 push qword [rbp + 40]
248 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
264 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
278 ;; FX_SAVE_STATE_X64 FxSaveState;
282 db 0xf, 0xae, 00000111y ;fxsave [rdi]
284 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
287 ;; UINT32 ExceptionData;
288 push qword [rbp + 16]
290 ;; call into exception handler
292 lea rax, [ASM_PFX(SmiPFHandler)]
294 ;; Prepare parameter and call
297 ; Per X64 calling convention, allocate maximum parameter stack space
298 ; and make sure RSP is 16-byte aligned
306 ;; UINT64 ExceptionData;
309 ;; FX_SAVE_STATE_X64 FxSaveState;
312 db 0xf, 0xae, 00001110y ; fxrstor [rsi]
315 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
316 ;; Skip restoration of DRx registers to support debuggers
317 ;; that set breakpoints in interrupt/exception context
320 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
323 add rsp, 8 ; not for Cr1
337 ;; UINT64 Gdtr[2], Idtr[2];
338 ;; Best not let anyone mess with these particular registers...
344 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
346 ; mov gs, rax ; not for gs
348 ; mov fs, rax ; not for fs
349 ; (X64 will not use fs and gs, so we do not restore it)
354 pop qword [rbp + 32] ; for cs
355 pop qword [rbp + 56] ; for ss
357 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
358 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
361 add rsp, 8 ; not for rbp
362 pop qword [rbp + 48] ; for rsp
378 ; Enable TF bit after page fault handler runs
379 bts dword [rsp + 40], 8 ;RFLAGS
382 add rsp, 16 ; skip INT# & ErrCode