1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
11 ; Exception handlers used in SM mode
13 ;-------------------------------------------------------------------------------
15 extern ASM_PFX(SmiPFHandler)
17 global ASM_PFX(gcSmiIdtr)
18 global ASM_PFX(gcSmiGdtr)
23 NullSeg: DQ 0 ; reserved by architecture
73 ; TSS Segment for X64 specially
75 DW TSS_DESC_SIZE ; LimitLow
83 GDT_SIZE equ $ - NullSeg
85 ; Create TSS Descriptor just after GDT
103 DW 0 ; I/O Map Base Address
104 TSS_DESC_SIZE equ $ - TssDescriptor
107 ; This structure serves as a template for all processors.
121 DQ 0 ; fixed in InitializeMpServiceData()
127 PSD_SIZE equ $ - ASM_PFX(gcPsd)
130 ; CODE & DATA segments for SMM runtime
132 CODE_SEL equ CodeSeg64 - NullSeg
133 DATA_SEL equ DataSeg32 - NullSeg
134 CODE32_SEL equ CodeSeg32 - NullSeg
147 ;------------------------------------------------------------------------------
148 ; _SmiExceptionEntryPoints is the collection of exception entrypoints followed
149 ; by a common exception handler.
151 ; Stack frame would be as follows as specified in IA32 manuals:
153 ; +---------------------+ <-- 16-byte aligned ensured by processor
155 ; +---------------------+
157 ; +---------------------+
159 ; +---------------------+
161 ; +---------------------+
163 ; +---------------------+
165 ; +---------------------+
167 ; +---------------------+
169 ; +---------------------+ <-- RBP, 16-byte aligned
171 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
172 ;------------------------------------------------------------------------------
173 global ASM_PFX(PageFaultIdtHandlerSmmProfile)
174 ASM_PFX(PageFaultIdtHandlerSmmProfile):
175 push 0xe ; Page Fault
176 test spl, 8 ; odd multiple of 8 => ErrCode present
178 push qword [rsp] ; duplicate INT# if no ErrCode
179 mov qword [rsp + 8], 0
185 ; Since here the stack pointer is 16-byte aligned, so
186 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
190 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
191 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
204 push qword [rbp + 48] ; RSP
205 push qword [rbp] ; RBP
209 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
210 movzx rax, word [rbp + 56]
212 movzx rax, word [rbp + 32]
224 push qword [rbp + 24]
226 ;; UINT64 Gdtr[2], Idtr[2];
240 push qword [rbp + 40]
242 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
258 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
272 ;; FX_SAVE_STATE_X64 FxSaveState;
278 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
281 ;; UINT32 ExceptionData;
282 push qword [rbp + 16]
284 ;; call into exception handler
286 lea rax, [ASM_PFX(SmiPFHandler)]
288 ;; Prepare parameter and call
291 ; Per X64 calling convention, allocate maximum parameter stack space
292 ; and make sure RSP is 16-byte aligned
300 ;; UINT64 ExceptionData;
303 ;; FX_SAVE_STATE_X64 FxSaveState;
309 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
310 ;; Skip restoration of DRx registers to support debuggers
311 ;; that set breakpoints in interrupt/exception context
314 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
317 add rsp, 8 ; not for Cr1
331 ;; UINT64 Gdtr[2], Idtr[2];
332 ;; Best not let anyone mess with these particular registers...
338 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
340 ; mov gs, rax ; not for gs
342 ; mov fs, rax ; not for fs
343 ; (X64 will not use fs and gs, so we do not restore it)
348 pop qword [rbp + 32] ; for cs
349 pop qword [rbp + 56] ; for ss
351 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
352 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
355 add rsp, 8 ; not for rbp
356 pop qword [rbp + 48] ; for rsp
372 ; Enable TF bit after page fault handler runs
373 bts dword [rsp + 40], 8 ;RFLAGS
376 add rsp, 16 ; skip INT# & ErrCode