1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Functions for relocating SMBASE's for all processors
19 ;-------------------------------------------------------------------------------
21 extern ASM_PFX(SmmInitHandler)
22 extern ASM_PFX(mRebasedFlag)
23 extern ASM_PFX(mSmmRelocationOriginalAddress)
25 global ASM_PFX(gSmmCr3)
26 global ASM_PFX(gSmmCr4)
27 global ASM_PFX(gSmmCr0)
28 global ASM_PFX(gSmmJmpAddr)
29 global ASM_PFX(gSmmInitStack)
30 global ASM_PFX(gcSmiInitGdtr)
31 global ASM_PFX(gcSmmInitSize)
32 global ASM_PFX(gcSmmInitTemplate)
33 global ASM_PFX(mRebasedFlagAddr32)
34 global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
39 ASM_PFX(gcSmiInitGdtr):
43 global ASM_PFX(SmmStartup)
45 DB 0x66, 0xb8 ; mov eax, imm32
46 ASM_PFX(gSmmCr3): DD 0
49 lgdt [ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
50 DB 0x66, 0xb8 ; mov eax, imm32
51 ASM_PFX(gSmmCr4): DD 0
52 or ah, 2 ; enable XMM registers access
55 mov ecx, 0xc0000080 ; IA32_EFER MSR
57 or ah, 1 ; set LME bit
59 DB 0x66, 0xb8 ; mov eax, imm32
60 ASM_PFX(gSmmCr0): DD 0
61 mov cr0, rax ; enable protected mode & paging
62 DB 0x66, 0xea ; far jmp to long mode
63 ASM_PFX(gSmmJmpAddr): DQ @LongMode
64 @LongMode: ; long-mode starts here
65 DB 0x48, 0xbc ; mov rsp, imm64
66 ASM_PFX(gSmmInitStack): DQ 0
67 and sp, 0xfff0 ; make sure RSP is 16-byte aligned
69 ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
70 ; them before calling C-function.
74 movdqa [rsp + 0x10], xmm1
75 movdqa [rsp + 0x20], xmm2
76 movdqa [rsp + 0x30], xmm3
77 movdqa [rsp + 0x40], xmm4
78 movdqa [rsp + 0x50], xmm5
81 call ASM_PFX(SmmInitHandler)
85 ; Restore XMM0~5 after calling C-function.
88 movdqa xmm1, [rsp + 0x10]
89 movdqa xmm2, [rsp + 0x20]
90 movdqa xmm3, [rsp + 0x30]
91 movdqa xmm4, [rsp + 0x40]
92 movdqa xmm5, [rsp + 0x50]
97 ASM_PFX(gcSmmInitTemplate):
98 mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
102 DQ ASM_PFX(SmmStartup)
104 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
107 global ASM_PFX(SmmRelocationSemaphoreComplete)
108 ASM_PFX(SmmRelocationSemaphoreComplete):
110 mov rax, [ASM_PFX(mRebasedFlag)]
113 jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
116 ; Semaphore code running in 32-bit mode
118 global ASM_PFX(SmmRelocationSemaphoreComplete32)
119 ASM_PFX(SmmRelocationSemaphoreComplete32):
124 ASM_PFX(mRebasedFlagAddr32): dd 0
130 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0