Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl

   1 /*-----------------------------------------------------------------------------
   2 -------------------------------------------------------------------------------
   3
   4
   5  Intel Silvermont Processor Power Management BIOS Reference Code
   6
   7  Copyright (c) 2006 - 2014, Intel Corporation
   8
   9   SPDX-License-Identifier: BSD-2-Clause-Patent
  10
  11
  12  Filename:      APIST.ASL
  13
  14  Revision:      Refer to Readme
  15
  16  Date:          Refer to Readme
  17
  18 --------------------------------------------------------------------------------
  19 -------------------------------------------------------------------------------
  20
  21  This Processor Power Management BIOS Source Code is furnished under license
  22  and may only be used or copied in accordance with the terms of the license.
  23  The information in this document is furnished for informational use only, is
  24  subject to change without notice, and should not be construed as a commitment
  25  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  26  for any errors or inaccuracies that may appear in this document or any
  27  software that may be provided in association with this document.
  28
  29  Except as permitted by such license, no part of this document may be
  30  reproduced, stored in a retrieval system, or transmitted in any form or by
  31  any means without the express written consent of Intel Corporation.
  32
  33  WARNING: You are authorized and licensed to install and use this BIOS code
  34  ONLY on an IST PC. This utility may damage any system that does not
  35  meet these requirements.
  36
  37         An IST PC is a computer which
  38         (1) Is capable of seamlessly and automatically transitioning among
  39         multiple performance states (potentially operating at different
  40         efficiency ratings) based upon power source changes, END user
  41         preference, processor performance demand, and thermal conditions; and
  42         (2) Includes an Intel Pentium II processors, Intel Pentium III
  43         processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  44         Processor-M, Intel Pentium M Processor, or any other future Intel
  45         processors that incorporates the capability to transition between
  46         different performance states by altering some, or any combination of,
  47         the following processor attributes: core voltage, core frequency, bus
  48         frequency, number of processor cores available, or any other attribute
  49         that changes the efficiency (instructions/unit time-power) at which the
  50         processor operates.
  51
  52 -------------------------------------------------------------------------------
  53 -------------------------------------------------------------------------------
  54
  55 NOTES:
  56         (1) <TODO> - IF the trap range and port definitions do not match those
  57         specified by this reference code, this file must be modified IAW the
  58         individual implmentation.
  59
  60 --------------------------------------------------------------------------------
  61 ------------------------------------------------------------------------------*/
  62
  63
  64 DefinitionBlock (
  65         "APIST.aml",
  66         "SSDT",
  67         1,
  68         "PmRef",
  69         "ApIst",
  70         0x3000
  71         )
  72 {
  73         External(\_PR.CPU0._PSS, MethodObj)
  74         External(\_PR.CPU0._PCT, MethodObj)
  75         External(\_PR.CPU0._PPC, IntObj)
  76         External(\_PR.CPU0._PSD, MethodObj)
  77         External(\_PR.CPU1, DeviceObj)
  78         External(\_PR.CPU2, DeviceObj)
  79         External(\_PR.CPU3, DeviceObj)
  80         External (CFGD)
  81         External (PDC0)
  82
  83         Scope(\_PR.CPU1)
  84         {
  85                 Method(_PPC,0)
  86                 {
  87                         Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
  88                 }
  89
  90                 Method(_PCT,0)
  91                 {
  92                         Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
  93                 }
  94
  95                 Method(_PSS,0)
  96                 {
  97                         //Return the same table as CPU0 for CMP cases.
  98                         Return(\_PR.CPU0._PSS)
  99                 }
 100
 101                 // The _PSD object provides information to the OSPM related
 102                 // to P-State coordination between processors in a multi-processor
 103                 // configurations.
 104                 //
 105                 Method(_PSD,0)
 106                 {
 107                         Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
 108                 }
 109         }
 110
 111         Scope(\_PR.CPU2)
 112         {
 113                 Method(_PPC,0)
 114                 {
 115                         Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
 116                 }
 117
 118                 Method(_PCT,0)
 119                 {
 120                         Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
 121                 }
 122
 123                 Method(_PSS,0)
 124                 {
 125                         //Return the same table as CPU0 for CMP cases.
 126                         Return(\_PR.CPU0._PSS)
 127                 }
 128
 129                 // The _PSD object provides information to the OSPM related
 130                 // to P-State coordination between processors in a multi-processor
 131                 // configurations.
 132                 //
 133                 Method(_PSD,0)
 134                 {
 135                         Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
 136                 }
 137         }
 138
 139         Scope(\_PR.CPU3)
 140         {
 141                 Method(_PPC,0)
 142                 {
 143                         Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
 144                 }
 145
 146                 Method(_PCT,0)
 147                 {
 148                         Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
 149                 }
 150
 151                 Method(_PSS,0)
 152                 {
 153                         //Return the same table as CPU0 for CMP cases.
 154                         Return(\_PR.CPU0._PSS)
 155                 }
 156
 157                 // The _PSD object provides information to the OSPM related
 158                 // to P-State coordination between processors in a multi-processor
 159                 // configurations.
 160                 //
 161                 Method(_PSD,0)
 162                 {
 163                         Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
 164                 }
 165         }
 166 } // End of Definition Block