Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl

   1
   2 /*-----------------------------------------------------------------------------
   3 -------------------------------------------------------------------------------
   4
   5
   6  Intel Silvermont Processor Power Management BIOS Reference Code
   7
   8  Copyright (c) 2006 - 2014, Intel Corporation
   9
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12
  13  Filename:    CPU0CST.ASL
  14
  15  Revision:    Refer to Readme
  16
  17  Date:        Refer to Readme
  18
  19 --------------------------------------------------------------------------------
  20 -------------------------------------------------------------------------------
  21
  22  This Processor Power Management BIOS Source Code is furnished under license
  23  and may only be used or copied in accordance with the terms of the license.
  24  The information in this document is furnished for informational use only, is
  25  subject to change without notice, and should not be construed as a commitment
  26  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  27  for any errors or inaccuracies that may appear in this document or any
  28  software that may be provided in association with this document.
  29
  30  Except as permitted by such license, no part of this document may be
  31  reproduced, stored in a retrieval system, or transmitted in any form or by
  32  any means without the express written consent of Intel Corporation.
  33
  34  WARNING: You are authorized and licensed to install and use this BIOS code
  35  ONLY on an IST PC. This utility may damage any system that does not
  36  meet these requirements.
  37
  38     An IST PC is a computer which
  39     (1) Is capable of seamlessly and automatically transitioning among
  40     multiple performance states (potentially operating at different
  41     efficiency ratings) based upon power source changes, END user
  42     preference, processor performance demand, and thermal conditions; and
  43     (2) Includes an Intel Pentium II processors, Intel Pentium III
  44     processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  45     Processor-M, Intel Pentium M Processor, or any other future Intel
  46     processors that incorporates the capability to transition between
  47     different performance states by altering some, or any combination of,
  48     the following processor attributes: core voltage, core frequency, bus
  49     frequency, number of processor cores available, or any other attribute
  50     that changes the efficiency (instructions/unit time-power) at which the
  51     processor operates.
  52
  53 -------------------------------------------------------------------------------
  54 -------------------------------------------------------------------------------
  55
  56 NOTES:
  57     (1) <TODO> - IF the trap range and port definitions do not match those
  58     specified by this reference code, this file must be modified IAW the
  59     individual implmentation.
  60
  61 --------------------------------------------------------------------------------
  62 ------------------------------------------------------------------------------*/
  63
  64
  65 DefinitionBlock (
  66     "CPU0CST.aml",
  67     "SSDT",
  68     1,
  69     "PmRef",
  70     "Cpu0Cst",
  71     0x3001
  72     )
  73 {
  74     External(\_PR.CPU0, DeviceObj)
  75     External(PWRS)
  76     External(CFGD)
  77     External(PDC0)
  78
  79     Scope(\_PR.CPU0)
  80     {
  81         OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG
  82         Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG
  83         { DBG8, 8,}                    //DBG
  84
  85         Method (_CST, 0)
  86         {
  87             Store(0x60,DBG8) //DBG
  88
  89             // IF CMP is supported, but independent C-States beyond C1 are
  90             // not supported; return C1 Halt and rely on BIOS based software
  91             // coordination
  92             //
  93             //   CFGD[24] = CMP support
  94             //   PDCx[4]  = 0 - OS does not support ind. C2/C3 in MP systems
  95             //
  96             // Note:  SMI will be generated when both processor enter the
  97             // Halt state.
  98             //
  99             If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
 100             {
 101                 Store(0x61,DBG8) //DBG
 102                 Return(Package() {
 103                     1,
 104                     Package()
 105                     {   // C1 halt, but with BIOS coordination
 106                         ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
 107                         1,
 108                         157,
 109                         1000
 110                     }
 111                 })
 112             }
 113
 114             // IF MWAIT extensions are supported, use them.
 115             //
 116             //  IF C6 capable/enabled AND Battery
 117             //        Report MWAIT C1, C2, C6 w/ BM_STS avoidance
 118             //  ELSE IF C4 capable/enabled AND Battery
 119             //        Report MWAIT C1, C2, C4 w/ BM_STS avoidance
 120             //  ELSE IF C3 capable/enabled
 121             //      Report MWAIT C1, C2, C3 w/ BM_STS avoidance
 122             //  ELSE IF C2 capable/enabled
 123             //        Report MWAIT C1, C2
 124             //  ELSE
 125             //        Report MWAIT C1
 126             //
 127             //   CFGD[21] = 1 - MWAIT extensions supported
 128             //   CFGD[13] = 1 - C7  Capable/Enabled
 129             //   CFGD[12] = 1 - C6S Capable/Enabled
 130             //   CFGD[11] = 1 - C6  Capable/Enabled
 131             //   CFGD[7]  = 1 - C4  Capable/Enabled
 132             //   CFGD[5]  = 1 - C3  Capable/Enabled
 133             //   PDCx[9]  = 1 - OS  supports MWAIT extensions
 134             //   PDCx[8]  = 1 - OS  supports MWAIT for C1
 135             //            (Inferred from PDCx[9] = 1.)
 136             //   PDCx[4]  = 1 - OS supports independent C2/C3 in MP systems
 137             //    or
 138             //   NOT CMP  (Inferred from previous check.)
 139             //
 140             If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
 141             {
 142                 //
 143                 // <TODO> The implementor may wish to only report C1-C2
 144                 // when on AC power.  In this case, the IF clause below can
 145                 // be modified to something like:
 146                 //
 147                 // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"
 148                 //
 149                 // Which uses the power state of the system (PWRS) to
 150                 // determine whether to allow deepers states.
 151                 //
 152                 //   IF C7 supported AND on battery
 153                 //    report MWAIT C1, C6, C7
 154                 //
 155                 //   CFGD[13] = C7  Capable/Enabled
 156                 //   CFGD[11] = C6  Capable/Enabled
 157                 //
 158               If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))
 159                 {
 160                     Store(0x77,DBG8) //DBG
 161                     Return( Package()
 162                     {
 163                         3,
 164                         Package()
 165                         {   // C1, MWAIT
 166                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
 167                             1,
 168                             1,
 169                             1000
 170                         },
 171                         Package()
 172                         {
 173                             // C6, MWAIT Extension with Incremental L2 Shrink
 174                             // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
 175                             // C6, MWAIT Extension with No L2 Shrink
 176                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
 177                             2,
 178                             500,
 179                             10
 180                         },
 181                         Package()
 182                         {
 183                             // C7, MWAIT Extension with Full L2 Shrink
 184                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},
 185                             3,
 186                             1500,   //PnP setting, 1.5 ms for worst-case exit latency
 187                             10
 188                         }
 189                     })
 190                 }
 191
 192
 193              If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))
 194                 {
 195                     Store(0x67,DBG8) //DBG
 196                     Return( Package()
 197                     {
 198                         3,
 199                         Package()
 200                         {   // C1, MWAIT
 201                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
 202                             1,
 203                             1,
 204                             1000
 205                         },
 206                         Package()
 207                         {
 208                             // C6, MWAIT Extension with Incremental L2 Shrink
 209                             // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
 210                             // C6 = C6NS, MWAIT Extension with No L2 Shrink
 211                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
 212                             2,
 213                             500,
 214                             10
 215                         },
 216                         Package()
 217                         {
 218
 219                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},
 220                             3,
 221                             1500,   //PnP setting, 1.5 ms for worst-case exit latency
 222                             10
 223                         }
 224                     })
 225                 }
 226
 227                 If(And(CFGD,0x800)) // Setup Max C-State = C6
 228                 {
 229                     Store(0x76,DBG8) //DBG
 230                     Return( Package()
 231                     {
 232                         2,
 233                         Package()
 234                         {   // C1, MWAIT
 235                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
 236                             1,
 237                             1,
 238                             1000
 239                         },
 240                         Package()
 241                         {
 242                             // C6, MWAIT Extension with Incremental L2 Shrink
 243                             // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
 244                             // C6, MWAIT Extension with No L2 Shrink
 245                             ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
 246                             2,
 247                             500,
 248                             10
 249                         }
 250                     })
 251                 }
 252                 //
 253                 // IF no deeper C-States are supported; report MWAIT C1.
 254                 //
 255                 Store(0x71,DBG8) //DBG
 256                 Return(Package()
 257                 {
 258                     1,
 259                     Package()
 260                     {   // C1, MWAIT
 261                         ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
 262                         1,
 263                         1,
 264                         1000
 265                     }
 266                 })
 267             }
 268
 269
 270         }
 271     }
 272 }
 273
 274