Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
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   7
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   9
  10
  11 Module Name:
  12
  13   PlatformBaseAddresses.h
  14
  15 Abstract:
  16
  17
  18
  19 Revision History
  20
  21 ++*/
  22
  23
  24 #ifndef _PLATFORM_BASE_ADDRESSES_H
  25 #define _PLATFORM_BASE_ADDRESSES_H
  26
  27 //
  28 // Define some fixed platform device location information
  29 //
  30
  31 //
  32 // Define platform base
  33 //
  34
  35 //
  36 // SIO
  37 //
  38 #define SIO_BASE_ADDRESS                  0x0680
  39 #define SIO_MONITORING_BASE_ADDRESS       0x0290
  40 #define SIO_BASE_MASK                     0xFFF0
  41 #define WINDBOND_ECIR_BASE_ADDRESS        0x0810
  42 #define SIO_MAILBOX_BASE_ADDRESS          0x0360    // Used by EC controller
  43 #define SIO_EC_CHANNEL2                   0x62      // Used by EC controller for offset 0x62 and 0x66
  44
  45
  46 //
  47 // South Cluster
  48 //
  49 #define ACPI_BASE_ADDRESS                 0x0400
  50 #define GPIO_BASE_ADDRESS                 0x0500
  51 #define SMBUS_BUS_DEV_FUNC                0x1F0300
  52 #define SMBUS_BASE_ADDRESS                0xEFA0     // SMBus IO Base Address
  53 #define SPI_BASE_ADDRESS                  0xFED01000 // SPI Memory Base Address
  54 #define PMC_BASE_ADDRESS                  0xFED03000 // PMC Memory Base Address
  55 #define SMBM_BASE_ADDRESS                 0xFED04000 // SMBus Memory Base Address
  56 #define IO_BASE_ADDRESS                   0xFED0C000 // IO Memory Base Address
  57 #define ILB_BASE_ADDRESS                  0xFED08000 // ILB Memory Base Address
  58 #define HPET_BASE_ADDRESS                 0xFED00000 // HPET Base Address
  59 #define RCBA_BASE_ADDRESS                 0xFED1C000 // Root Complex Base Address
  60 #define MPHY_BASE_ADDRESS                 0xFEF00000 // MPHY Memory Base Address
  61 #define PUNIT_BASE_ADDRESS                0xFED05000 // PUnit Memory Base Address
  62
  63 //
  64 // GPIO GROUP OFFSET
  65 //
  66 #define GPIO_SCORE_OFFSET                 0x0000
  67 #define GPIO_NCORE_OFFSET                 0x1000
  68 #define GPIO_SSUS_OFFSET                  0x2000
  69
  70 //
  71 // MCH/CPU
  72 //
  73 #define DMI_BASE_ADDRESS                  0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10
  74 #define EP_BASE_ADDRESS                   0xFED19000
  75 #define MC_MMIO_BASE                      0xFED14000 // Base Address for MMIO registers
  76
  77 //
  78 // TPM
  79 //
  80 #define TPM_BASE_ADDRESS                  0xFED40000  // Base address for TPM
  81
  82 //
  83 // Local and I/O APIC addresses.
  84 //
  85 #define IO_APIC_ADDRESS                   0xFEC00000
  86 #define IIO_IOAPIC_ADDRESS                0xFEC90000
  87 #define LOCAL_APIC_ADDRESS                0xFEE00000
  88
  89
  90 #endif
  91
  92