5 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
7 SPDX-License-Identifier: BSD-2-Clause-Patent
15 This file defines the EFI SPI PPI which implements the
16 Intel(R) PCH SPI Host Controller Compatibility Interface.
25 #define PEI_SDHC_PPI_GUID \
27 0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \
29 typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI
;
31 #define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
69 UINT32 HighSpeedSupport
: 1; //High speed supported
70 UINT32 V18Support
: 1; //1.8V supported
71 UINT32 V30Support
: 1; //3.0V supported
72 UINT32 V33Support
: 1; //3.3V supported
74 UINT32 BusWidth4
: 1; // 4 bit width
75 UINT32 BusWidth8
: 1; // 8 bit width
77 UINT32 SDMASupport
: 1;
78 UINT32 ADMA2Support
: 1;
85 #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
86 #define PCI_IF_STANDARD_HOST_NO_DMA 0x00
87 #define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
90 //MMIO Registers definition for MMC/SDIO controller
92 #define MMIO_DMAADR 0x00
93 #define MMIO_BLKSZ 0x04
94 #define MMIO_BLKCNT 0x06
95 #define MMIO_CMDARG 0x08
96 #define MMIO_XFRMODE 0x0C
97 #define MMIO_SDCMD 0x0E
98 #define MMIO_RESP 0x10
99 #define MMIO_BUFDATA 0x20
100 #define MMIO_PSTATE 0x24
101 #define MMIO_HOSTCTL 0x28
102 #define MMIO_PWRCTL 0x29
103 #define MMIO_BLKGAPCTL 0x2A
104 #define MMIO_WAKECTL 0x2B
105 #define MMIO_CLKCTL 0x2C
106 #define MMIO_TOCTL 0x2E
107 #define MMIO_SWRST 0x2F
108 #define MMIO_NINTSTS 0x30
109 #define MMIO_ERINTSTS 0x32
110 #define MMIO_NINTEN 0x34
111 #define MMIO_ERINTEN 0x36
112 #define MMIO_NINTSIGEN 0x38
113 #define MMIO_ERINTSIGEN 0x3A
114 #define MMIO_AC12ERRSTS 0x3C
115 #define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2
116 #define MMIO_CAP 0x40
117 #define MMIO_CAP2 0x44 //hphang <- New in VLV2
118 #define MMIO_MCCAP 0x48
119 #define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2
120 #define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2
121 #define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2
122 #define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2
123 #define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2
124 #define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2
125 #define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2
126 #define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2
127 #define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2
128 #define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2
129 #define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2
130 #define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2
131 #define MMIO_SLTINTSTS 0xFC
132 #define MMIO_CTRLRVER 0xFE
133 #define MMIO_SRST 0x1FC
137 (EFIAPI
*EFI_SD_CONTROLLER_PPI_SEND_COMMAND
) (
138 IN PEI_SD_CONTROLLER_PPI
*This
,
139 IN UINT16 CommandIndex
,
141 IN TRANSFER_TYPE DataType
,
142 IN UINT8
*Buffer
, OPTIONAL
143 IN UINT32 BufferSize
,
144 IN RESPONSE_TYPE ResponseType
,
146 OUT UINT32
*ResponseData OPTIONAL
152 Set max clock frequency of the host, the actual frequency
153 may not be the same as MaxFrequency. It depends on
154 the max frequency the host can support, divider, and host
158 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
159 MaxFrequency - Max frequency in HZ
167 (EFIAPI
*EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY
) (
168 IN PEI_SD_CONTROLLER_PPI
*This
,
169 IN UINT32 MaxFrequency
175 Set bus width of the host
178 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
179 BusWidth - Bus width in 1, 4, 8 bits
183 EFI_INVALID_PARAMETER
188 (EFIAPI
*EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH
) (
189 IN PEI_SD_CONTROLLER_PPI
*This
,
198 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
199 SetHostDdrMode - True for DDR Mode set, false for normal mode
203 EFI_INVALID_PARAMETER
208 (EFIAPI
*EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE
) (
209 IN PEI_SD_CONTROLLER_PPI
*This
,
216 Set voltage which could supported by the host.
217 Support 0(Power off the host), 1.8V, 3.0V, 3.3V
219 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
220 Voltage - Units in 0.1 V
224 EFI_INVALID_PARAMETER
229 (EFIAPI
*EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE
) (
230 IN PEI_SD_CONTROLLER_PPI
*This
,
240 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
241 ResetAll - TRUE to reset all
250 (EFIAPI
*EFI_SD_CONTROLLER_PPI_RESET_SD_HOST
) (
251 IN PEI_SD_CONTROLLER_PPI
*This
,
252 IN RESET_TYPE ResetType
261 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
262 Enable - TRUE to enable, FALSE to disable
271 (EFIAPI
*EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD
) (
272 IN PEI_SD_CONTROLLER_PPI
*This
,
279 Find whether these is a card inserted into the slot. If so
280 init the host. If not, return EFI_NOT_FOUND.
283 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
292 (EFIAPI
*EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST
) (
293 IN PEI_SD_CONTROLLER_PPI
*This
302 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
303 BlockLength - card supportes block length
312 (EFIAPI
*EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH
) (
313 IN PEI_SD_CONTROLLER_PPI
*This
,
314 IN UINT32 BlockLength
323 This - Pointer to EFI_SD_HOST_IO_PROTOCOL
324 BlockLength - card supportes block length
333 (EFIAPI
*EFI_SD_CONTROLLER_PPI_SETUP_DEVICE
)(
334 IN PEI_SD_CONTROLLER_PPI
*This
338 // Interface structure for the EFI SD Host I/O Protocol
340 struct _PEI_SD_CONTROLLER_PPI
{
342 HOST_CAPABILITY HostCapability
;
343 EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand
;
344 EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency
;
345 EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth
;
346 EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage
;
347 EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode
;
348 EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost
;
349 EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd
;
350 EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost
;
351 EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength
;
352 EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice
;
354 // Extern the GUID for PPI users.
356 extern EFI_GUID gPeiSdhcPpiGuid
;