2 This PEIM will parse the hoblist from fsp and report them into pei core.
3 This file contains the main entrypoint of the PEIM.
5 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Library\IoLib.h>
19 #include <Library\SerialPortLib.h>
24 #define PCI_LPC_BASE (0x8000F800)
25 #define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
27 #define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
28 #define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes
29 #define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit
30 #define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1
31 #define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure
32 #define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure
34 #define R_PCH_LPC_UART_CTRL 0x80 // UART Control
35 #define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable
37 #define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address
38 #define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control
40 #define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
42 #define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
43 #define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable
44 #define PCIEX_BASE_ADDRESS 0xE0000000
45 #define PCI_EXPRESS_BASE_ADDRESS PCIEX_BASE_ADDRESS
46 #define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
47 #define SB_RCBA 0xfed1c000
60 #define MmPciAddress( Segment, Bus, Device, Function, Register ) \
61 ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
62 (UINTN)(Bus << 20) + \
63 (UINTN)(Device << 15) + \
64 (UINTN)(Function << 12) + \
68 #define DEFAULT_PCI_BUS_NUMBER_PCH 0
69 #define PCI_DEVICE_NUMBER_PCH_LPC 31
70 #define PCI_FUNCTION_NUMBER_PCH_LPC 0
72 #define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code
74 #define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)
75 #define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)
76 #define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)
77 #define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)
78 #define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)
79 #define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)
80 #define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)
81 #define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)
82 #define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)
83 #define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)
84 #define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)
85 #define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)
86 #define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)
87 #define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)
90 Return Pch stepping type
94 @retval PCH_STEPPING Pch stepping type
107 DEFAULT_PCI_BUS_NUMBER_PCH
,
108 PCI_DEVICE_NUMBER_PCH_LPC
,
109 PCI_FUNCTION_NUMBER_PCH_LPC
,
114 case V_PCH_LPC_RID_0
:
115 case V_PCH_LPC_RID_1
:
119 case V_PCH_LPC_RID_2
:
120 case V_PCH_LPC_RID_3
:
124 case V_PCH_LPC_RID_4
:
125 case V_PCH_LPC_RID_5
:
129 case V_PCH_LPC_RID_6
:
130 case V_PCH_LPC_RID_7
:
134 case V_PCH_LPC_RID_8
:
135 case V_PCH_LPC_RID_9
:
139 case V_PCH_LPC_RID_A
:
140 case V_PCH_LPC_RID_B
:
144 case V_PCH_LPC_RID_C
:
145 case V_PCH_LPC_RID_D
:
150 return PchSteppingMax
;
157 Enable legacy decoding on ICH6
161 @retval EFI_SUCCESS Always returns success.
171 // Program and enable PMC Base.
173 IoWrite32 (PCI_IDX
, PCI_LPC_REG(R_PCH_LPC_PMC_BASE
));
174 IoWrite32 (PCI_DAT
, (PMC_BASE_ADDRESS
| B_PCH_LPC_PMC_BASE_EN
));
177 // Enable COM1 for debug message output.
179 MmioAndThenOr32 (PMC_BASE_ADDRESS
+ R_PCH_PMC_GEN_PMCON_1
, (UINT32
) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR
+ B_PCH_PMC_GEN_PMCON_PWROK_FLR
)), BIT24
);
184 if (PchStepping()>= PchB0
)
185 MmioOr8 (ILB_BASE_ADDRESS
+ R_PCH_ILB_IRQE
, (UINT8
) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4
);
187 MmioOr8 (ILB_BASE_ADDRESS
+ R_PCH_ILB_IRQE
, (UINT8
) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3
);
188 MmioAnd32(IO_BASE_ADDRESS
+ 0x0520, (UINT32
)~(0x00000187));
189 MmioOr32 (IO_BASE_ADDRESS
+ 0x0520, (UINT32
)0x81); // UART3_RXD-L
190 MmioAnd32(IO_BASE_ADDRESS
+ 0x0530, (UINT32
)~(0x00000007));
191 MmioOr32 (IO_BASE_ADDRESS
+ 0x0530, (UINT32
)0x1); // UART3_RXD-L
192 MmioOr8 (PciD31F0RegBase
+ R_PCH_LPC_UART_CTRL
, (UINT8
) B_PCH_LPC_UART_CTRL_COM1_EN
);
194 SerialPortInitialize ();
195 SerialPortWrite ("EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);