Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9
  10 Module Name:
  11
  12   PlatformCpuInfo.h
  13
  14 Abstract:
  15
  16   GUID used for Platform CPU Info Data entries in the HOB list.
  17
  18 --*/
  19
  20 #ifndef _PLATFORM_CPU_INFO_GUID_H_
  21 #define _PLATFORM_CPU_INFO_GUID_H_
  22
  23 #include "CpuType.h"
  24 #include <Library/CpuIA32.h>
  25
  26 #define EFI_PLATFORM_CPU_INFO_GUID \
  27   {\
  28     0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \
  29   }
  30
  31 extern EFI_GUID gEfiPlatformCpuInfoGuid;
  32 extern CHAR16   EfiPlatformCpuInfoVariable[];
  33
  34 //
  35 // Tri-state for feature capabilities and enable/disable.
  36 // [0] clear=feature isn't capable
  37 // [0] set  =feature is capable
  38 // [1] clear=feature is disabled
  39 // [1] set  =feature is enabled
  40 //
  41 #define CPU_FEATURES_CAPABLE      BIT0
  42 #define CPU_FEATURES_ENABLE       BIT1
  43
  44 #define MAX_CACHE_DESCRIPTORS     64
  45 #define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
  46
  47 #pragma pack(1)
  48
  49 typedef struct {
  50   UINT32              FullCpuId;                // [31:0] & 0x0FFF0FFF
  51   UINT32              FullFamilyModelId;        // [31:0] & 0x0FFF0FF0
  52   UINT8               ExtendedFamilyId;         // [27:20]
  53   UINT8               ExtendedModelId;          // [19:16]
  54   UINT8               ProcessorType;            // [13:11]
  55   UINT8               FamilyId;                 // [11:8]
  56   UINT8               Model;                    // [7:4]
  57   UINT8               SteppingId;               // [3:0]
  58 } EFI_CPU_VERSION_INFO; // CPUID.1.EAX
  59
  60 typedef struct {
  61   UINT32              L1InstructionCacheSize;
  62   UINT32              L1DataCacheSize;
  63   UINT32              L2CacheSize;
  64   UINT32              L3CacheSize;
  65   UINT32              TraceCacheSize;
  66   UINT8               CacheDescriptor[MAX_CACHE_DESCRIPTORS];
  67 } EFI_CPU_CACHE_INFO; // CPUID.2.EAX
  68
  69 typedef struct {
  70   UINT8               PhysicalPackages;
  71   UINT8               LogicalProcessorsPerPhysicalPackage;
  72   UINT8               CoresPerPhysicalPackage;
  73   UINT8               ThreadsPerCore;
  74 } EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
  75
  76 typedef struct {
  77   UINT32              RegEdx;                   // CPUID.5.EAX
  78   UINT8               MaxCState;
  79   UINT8               C0SubCStatesMwait;        // EDX [3:0]
  80   UINT8               C1SubCStatesMwait;        // EDX [7:4]
  81   UINT8               C2SubCStatesMwait;        // EDX [11:8]
  82   UINT8               C3SubCStatesMwait;        // EDX [15:12]
  83   UINT8               C4SubCStatesMwait;        // EDX [19:16]
  84   UINT8               C5SubCStatesMwait;        // EDX [23:20]
  85   UINT8               C6SubCStatesMwait;        // EDX [27:24]
  86   UINT8               C7SubCStatesMwait;        // EDX [31:28]
  87   UINT8               MonitorMwaitSupport;      // ECX [0]
  88   UINT8               InterruptsBreakMwait;     // ECX [1]
  89 } EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
  90
  91 typedef struct {
  92   UINT8               Turbo;                    // EAX [1]
  93   UINT8               PECI;                     // EAX [0]
  94   UINT8               NumIntThresholds;         // EBX [3:0]
  95   UINT8               HwCoordinationFeedback;   // ECX [0]
  96 } EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
  97
  98 //
  99 // IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.
 100 //   - Keep the respective feature entry variable as default value (0x00)
 101 //     if the CPU is not capable for the feature.
 102 //   - Use the specially defined programming convention to update the variable
 103 //     to indicate capable, enable or disable.
 104 //     ie. F_CAPABLE for feature available
 105 //         F_ENABLE for feature enable
 106 //         F_DISABLE for feature disable
 107 //
 108 typedef struct {
 109   EFI_CPUID_REGISTER  Regs;                     // CPUID.1.EAX
 110   UINT8               Xapic;                    // ECX [21]
 111   UINT8               SSE4_2;                   // ECX [20]
 112   UINT8               SSE4_1;                   // ECX [19]
 113   UINT8               Dca;                      // ECX [18]
 114   UINT8               SupSSE3;                  // ECX [9]
 115   UINT8               Tm2;                      // ECX [8]
 116   UINT8               Eist;                     // ECX [7]
 117   UINT8               Lt;                       // ECX [6]
 118   UINT8               Vt;                       // ECX [5]
 119   UINT8               Mwait;                    // ECX [3]
 120   UINT8               SSE3;                     // ECX [0]
 121   UINT8               Tcc;                      // EDX [29]
 122   UINT8               Mt;                       // EDX [28]
 123   UINT8               SSE2;                     // EDX [26]
 124   UINT8               SSE;                      // EDX [25]
 125   UINT8               MMX;                      // EDX [23]
 126   EFI_CPUID_REGISTER  ExtRegs;                  // CPUID.80000001.EAX
 127   UINT8               ExtLahfSahf64;            // ECX [0]
 128   UINT8               ExtIntel64;               // EDX [29]
 129   UINT8               ExtXd;                    // EDX [20]
 130   UINT8               ExtSysCallRet64;          // EDX [11]
 131   UINT16              Ht;                       // CPUID.0B.EAX EBX [15:0]
 132 } EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
 133
 134 typedef struct {
 135   UINT8               PhysicalBits;
 136   UINT8               VirtualBits;
 137 } EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
 138
 139 typedef struct {
 140   UINT8               PlatformID;               // MSR 0x17 [52:50]
 141   UINT32              MicrocodeRevision;        // MSR 0x8B [63:32]
 142   UINT8               MaxEfficiencyRatio;       // MSR 0xCE [47:40]
 143   UINT8               DdrRatioUnlockCap;        // MSR 0xCE [30]
 144   UINT8               TdcTdpLimitsTurbo;        // MSR 0xCE [29]
 145   UINT8               RatioLimitsTurbo;         // MSR 0xCE [28]
 146   UINT8               PreProduction;            // MSR 0xCE [27]
 147   UINT8               DcuModeSelect;            // MSR 0xCE [26]
 148   UINT8               MaxNonTurboRatio;         // MSR 0xCE [15:8]
 149   UINT8               Emrr;                     // MSR 0xFE [12]
 150   UINT8               Smrr;                     // MSR 0xFE [11]
 151   UINT8               VariableMtrrCount;        // MSR 0xFE [7:0]
 152   UINT16              PState;                   // MSR 0x198 [15:0]
 153   UINT8               TccActivationTemperature; // MSR 0x1A2 [23:16]
 154   UINT8               TemperatureControlOffset; // MSR 0x1A2 [15:8]
 155   UINT32              PCIeBar;                  // MSR 0x300 [39:20]
 156   UINT8               PCIeBarSizeMB;            // MSR 0x300 [3:1]
 157 } EFI_MSR_FEATURES;
 158
 159 typedef struct {
 160   BOOLEAN                            IsIntelProcessor;
 161   UINT8                              BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
 162   UINT32                             CpuidMaxInputValue;
 163   UINT32                             CpuidMaxExtInputValue;
 164   EFI_CPU_UARCH                      CpuUarch;
 165   EFI_CPU_FAMILY                     CpuFamily;
 166   EFI_CPU_PLATFORM                   CpuPlatform;
 167   EFI_CPU_TYPE                       CpuType;
 168   EFI_CPU_VERSION_INFO               CpuVersion;
 169   EFI_CPU_CACHE_INFO                 CpuCache;
 170   EFI_CPU_FEATURES                   CpuFeatures;
 171   EFI_CPU_CSTATE_INFO                CpuCState;
 172   EFI_CPU_PACKAGE_INFO               CpuPackage;
 173   EFI_CPU_POWER_MANAGEMENT           CpuPowerManagement;
 174   EFI_CPU_ADDRESS_BITS               CpuAddress;
 175   EFI_MSR_FEATURES                   Msr;
 176 } EFI_PLATFORM_CPU_INFO;
 177
 178 #pragma pack()
 179
 180 #endif