3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 GUID used for Platform Info Data entries in the HOB list.
26 #ifndef _PLATFORM_INFO_GUID_H_
27 #define _PLATFORM_INFO_GUID_H_
32 #include <Library/HobLib.h>
33 #include <Library/IoLib.h>
34 #include <Library/DebugLib.h>
35 #include <Library/SmbusLib.h>
36 #include <IndustryStandard/SmBus.h>
39 #define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.
42 // Start::BayLake Board Defines
44 #define BOARD_REVISION_DEFAULT = 0xff
45 #define UNKNOWN_FABID 0x0F
46 #define FAB_ID_MASK 0x0F
47 #define BOARD_ID_2 0x01
48 #define BOARD_ID_1 0x40
49 #define BOARD_ID_0 0x04
51 #define BOARD_ID_DT_CRB 0x0
52 #define BOARD_ID_DT_VLVR 0x1
53 #define BOARD_ID_SVP_VLV 0xC
54 #define BOARD_ID_SVP_EV_VLV 0xD
56 // End::BayLake Board Defines
60 // Start::Alpine Valley Board Defines
62 #define DC_ID_DDR3L 0x00
63 #define DC_ID_DDR3 0x04
64 #define DC_ID_LPDDR3 0x02
65 #define DC_ID_LPDDR2 0x06
66 #define DC_ID_DDR4 0x01
67 #define DC_ID_DDR3L_ECC 0x05
68 #define DC_ID_NO_MEM 0x07
70 // End::Alpine Valley Board Defines
73 #define MAX_FAB_ID_RETRY_COUNT 100
74 #define MAX_FAB_ID_CHECK_COUNT 3
76 #define PLATFORM_INFO_HOB_REVISION 0x1
78 #define EFI_PLATFORM_INFO_GUID \
80 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
83 extern EFI_GUID gEfiPlatformInfoGuid
;
107 UINT16 PciResourceIoBase
;
108 UINT16 PciResourceIoLimit
;
109 UINT32 PciResourceMem32Base
;
110 UINT32 PciResourceMem32Limit
;
111 UINT64 PciResourceMem64Base
;
112 UINT64 PciResourceMem64Limit
;
113 UINT64 PciExpressBase
;
114 UINT32 PciExpressSize
;
115 UINT8 PciHostAddressWidth
;
116 UINT8 PciResourceMinSecBus
;
117 } EFI_PLATFORM_PCI_DATA
;
120 UINT8 CpuAddressWidth
;
121 UINT32 CpuFamilyStepping
;
122 } EFI_PLATFORM_CPU_DATA
;
125 UINT8 SysIoApicEnable
;
127 } EFI_PLATFORM_SYS_DATA
;
137 UINT32 MemIgdGttSize
;
138 UINT32 MemIgdGttBase
;
141 UINT32 MemConfigSize
;
149 } EFI_PLATFORM_MEM_DATA
;
153 UINT32 IgdOpRegionAddress
; // IGD OpRegion Starting Address
154 UINT8 IgdBootType
; // IGD Boot Display Device
155 UINT8 IgdPanelType
; // IGD Panel Type CMOs option
156 UINT8 IgdTvFormat
; // IGD TV Format CMOS option
157 UINT8 IgdTvMinor
; // IGD TV Minor Format CMOS option
158 UINT8 IgdPanelScaling
; // IGD Panel Scaling
159 UINT8 IgdBlcConfig
; // IGD BLC Configuration
160 UINT8 IgdBiaConfig
; // IGD BIA Configuration
161 UINT8 IgdSscConfig
; // IGD SSC Configuration
162 UINT8 IgdDvmtMemSize
; // IGD DVMT Memory Size
163 UINT8 IgdFunc1Enable
; // IGD Function 1 Enable
164 UINT8 IgdHpllVco
; // HPLL VCO
165 UINT8 IgdSciSmiMode
; // GMCH SMI/SCI mode (0=SCI)
166 UINT8 IgdPAVP
; // IGD PAVP data
167 } EFI_PLATFORM_IGD_DATA
;
170 BOARD_ID_AV_SVP
= 0x0, // Alpine Valley Board
171 BOARD_ID_BL_RVP
= 0x2, // BayLake Board (RVP)
172 BOARD_ID_BL_FFRD8
= 0x3, // FFRD8 b'0011
173 BOARD_ID_BL_FFRD
= 0x4, // BayLake Board (FFRD)
174 BOARD_ID_BL_RVP_DDR3L
= 0x5, // BayLake Board (RVP DDR3L)
175 BOARD_ID_BL_STHI
= 0x7, // PPV- STHI Board
176 BOARD_ID_BB_RVP
= 0x20, // Bayley Bay Board
177 BOARD_ID_BS_RVP
= 0x30, // Bakersport Board
178 BOARD_ID_CVH
= 0x90, // Crestview Hills
179 BOARD_ID_MINNOW2
= 0xA0, // MinnowBorad Max
180 BOARD_ID_MINNOW2_TURBOT
= 0xB0 // MinnowBoard Turbot
192 PR05
= 1, // FFRD PR0.3 and PR 0.5
194 PR11
= 3 // FFRD PR1.1
199 // VLV2 GPIO GROUP OFFSET
201 #define GPIO_SCORE_OFFSET 0x0000
202 #define GPIO_NCORE_OFFSET 0x1000
203 #define GPIO_SSUS_OFFSET 0x2000
206 // GPIO Initialization Data Structure for BayLake.
207 // SC = SCORE, SS= SSUS
208 // Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
245 // CFIO PAD configuration Registers
253 UINT32 Func_Pin_Mux
:3; // 0:2 Function of CFIO selection
254 UINT32 ipslew
:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
255 UINT32 inslew
:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
256 UINT32 Pull_assign
:2; // 7:8 Pull assignment
257 UINT32 Pull_strength
:2; // 9:10 Pull strength
258 UINT32 Bypass_flop
:1; // 11 Bypass flop
259 UINT32 Filter_en
:1; // 12 Filter Enable
260 UINT32 Hist_ctrl
:2; // 13:14 hysteresis control
261 UINT32 Hist_enb
:1; // 15 Hysteresis enable, active low
262 UINT32 Delay_line
:6; // 16:21 Delay line values - Delay values for input or output
263 UINT32 Reserved
:3; // 22:24 Reserved
264 UINT32 TPE
:1; // 25 Trigger Positive Edge Enable
265 UINT32 TNE
:1; // 26 Trigger Negative Edge Enable
266 UINT32 Reserved2
:3; // 27:29 Reserved
267 UINT32 i1p5sel
:1; // 30
268 UINT32 IODEN
:1; // 31 : Open Drain enable. Active high
275 UINT32 instr
:16; // 0:15 Pad (N) strength.
276 UINT32 ipstr
:16; // 16:31 Pad (P) strength.
283 UINT32 pad_val
:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
284 UINT32 ioutenb
:1; // 1 output enable
285 UINT32 iinenb
:1; // 2 input enable
286 UINT32 Reserved
:29; // 3:31 Reserved
293 UINT32 ihbpen
:1; // 0 Pad high by pass enable
294 UINT32 ihbpinen
:1; // 1 Pad high by pass input
295 UINT32 instaticen
:1; // 2 TBD
296 UINT32 ipstaticen
:1; // 3 TBD
297 UINT32 Overide_strap_pin
:1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
298 UINT32 Overide_strap_pin_val
:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
299 UINT32 TestMode_Pin_Mux
:3; // 6:9 DFX Pin Muxing
304 // GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
307 Native
= 0xFF, // Native, no need to set PAD_VALUE
308 GPI
= 2, // GPI, input only in PAD_VALUE
309 GPO
= 4, // GPO, output only in PAD_VALUE
310 GPIO
= 0, // GPIO, input & output
311 TRISTS
= 6, // Tri-State
333 // Mapping to CONF0 bit 27:24
334 // Note: Assume "Direct Irq En" is not set, unless specially notified.
338 TRIG_Edge_High
= /*BIT3 |*/ BIT1
, // Positive Edge (Rasing)
339 TRIG_Edge_Low
= /*BIT3 |*/ BIT2
, // Negative Edge (Falling)
340 TRIG_Edge_Both
= /*BIT3 |*/ BIT2
| BIT1
, // Both Edge
341 TRIG_Level_High
= /*BIT3 |*/ BIT1
| BIT0
, // Level High
342 TRIG_Level_Low
= /*BIT3 |*/ BIT2
| BIT0
, // Level Low
346 P_20K_H
, // Pull Up 20K
347 P_20K_L
, // Pull Down 20K
348 P_10K_H
, // Pull Up 10K
349 P_10K_L
, // Pull Down 10K
350 P_2K_H
, // Pull Up 2K
351 P_2K_L
, // Pull Down 2K
356 #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
358 #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
362 // GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
363 // NC = NCORE, SC = SCORE, SS= SSUS
368 char pad_name
[32];// GPIO Pin Name for debug purpose
371 GPIO_USAGE usage
; // GPIO pin used as Native mode or GPI/GPO/GPIO mode
372 GPO_D4 gpod4
; // GPO default value
373 GPIO_FUNC_NUM func
; // Function Number (F0~F7)
374 INT_TYPE int_type
; // Edge or Level trigger, low or high active
375 PULL_TYPE pull
; // Pull Up or Down
376 UINT8 offset
; // Equal with (PCONF0 register offset >> 4 bits)
377 } GPIO_CONF_PAD_INIT
;
380 //typedef UINT64 BOARD_FEATURES
382 typedef struct _EFI_PLATFORM_INFO_HOB
{
383 UINT16 PlatformType
; // Platform Type
384 UINT8 BoardId
; // Board ID
385 UINT8 BoardRev
; // Board Revision
386 PLATFORM_FLAVOR PlatformFlavor
; // Platform Flavor
387 UINT8 DDRDaughterCardCh0Id
;// DDR daughter card channel 0 id
388 UINT8 DDRDaughterCardCh1Id
;// DDR daughter card channel 1 id
389 UINT8 ECOId
; // ECO applied on platform
394 EFI_PLATFORM_PCI_DATA PciData
;
395 EFI_PLATFORM_CPU_DATA CpuData
;
396 EFI_PLATFORM_MEM_DATA MemData
;
397 EFI_PLATFORM_SYS_DATA SysData
;
398 EFI_PLATFORM_IGD_DATA IgdData
;
399 UINT8 RevisonId
; // Structure Revision ID
400 EFI_PHYSICAL_ADDRESS PlatformCfioData
;
401 EFI_PHYSICAL_ADDRESS PlatformGpioData_NC
;
402 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC
;
403 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS
;
404 EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI
;
405 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI
;
406 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI
;
407 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1
;
408 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1
;
409 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1
;
413 UINT16 AudioSubsystemDeviceId
;
415 UINT64 AcpiOemTableId
;
417 } EFI_PLATFORM_INFO_HOB
;
423 IN CONST EFI_PEI_SERVICES
**PeiServices
,
424 OUT EFI_PLATFORM_INFO_HOB
**PlatformInfoHob
429 InstallPlatformClocksNotify (
430 IN CONST EFI_PEI_SERVICES
**PeiServices
434 InstallPlatformSysCtrlGPIONotify (
435 IN CONST EFI_PEI_SERVICES
**PeiServices