Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9
  10
  11 Module Name:
  12
  13   PlatformInfo.h
  14
  15 Abstract:
  16
  17   GUID used for Platform Info Data entries in the HOB list.
  18
  19 --*/
  20
  21 #ifndef _PLATFORM_INFO_GUID_H_
  22 #define _PLATFORM_INFO_GUID_H_
  23
  24 #ifndef ECP_FLAG
  25 #include <PiPei.h>
  26
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/DebugLib.h>
  30 #include <Library/SmbusLib.h>
  31 #include <IndustryStandard/SmBus.h>
  32 #endif
  33
  34 #define PLATFORM_INFO_REVISION = 1      // Revision id for current platform information struct.
  35
  36 //
  37 // Start::BayLake Board Defines
  38 //
  39 #define BOARD_REVISION_DEFAULT = 0xff
  40 #define UNKNOWN_FABID           0x0F
  41 #define FAB_ID_MASK                     0x0F
  42 #define BOARD_ID_2   0x01
  43 #define BOARD_ID_1   0x40
  44 #define BOARD_ID_0   0x04
  45
  46 #define BOARD_ID_DT_CRB     0x0
  47 #define BOARD_ID_DT_VLVR    0x1
  48 #define BOARD_ID_SVP_VLV    0xC
  49 #define BOARD_ID_SVP_EV_VLV 0xD
  50 //
  51 // End::BayLake Board Defines
  52 //
  53
  54 //
  55 // Start::Alpine Valley Board Defines
  56 //
  57 #define DC_ID_DDR3L      0x00
  58 #define DC_ID_DDR3       0x04
  59 #define DC_ID_LPDDR3     0x02
  60 #define DC_ID_LPDDR2     0x06
  61 #define DC_ID_DDR4       0x01
  62 #define DC_ID_DDR3L_ECC  0x05
  63 #define DC_ID_NO_MEM     0x07
  64 //
  65 // End::Alpine Valley Board Defines
  66 //
  67
  68 #define MAX_FAB_ID_RETRY_COUNT  100
  69 #define MAX_FAB_ID_CHECK_COUNT  3
  70
  71 #define PLATFORM_INFO_HOB_REVISION      0x1
  72
  73 #define EFI_PLATFORM_INFO_GUID \
  74   { \
  75     0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
  76   }
  77
  78 extern EFI_GUID gEfiPlatformInfoGuid;
  79
  80 typedef enum {
  81   FlavorUnknown = 0,
  82
  83   //
  84   // Mobile
  85   //
  86   FlavorMobile = 1,
  87
  88   //
  89   // Desktop
  90   //
  91   FlavorDesktop = 2,
  92
  93   //
  94   // Tablet
  95   //
  96   FlavorTablet = 3
  97 } PLATFORM_FLAVOR;
  98
  99 #pragma pack(1)
 100
 101 typedef struct {
 102   UINT16  PciResourceIoBase;
 103   UINT16  PciResourceIoLimit;
 104   UINT32  PciResourceMem32Base;
 105   UINT32  PciResourceMem32Limit;
 106   UINT64  PciResourceMem64Base;
 107   UINT64  PciResourceMem64Limit;
 108   UINT64  PciExpressBase;
 109   UINT32  PciExpressSize;
 110   UINT8   PciHostAddressWidth;
 111   UINT8   PciResourceMinSecBus;
 112 } EFI_PLATFORM_PCI_DATA;
 113
 114 typedef struct {
 115   UINT8 CpuAddressWidth;
 116   UINT32 CpuFamilyStepping;
 117 } EFI_PLATFORM_CPU_DATA;
 118
 119 typedef struct {
 120   UINT8 SysIoApicEnable;
 121   UINT8 SysSioExist;
 122 } EFI_PLATFORM_SYS_DATA;
 123
 124 typedef struct {
 125   UINT32  MemTolm;
 126   UINT32  MemMaxTolm;
 127   UINT32  MemTsegSize;
 128   UINT32  MemTsegBase;
 129   UINT32  MemIedSize;
 130   UINT32  MemIgdSize;
 131   UINT32  MemIgdBase;
 132   UINT32  MemIgdGttSize;
 133   UINT32  MemIgdGttBase;
 134   UINT64  MemMir0;
 135   UINT64  MemMir1;
 136   UINT32  MemConfigSize;
 137   UINT16  MmioSize;
 138   UINT8   DdrFreq;
 139   UINT8   DdrType;
 140   UINT32  MemSize;
 141   BOOLEAN EccSupport;
 142   UINT8   Reserved[3];
 143   UINT16  DimmSize[2];
 144 } EFI_PLATFORM_MEM_DATA;
 145
 146
 147 typedef struct {
 148   UINT32 IgdOpRegionAddress;    // IGD OpRegion Starting Address
 149   UINT8  IgdBootType;           // IGD Boot Display Device
 150   UINT8  IgdPanelType;          // IGD Panel Type CMOs option
 151   UINT8  IgdTvFormat;           // IGD TV Format CMOS option
 152   UINT8  IgdTvMinor;            // IGD TV Minor Format CMOS option
 153   UINT8  IgdPanelScaling;       // IGD Panel Scaling
 154   UINT8  IgdBlcConfig;          // IGD BLC Configuration
 155   UINT8  IgdBiaConfig;          // IGD BIA Configuration
 156   UINT8  IgdSscConfig;          // IGD SSC Configuration
 157   UINT8  IgdDvmtMemSize;        // IGD DVMT Memory Size
 158   UINT8  IgdFunc1Enable;        // IGD Function 1 Enable
 159   UINT8  IgdHpllVco;            // HPLL VCO
 160   UINT8  IgdSciSmiMode;         // GMCH SMI/SCI mode (0=SCI)
 161   UINT8  IgdPAVP;               // IGD PAVP data
 162 } EFI_PLATFORM_IGD_DATA;
 163
 164 typedef enum {
 165   BOARD_ID_AV_SVP   = 0x0,    // Alpine Valley Board
 166   BOARD_ID_BL_RVP   = 0x2,    // BayLake Board (RVP)
 167   BOARD_ID_BL_FFRD8 = 0x3,    // FFRD8 b'0011
 168   BOARD_ID_BL_FFRD  = 0x4,    // BayLake Board (FFRD)
 169   BOARD_ID_BL_RVP_DDR3L  = 0x5,    // BayLake Board (RVP DDR3L)
 170   BOARD_ID_BL_STHI  = 0x7,    // PPV- STHI Board
 171   BOARD_ID_BB_RVP   = 0x20,   // Bayley Bay Board
 172   BOARD_ID_BS_RVP   = 0x30,   // Bakersport Board
 173   BOARD_ID_CVH      = 0x90,   // Crestview Hills
 174   BOARD_ID_MINNOW2  = 0xA0,    // MinnowBorad Max
 175   BOARD_ID_MINNOW2_TURBOT  = 0xB0    // MinnowBoard Turbot
 176
 177 } BOARD_ID_LIST;
 178
 179 typedef enum {
 180   FAB1 = 0,
 181   FAB2 = 1,
 182   FAB3 = 2
 183 } FAB_ID_LIST;
 184
 185 typedef enum {
 186     PR0  = 0,   // FFRD PR0
 187     PR05 = 1,   // FFRD PR0.3 and PR 0.5
 188     PR1  = 2,   // FFRD PR1
 189     PR11 = 3    // FFRD PR1.1
 190 } FFRD_ID_LIST;
 191
 192
 193 //
 194 // VLV2 GPIO GROUP OFFSET
 195 //
 196 #define GPIO_SCORE_OFFSET       0x0000
 197 #define GPIO_NCORE_OFFSET       0x1000
 198 #define GPIO_SSUS_OFFSET        0x2000
 199
 200 //
 201 // GPIO Initialization Data Structure for BayLake.
 202 // SC = SCORE, SS= SSUS
 203 // Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
 204 //
 205
 206 //
 207 // IO space
 208 //
 209 typedef struct{
 210   UINT32  Use_Sel_SC0;
 211   UINT32  Use_Sel_SC1;
 212   UINT32  Use_Sel_SC2;
 213   UINT32  Use_Sel_SS;
 214
 215   UINT32  Io_Sel_SC0;
 216   UINT32  Io_Sel_SC1;
 217   UINT32  Io_Sel_SC2;
 218   UINT32  Io_Sel_SS;
 219
 220   UINT32  GP_Lvl_SC0;
 221   UINT32  GP_Lvl_SC1;
 222   UINT32  GP_Lvl_SC2;
 223   UINT32  GP_Lvl_SS;
 224
 225   UINT32  TPE_SC0;
 226   UINT32  TPE_SS;
 227
 228   UINT32  TNE_SC0;
 229   UINT32  TNE_SS;
 230
 231   UINT32  TS_SC0;
 232   UINT32  TS_SS;
 233
 234   UINT32  WE_SS;
 235 } CFIO_INIT_STRUCT;
 236
 237
 238
 239 //
 240 // CFIO PAD configuration Registers
 241 //
 242 //
 243 // Memory space
 244 //
 245 typedef union {
 246   UINT32 dw;
 247   struct {
 248     UINT32 Func_Pin_Mux:3;  // 0:2 Function of CFIO selection
 249     UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
 250     UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
 251     UINT32 Pull_assign:2; // 7:8 Pull assignment
 252     UINT32 Pull_strength:2; // 9:10 Pull strength
 253     UINT32 Bypass_flop:1; // 11 Bypass flop
 254     UINT32 Filter_en:1; // 12 Filter Enable
 255     UINT32 Hist_ctrl:2; // 13:14 hysteresis control
 256     UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
 257     UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output
 258     UINT32 Reserved:3; // 22:24 Reserved
 259     UINT32 TPE:1; // 25 Trigger Positive Edge Enable
 260     UINT32 TNE:1; // 26 Trigger Negative Edge Enable
 261     UINT32 Reserved2:3; // 27:29 Reserved
 262     UINT32 i1p5sel:1; // 30
 263     UINT32 IODEN:1; // 31 : Open Drain enable. Active high
 264         } r;
 265 } PAD_CONF0;
 266
 267 typedef union{
 268   UINT32 dw;
 269   struct {
 270     UINT32 instr:16; // 0:15 Pad (N) strength.
 271     UINT32 ipstr:16; // 16:31 Pad (P) strength.
 272   }r;
 273 } PAD_CONF1;
 274
 275 typedef union{
 276   UINT32 dw;
 277   struct {
 278     UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
 279     UINT32 ioutenb:1; // 1 output enable
 280     UINT32 iinenb:1; // 2 input enable
 281     UINT32 Reserved:29; // 3:31 Reserved
 282   }r;
 283 } PAD_VAL;
 284
 285 typedef union{
 286   UINT32 GPI;
 287   struct {
 288     UINT32 ihbpen:1; // 0 Pad high by pass enable
 289     UINT32 ihbpinen:1; // 1 Pad high by pass input
 290     UINT32 instaticen:1; // 2 TBD
 291     UINT32 ipstaticen:1; // 3 TBD
 292     UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
 293     UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
 294     UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
 295   }r;
 296 } PAD_DFT;
 297
 298 //
 299 // GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
 300 //
 301 typedef enum {
 302   Native = 0xFF,  // Native, no need to set PAD_VALUE
 303   GPI = 2,    // GPI, input only in PAD_VALUE
 304   GPO = 4,    // GPO, output only in PAD_VALUE
 305   GPIO = 0,      // GPIO, input & output
 306   TRISTS = 6,      // Tri-State
 307   GPIO_NONE
 308 } GPIO_USAGE;
 309
 310 typedef enum {
 311   LO = 0,
 312   HI = 1,
 313   NA = 0xFF
 314 } GPO_D4;
 315
 316 typedef enum {
 317   F0 = 0,
 318   F1 = 1,
 319   F2 = 2,
 320   F3 = 3,
 321   F4 = 4,
 322   F5 = 5,
 323   F6 = 6,
 324   F7 = 7
 325 } GPIO_FUNC_NUM;
 326
 327 //
 328 // Mapping to CONF0 bit 27:24
 329 // Note: Assume "Direct Irq En" is not set, unless specially notified.
 330 //
 331 typedef enum {
 332   TRIG_ = 0,
 333   TRIG_Edge_High = /*BIT3 |*/ BIT1,     // Positive Edge (Rasing)
 334   TRIG_Edge_Low  = /*BIT3 |*/ BIT2,     // Negative Edge (Falling)
 335   TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1,      // Both Edge
 336   TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0,      // Level High
 337   TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0,      // Level Low
 338 } INT_TYPE;
 339
 340 typedef enum {
 341   P_20K_H,      // Pull Up 20K
 342   P_20K_L,      // Pull Down 20K
 343   P_10K_H,      // Pull Up 10K
 344   P_10K_L,      // Pull Down 10K
 345   P_2K_H,       // Pull Up 2K
 346   P_2K_L,       // Pull Down 2K
 347   P_NONE      // Pull None
 348 } PULL_TYPE;
 349
 350 #ifdef EFI_DEBUG
 351   #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
 352 #else
 353   #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {          usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
 354 #endif
 355
 356 //
 357 // GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
 358 // NC = NCORE, SC = SCORE, SS= SSUS
 359 //
 360 typedef struct {
 361
 362 #ifdef EFI_DEBUG
 363   char         pad_name[32];// GPIO Pin Name for debug purpose
 364 #endif
 365
 366   GPIO_USAGE     usage;     // GPIO pin used as Native mode or GPI/GPO/GPIO mode
 367   GPO_D4         gpod4;     // GPO default value
 368   GPIO_FUNC_NUM  func;      // Function Number (F0~F7)
 369   INT_TYPE       int_type;  // Edge or Level trigger, low or high active
 370   PULL_TYPE      pull;      // Pull Up or Down
 371   UINT8          offset;    // Equal with (PCONF0 register offset >> 4 bits)
 372 } GPIO_CONF_PAD_INIT;
 373
 374 //
 375 //typedef UINT64 BOARD_FEATURES
 376 //
 377 typedef struct _EFI_PLATFORM_INFO_HOB {
 378   UINT16                      PlatformType; // Platform Type
 379   UINT8                       BoardId;             // Board ID
 380   UINT8                       BoardRev;            // Board Revision
 381   PLATFORM_FLAVOR             PlatformFlavor;      // Platform Flavor
 382   UINT8                       DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
 383   UINT8                       DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
 384   UINT8                       ECOId;               // ECO applied on platform
 385   UINT16                      IohSku;
 386   UINT8                       IohRevision;
 387   UINT16                      IchSku;
 388   UINT8                       IchRevision;
 389   EFI_PLATFORM_PCI_DATA       PciData;
 390   EFI_PLATFORM_CPU_DATA       CpuData;
 391   EFI_PLATFORM_MEM_DATA       MemData;
 392   EFI_PLATFORM_SYS_DATA       SysData;
 393   EFI_PLATFORM_IGD_DATA       IgdData;
 394   UINT8                       RevisonId;           // Structure Revision ID
 395   EFI_PHYSICAL_ADDRESS        PlatformCfioData;
 396   EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC;
 397   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC;
 398   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS;
 399   EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC_TRI;
 400   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_TRI;
 401   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_TRI;
 402   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1;
 403   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_PR1_1;
 404   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1_1;
 405
 406   UINT8                       CfioEnabled;
 407   UINT32                      SsidSvid;
 408   UINT16                      AudioSubsystemDeviceId;
 409   UINT64                      AcpiOemId;
 410   UINT64                      AcpiOemTableId;
 411   UINT16                      MemCfgID;
 412 } EFI_PLATFORM_INFO_HOB;
 413
 414 #pragma pack()
 415
 416 EFI_STATUS
 417 GetPlatformInfoHob (
 418   IN CONST EFI_PEI_SERVICES           **PeiServices,
 419   OUT EFI_PLATFORM_INFO_HOB           **PlatformInfoHob
 420   );
 421
 422
 423 EFI_STATUS
 424 InstallPlatformClocksNotify (
 425   IN CONST EFI_PEI_SERVICES           **PeiServices
 426   );
 427
 428 EFI_STATUS
 429 InstallPlatformSysCtrlGPIONotify (
 430   IN CONST EFI_PEI_SERVICES           **PeiServices
 431   );
 432
 433 #endif