Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9 Module Name:
  10
  11   CK505ClockPlatformInfo.h
  12
  13 Abstract:
  14
  15   Protocol to communicate product clock routing information.
  16
  17 GUID Info:
  18  {3C485EA4-449A-46ce-BB08-2A336EA96B4E}
  19  0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e);
  20
  21 **/
  22
  23 #ifndef _CLOCK_PLATFORM_INFO_H_
  24 #define _CLOCK_PLATFORM_INFO_H_
  25
  26
  27 #define EFI_CK505_CLOCK_PLATFORM_INFO_GUID  \
  28   {0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e}
  29
  30 //
  31 // Structure to hold register modifications
  32 //
  33 typedef enum {
  34   None           = 0x00000000,
  35   nICS9LP505_1   = 0x00000001,
  36   nICS9LP505_2   = 0x00000002,
  37   nIDTCV163      = 0x00000004,
  38   nIDTCV174      = 0x00000008,
  39   nSLG505YC56    = 0x00000010,
  40   nSLG505YC64    = 0x00000020,
  41   nCY28505       = 0x00000040,
  42   nCY28505_2     = 0x00000080,
  43   nCY28505LF     = 0x00000100,
  44   nPI6C505_OLD   = 0x00000200,
  45   nPI6C505_RevD  = 0x00000400,
  46   nGENERIC_505   = 0x00000800,
  47   nSLG505YC264   = 0x00001000,
  48   nIDTCV183      = 0x00002000,
  49   nSLG505YC256   = 0x00004000,
  50   nIDTCV184      = 0x00008000,
  51   nIDTCV190      = 0x00010000,
  52   All            = 0xFFFFFFFF
  53 } EFI_CLOCKS_SUPPORTED;
  54
  55 typedef enum {
  56   Disabled,
  57   Enabled,
  58   EnabledWithoutSwitch,
  59   EnabledWithSwitch
  60 } EFI_SIGNAL_STATE;
  61
  62 typedef enum {
  63   SrcClk11,
  64   SrcClk10,
  65   SrcClk9,
  66   SrcClk8,
  67   SrcClk7,
  68   SrcClk6,
  69   SrcClk5,
  70   SrcClk4,
  71   SrcClk3,
  72   SrcClk2,
  73   SrcClk1,
  74   SrcClk0,
  75   CpuClk1,
  76   CpuClk0,
  77   Ref0,
  78   Dot96,
  79   Usb48,
  80   PciClkF5,
  81   PciClk4,
  82   PciClk3,
  83   PciClk2,
  84   PciClk1,
  85   PciClk0,
  86   SaveClockConfiguration,
  87   MePresent,
  88   Cr_A,
  89   Cr_B,
  90   Cr_C,
  91   Cr_D,
  92   Cr_E,
  93   Cr_F,
  94   Cr_G,
  95   Cr_H,
  96   Clk_None // Dummy entry for dynamic detection
  97 } EFI_CLOCK_SIGNAL_NAME;
  98
  99 typedef struct {
 100   EFI_CLOCK_SIGNAL_NAME     Signal;
 101   EFI_SIGNAL_STATE          State;
 102   EFI_CLOCKS_SUPPORTED      Supported;
 103 } EFI_STATIC_SIGNALS;
 104
 105 typedef struct {
 106   BOOLEAN               BehindBridge;
 107   UINT16                BridgeBus;
 108   UINT16                BridgeDev;
 109   UINT16                BridgeFunction;
 110   UINT16                TargetDevice;
 111   EFI_CLOCK_SIGNAL_NAME Signal;
 112 } EFI_DYNAMIC_SIGNALS;
 113
 114
 115 typedef struct {
 116   EFI_STATIC_SIGNALS      *StaticClockTable;
 117   UINTN                   StaticClockTableCount;
 118   EFI_STATIC_SIGNALS      *SxClockTable;
 119   UINTN                   SxClockTableCount;
 120   EFI_STATIC_SIGNALS      *DynamicDisabledClocksTable;
 121   UINTN                   DynamicDisabledClocksTableCount;
 122 } EFI_CLOCK_PLATFORM_INFO;
 123
 124 extern EFI_GUID gEfiCk505ClockPlatformInfoGuid;
 125
 126 #endif