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1 /** @file
2 Multiplatform initialization.
3
4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8
9
10 **/
11
12 #include <MultiPlatformLib.h>
13
14 /**
15 Platform Type detection. Because the PEI globle variable
16 is in the flash, it could not change directly.So use
17 2 PPIs to distinguish the platform type.
18
19 @param FfsHeader Pointer to Firmware File System file header.
20 @param PeiServices General purpose services available to every PEIM.
21
22 @retval EFI_SUCCESS Memory initialization completed successfully.
23 @retval Others All other error conditions encountered result in an ASSERT.
24
25 **/
26 EFI_STATUS
27 MultiPlatformInfoInit (
28 IN CONST EFI_PEI_SERVICES **PeiServices,
29 IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
30 )
31 {
32 UINT32 PcieLength;
33
34
35 PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
36
37 PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);
38
39 //
40 // Update ICH Type
41 //
42 //
43 // Device ID
44 //
45 PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);
46
47 PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);
48
49 //
50 //64MB
51 //
52 PcieLength = 0x04000000;
53
54 //
55 // Don't support BASE above 4GB currently.
56 //
57 PlatformInfoHob->PciData.PciExpressSize = PcieLength;
58 PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);
59
60 PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
61 PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
62
63 PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
64 PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
65 PlatformInfoHob->CpuData.CpuAddressWidth = 36;
66
67 PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
68 PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
69
70 PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
71
72 //
73 // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.
74 //
75 if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
76 PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
77 } else {
78 PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
79 }
80 PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
81
82 //
83 // Platform PCI MMIO Size in unit of 1MB.
84 //
85 PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
86
87 //
88 // Enable ICH IOAPIC
89 //
90 PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
91
92 DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n",
93 PlatformInfoHob->PlatformFlavor,
94 FlavorTablet,
95 FlavorMobile,
96 FlavorDesktop));
97
98 //
99 // Get Platform Info and fill the Hob.
100 //
101 PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
102
103 //
104 // Get GPIO table
105 //
106 MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
107
108 //
109 // Program GPIO
110 //
111 MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
112
113 //
114 // Update OemId
115 //
116 InitializeBoardOemId (PeiServices, PlatformInfoHob);
117 InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
118
119 return EFI_SUCCESS;
120 }