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1 /** @file
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7
8
9 Module Name:
10
11
12 PeiPostCode.c
13
14 Abstract:
15
16 Worker functions for PostCode
17
18 --*/
19
20 #include "EfiStatusCode.h"
21
22 #pragma pack(1)
23 typedef struct {
24 EFI_STATUS_CODE_VALUE StatusValue;
25 UINT8 Port80Value;
26 } EFI_STATUS_CODE_TO_PORT_80;
27 #pragma pack()
28
29 //
30 // see Edk\Foundation\Library\EfiCommonLib\PostCode.c for DXE/BDS POST codes.
31 //
32 EFI_STATUS_CODE_TO_PORT_80 mPeiPort80Table[] = {
33 //
34 // Platform init
35 //
36 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_INIT, 0x11},
37 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP1, 0x12},
38 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP2, 0x13},
39 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP3, 0x14},
40 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP4, 0x15},
41
42 //
43 // SMBUS
44 //
45 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_INIT, 0x16},
46 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_ENTRY, 0x17},
47 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_EXIT, 0x18},
48
49 //
50 // Clock
51 //
52 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY, 0x19},
53 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_EXIT, 0x1A},
54
55 //
56 // Over clocking support
57 //
58 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_ENTRY, 0x1B},
59 {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_EXIT, 0x1C},
60
61 //
62 // MRC
63 //
64 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_INIT_BEGIN, 0x21},
65 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_SPD_READ, 0x23},
66 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PRESENCE_DETECT, 0x24},
67 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TIMING, 0x25},
68 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_OPTIMIZING, 0x26},
69 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_CONFIGURING, 0x27},
70 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST, 0x28},
71 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_COMPLETE, 0x29},
72
73 //
74 // Platform Init after MRC
75 //
76 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR, 0x2A},
77 {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR_END, 0x2B},
78
79 {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN, 0x31},
80 {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_AUTO, 0x32},
81 {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD, 0x33},
82 {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START, 0x34},
83 {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE, 0x35},
84
85 {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_INIT, 0x41},
86 {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_STEP1, 0x42},
87 {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_END, 0x43},
88 {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_INIT, 0x44},
89 {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_STEP1, 0x45},
90 {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_END, 0x46}
91 };
92
93 BOOLEAN
94 PeiCodeTypeToPostCode (
95 IN EFI_STATUS_CODE_TYPE CodeType,
96 IN EFI_STATUS_CODE_VALUE Value,
97 OUT UINT8 *PostCode
98 )
99 {
100 UINTN Index;
101
102 if (CodeType == EFI_PROGRESS_CODE) {
103 if ((Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN)) ||
104 (Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_END)) ||
105 (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_BEGIN)) ||
106 (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_END))) {
107 return FALSE;
108 }
109 } else {
110 return FALSE;
111 }
112
113 for (Index = 0; Index < sizeof(mPeiPort80Table)/sizeof(EFI_STATUS_CODE_TO_PORT_80); Index++) {
114 if (mPeiPort80Table[Index].StatusValue == Value) {
115 *PostCode = mPeiPort80Table[Index].Port80Value;
116 return TRUE;
117 }
118 }
119
120 return FALSE;
121 }