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git.proxmox.com Git - mirror_edk2.git/blob - Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 Driver configuration include file
25 #ifndef _CONFIGURATION_H
26 #define _CONFIGURATION_H
28 #define EFI_NON_DEVICE_CLASS 0x00
29 #define EFI_DISK_DEVICE_CLASS 0x01
30 #define EFI_VIDEO_DEVICE_CLASS 0x02
31 #define EFI_NETWORK_DEVICE_CLASS 0x04
32 #define EFI_INPUT_DEVICE_CLASS 0x08
33 #define EFI_ON_BOARD_DEVICE_CLASS 0x10
34 #define EFI_OTHER_DEVICE_CLASS 0x20
39 #define PROCESSOR_HT_MODE 0x0100
40 #define PROCESSOR_FSB_MULTIPLIER 0x0101
41 #define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211
46 #define MEMORY_SLOT1_SPEED 0x0200
47 #define MEMORY_SLOT2_SPEED 0x0201
48 #define MEMORY_SLOT3_SPEED 0x0202
49 #define MEMORY_SLOT4_SPEED 0x0203
50 #define END_MEMORY_SLOT_SPEED 0x020F
51 #define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210
52 #define UCLK_RATIO_CONTROL 0x0212
57 #define FRONT_PAGE_ITEM_LANGUAGE 0x300
62 #define BOOT_DEVICE_PRIORITY_BEGIN 0x0400
63 #define BOOT_DEVICE_PRIORITY_END 0x0401
64 #define BOOT_OPTICAL_DEVICE_BEGIN 0x0410
65 #define BOOT_OPTICAL_DEVICE_END 0x0411
66 #define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420
67 #define BOOT_REMOVABLE_DEVICE_END 0x0421
68 #define BOOT_PXE_DEVICE_BEGIN 0x0430
69 #define BOOT_PXE_DEVICE_END 0x0431
70 #define BOOT_MENU_TYPE_BEGIN 0x0440
71 #define BOOT_MENU_TYPE_END 0x0441
72 #define BOOT_USB_DEVICE_BEGIN 0x0450
73 #define BOOT_USB_DEVICE_END 0x0451
74 #define BOOT_USB_FIRST_BEGIN 0x0460
75 #define BOOT_USB_FIRST_END 0x0461
76 #define BOOT_UEFI_BEGIN 0x0470
77 #define BOOT_UEFI_END 0x0471
78 #define BOOT_USB_UNAVAILABLE_BEGIN 0x0480
79 #define BOOT_USB_UNAVAILABLE_END 0x0481
80 #define BOOT_CD_UNAVAILABLE_BEGIN 0x0490
81 #define BOOT_CD_UNAVAILABLE_END 0x0491
82 #define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0
83 #define BOOT_FDD_UNAVAILABLE_END 0x04A1
84 #define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0
85 #define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1
86 #define BOOT_USB_OPT_LABEL_BEGIN 0x04C0
87 #define BOOT_USB_OPT_LABEL_END 0x04C1
89 #define VAR_EQ_ADMIN_NAME 0x0041 // A
90 #define VAR_EQ_ADMIN_DECIMAL_NAME L"65"
91 #define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B
92 #define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"
93 #define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C
94 #define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"
95 #define VAR_EQ_CPU_EE_NAME 0x0045 // E
96 #define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"
97 #define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F
98 #define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"
99 #define VAR_EQ_HT_MODE_NAME 0x0048 // H
100 #define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"
101 #define VAR_EQ_AHCI_MODE_NAME 0x0049 // I
102 #define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"
103 #define VAR_EQ_CPU_LOCK_NAME 0x004C // L
104 #define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"
105 #define VAR_EQ_NX_MODE_NAME 0x004E // N
106 #define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"
107 #define VAR_EQ_RAID_MODE_NAME 0x0052 // R
108 #define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"
109 #define VAR_EQ_1394_MODE_NAME 0x0054 // T
110 #define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"
111 #define VAR_EQ_USER_NAME 0x0055 // U
112 #define VAR_EQ_USER_DECIMAL_NAME L"85"
113 #define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V
114 #define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"
115 #define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W
116 #define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"
117 #define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X
118 #define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"
119 #define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y
120 #define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"
121 #define VAR_EQ_UNCON_CPU_NAME 0x005B // ??
122 #define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"
123 #define VAR_EQ_VAR_HIDE_NAME 0x005C // ??
124 #define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"
125 #define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??
126 #define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"
127 #define VAR_EQ_TPM_MODE_NAME 0x005E // ^
128 #define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"
129 #define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??
130 #define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"
131 #define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??
132 #define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"
133 #define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??
134 #define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"
135 #define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??
136 #define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"
137 #define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??
138 #define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"
139 #define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??
140 #define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"
141 #define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??
142 #define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"
143 #define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f
144 #define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"
145 #define VAR_EQ_2_MEMORY_NAME 0x0067 // ??
146 #define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"
147 #define VAR_EQ_2_SATA_NAME 0x0068 // ??
148 #define VAR_EQ_2_SATA_DECIMAL_NAME L"104"
149 #define VAR_EQ_NEC_SKU_NAME 0x0069 // ??
150 #define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"
151 #define VAR_EQ_AMT_MODE_NAME 0x006A // ??
152 #define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"
153 #define VAR_EQ_LCLX_SKU_NAME 0x006B // ??
154 #define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"
155 #define VAR_EQ_VT_NAME 0x006C
156 #define VAR_EQ_VT_DECIMAL_NAME L"108"
157 #define VAR_EQ_LT_NAME 0x006D
158 #define VAR_EQ_LT_DECIMAL_NAME L"109"
159 #define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??
160 #define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"
161 #define VAR_EQ_HPET_NAME 0x006F
162 #define VAR_EQ_HPET_DECIMAL_NAME L"111"
163 #define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??
164 #define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"
165 #define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??
166 #define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"
167 #define VAR_EQ_CPU_CMP_NAME 0x0072
168 #define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"
169 #define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??
170 #define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"
171 #define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??
172 #define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"
173 #define VAR_EQ_AFSC_SETUP_NAME 0x0075
174 #define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"
175 #define VAR_EQ_MINICARD_MODE_NAME 0x0076 //
176 #define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"
177 #define VAR_EQ_VIDEO_IGD_NAME 0x0077 //
178 #define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"
179 #define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //
180 #define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"
181 #define VAR_EQ_LEGACY_FREE_NAME 0x0079 //
182 #define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"
183 #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A
184 #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122"
185 #define VAR_EQ_CPU_FSB_NAME 0x007B //
186 #define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"
187 #define VAR_EQ_SATA0_DEVICE_NAME 0x007C //
188 #define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"
189 #define VAR_EQ_SATA1_DEVICE_NAME 0x007D //
190 #define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"
191 #define VAR_EQ_SATA2_DEVICE_NAME 0x007E //
192 #define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"
193 #define VAR_EQ_SATA3_DEVICE_NAME 0x007F //
194 #define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"
195 #define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //
196 #define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"
197 #define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //
198 #define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"
199 #define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled
200 #define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"
201 #define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083
202 #define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"
203 #define VAR_EQ_USB_2_NAME 0x0084 //
204 #define VAR_EQ_USB_2_DECIMAL_NAME L"132"
205 #define VAR_EQ_RVP_NAME 0x0085 //
206 #define VAR_EQ_RVP_DECIMAL_NAME L"133"
207 #define VAR_EQ_ECIR_NAME 0x0086
208 #define VAR_EQ_ECIR_DECIMAL_NAME L"134"
209 #define VAR_EQ_WAKONS5KB_NAME 0x0087
210 #define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"
211 #define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088
212 #define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"
213 #define VAR_EQ_FINGERPRINT_NAME 0x0089
214 #define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"
215 #define VAR_EQ_BLUETOOTH_NAME 0x008A
216 #define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"
217 #define VAR_EQ_WLAN_NAME 0x008B
218 #define VAR_EQ_WLAN_DECIMAL_NAME L"139"
219 #define VAR_EQ_1_PATA_NAME 0x008C
220 #define VAR_EQ_1_PATA_DECIMAL_NAME L"140"
221 #define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D
222 #define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"
223 #define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E
224 #define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"
225 #define VAR_EQ_XE_MODE_CAP_NAME 0x008F
226 #define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"
227 #define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090
228 #define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"
229 #define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091
230 #define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"
231 #define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??
232 #define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"
233 #define VAR_EQ_LVDS_NAME 0x0093
234 #define VAR_EQ_LVDS_DECIMAL_NAME L"147"
235 #define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094
236 #define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"
237 #define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095
238 #define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"
239 #define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096
240 #define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"
241 #define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??
242 #define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"
243 #define VAR_EQ_VIDEO_SLOT_NAME 0x0098
244 #define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"
245 #define VAR_EQ_HDMI_SLOT_NAME 0x0099
246 #define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"
247 #define VAR_EQ_SERIAL2_HIDE_NAME 0x009a
248 #define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"
251 #define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e
252 #define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"
255 #define VAR_EQ_MSATA_HIDE_NAME 0x009f
256 #define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"
259 #define VAR_EQ_PCI_SLOT1_NAME 0x00a0
260 #define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"
261 #define VAR_EQ_PCI_SLOT2_NAME 0x00a1
262 #define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"
267 #define ROOT_FORM_ID 1
270 // Advance Page. Do not have to be sequential but have to be unique
272 #define CONFIGURATION_ROOT_FORM_ID 2
273 #define BOOT_CONFIGURATION_ID 3
274 #define ONBOARDDEVICE_CONFIGURATION_ID 4
275 #define DRIVE_CONFIGURATION_ID 5
276 #define FLOPPY_CONFIGURATION_ID 6
277 #define EVENT_LOG_CONFIGURATION_ID 7
278 #define VIDEO_CONFIGURATION_ID 8
279 #define USB_CONFIGURATION_ID 9
280 #define HARDWARE_MONITOR_CONFIGURATION_ID 10
281 #define VIEW_EVENT_LOG_CONFIGURATION_ID 11
282 #define MEMORY_OVERRIDE_ID 12
283 #define CHIPSET_CONFIGURATION_ID 13
284 #define BURN_IN_MODE_ID 14
285 #define PCI_EXPRESS_ID 15
286 #define MANAGEMENT_CONFIGURATION_ID 16
287 #define CPU_CONFIGURATION_ID 17
288 #define PCI_CONFIGURATION_ID 18
289 #define SECURITY_CONFIGURATION_ID 19
290 #define ZIP_CONFIGURATION_ID 20
291 #define AFSC_FAN_CONTROL_ID 21
292 #define VFR_FORMID_CSI 22
293 #define VFR_FORMID_MEMORY 23
294 #define VFR_FORMID_IOH 24
295 #define VFR_FORMID_CPU_CSI 25
296 #define VFR_FORMID_IOH_CONFIG 26
297 #define VFR_FORMID_VTD 27
298 #define VFR_FORMID_PCIE_P0 28
299 #define VFR_FORMID_PCIE_P1 29
300 #define VFR_FORMID_PCIE_P2 30
301 #define VFR_FORMID_PCIE_P3 31
302 #define VFR_FORMID_PCIE_P4 32
303 #define VFR_FORMID_PCIE_P5 33
304 #define VFR_FORMID_PCIE_P6 34
305 #define VFR_FORMID_PCIE_P7 35
306 #define VFR_FORMID_PCIE_P8 36
307 #define VFR_FORMID_PCIE_P9 37
308 #define VFR_FORMID_PCIE_P10 38
309 #define VFR_FID_SKT0 39
310 #define VFR_FID_IOH0 40
311 #define VFR_FID_IOH_DEV_HIDE 41
312 #define PROCESSOR_OVERRIDES_FORM_ID 42
313 #define BUS_OVERRIDES_FORM_ID 43
314 #define REF_OVERRIDES_FORM_ID 44
315 #define MEMORY_INFORMATION_ID 45
316 #define LVDS_WARNING_ID 46
317 #define LVDS_CONFIGURATION_ID 47
318 #define PCI_SLOT_CONFIGURATION_ID 48
319 #define HECETA_CONFIGURATION_ID 49
320 #define LVDS_EXPERT_CONFIGURATION_ID 50
321 #define PCI_SLOT_7_ID 51
322 #define PCI_SLOT_6_ID 52
323 #define PCI_SLOT_5_ID 53
324 #define PCI_SLOT_4_ID 54
325 #define PCI_SLOT_3_ID 55
326 #define PCI_SLOT_2_ID 56
327 #define PCI_SLOT_1_ID 57
328 #define BOOT_DISPLAY_ID 58
329 #define CPU_PWR_CONFIGURATION_ID 59
331 #define FSC_CONFIGURATION_ID 60
332 #define FSC_CPU_TEMPERATURE_FORM_ID 61
333 #define FSC_VTT_VOLTAGE_FORM_ID 62
334 #define FSC_FEATURES_CONTROL_ID 63
335 #define FSC_FAN_CONFIGURATION_ID 64
336 #define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65
337 #define FSC_FRONT_FAN_CONFIGURATION_ID 66
338 #define FSC_REAR_FAN_CONFIGURATION_ID 67
339 #define FSC_AUX_FAN_CONFIGURATION_ID 68
340 #define FSC_12_VOLTAGE_FORM_ID 69
341 #define FSC_5_VOLTAGE_FORM_ID 70
342 #define FSC_3P3_VOLTAGE_FORM_ID 71
343 #define FSC_2P5_VOLTAGE_FORM_ID 72
344 #define FSC_VCC_VOLTAGE_FORM_ID 73
345 #define FSC_PCH_TEMPERATURE_FORM_ID 74
346 #define FSC_MEM_TEMPERATURE_FORM_ID 75
347 #define FSC_VR_TEMPERATURE_FORM_ID 76
348 #define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77
349 #define FSC_5BACKUP_VOLTAGE_FORM_ID 78
350 #define ROOT_MAIN_FORM_ID 79
351 #define ROOT_BOOT_FORM_ID 80
352 #define ROOT_MAINTENANCE_ID 81
353 #define ROOT_POWER_FORM_ID 82
354 #define ROOT_SECURITY_FORM_ID 83
355 #define ROOT_PERFORMANCE_FORM_ID 84
356 #define ROOT_SYSTEM_SETUP_FORM_ID 85
358 #define ADDITIONAL_SYSTEM_INFO_FORM_ID 86
360 #define THERMAL_CONFIG_FORM_ID 87
362 #define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A
363 #define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B
364 #define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C
365 #define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D
366 #define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E
367 #define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F
368 #define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010
369 #define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011
372 // Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
374 #define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000
375 #define ADVANCE_VIDEO_CALLBACK_KEY 0x2001
376 #define CONFIGURATION_FSC_CALLBACK_KEY 0x2002
377 #define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003
378 #define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004
379 #define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005
380 #define ADVANCE_LVDS_CALLBACK_KEY 0x2010
383 // Main Callback Keys. Do not have to be sequential but have to be unique
385 #define MAIN_LANGUAGE_CALLBACK_KEY 0x3000
388 // Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
390 #define POWER_HARDWARE_CALLBACK_KEY 0x4000
393 // Performance Callback Keys. Do not have to be sequential but have to be unique
395 #define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000
396 #define PERFORMANCE_CALLBACK_KEY 0x5001
397 #define BUS_OVERRIDES_CALLBACK_KEY 0x5002
398 #define MEMORY_CFG_CALLBACK_KEY 0x5003
399 #define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004
400 #define MEMORY_RATIO_CALLBACK_KEY 0x5005
401 #define MEMORY_MODE_CALLBACK_KEY 0x5006
404 // Security Callback Keys. Do not have to be sequential but have to be unique
406 #define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000
407 #define SECURITY_USER_CALLBACK_KEY 0x1001
408 #define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002
409 #define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004
410 #define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008
411 #define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010
412 #define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020
413 #define SECURITY_USER_HDD_CALLBACK_KEY 0x1040
416 // Boot Callback Keys. Do not have to be sequential but have to be unique
418 #define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003
419 #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004
420 #define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005
421 #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006
424 // IDCC/Setup FSB Frequency Override Range
426 #define EFI_IDCC_FSB_MIN 133
427 #define EFI_IDCC_FSB_MAX 240
428 #define EFI_IDCC_FSB_STEP 1
433 #define EFI_REF_DAC_MIN 0
434 #define EFI_REF_DAC_MAX 255
435 #define EFI_GTLREF_DEF 170
436 #define EFI_DDRREF_DEF 128
437 #define EFI_DIMMREF_DEF 128
440 // Setup FSB Frequency Override Range
442 #define EFI_FSB_MIN 133
443 #define EFI_FSB_MAX 240
444 #define EFI_FSB_STEP 1
445 #define EFI_FSB_AUTOMATIC 0
446 #define EFI_FSB_MANUAL 1
447 #define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1
448 #define FSB_FREQ_ENTRY_TYPE UINT16_TYPE
451 // Setup processor multiplier range
453 #define EFI_PROC_MULT_MIN 5
454 #define EFI_PROC_MULT_MAX 40
455 #define EFI_PROC_MULT_STEP 1
456 #define EFI_PROC_AUTOMATIC 0
457 #define EFI_PROC_MANUAL 1
458 #define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1
459 #define PROC_MULT_ENTRY_TYPE UINT8_TYPE
462 // PCI Express Definitions
464 #define EFI_PCIE_FREQ_DEF 0x0
466 #define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE
467 #define PCIE_FREQ_ENTRY_7 0x7
468 #define PCIE_FREQ_ENTRY_6 0x6
469 #define PCIE_FREQ_ENTRY_5 0x5
470 #define PCIE_FREQ_ENTRY_4 0x4
471 #define PCIE_FREQ_ENTRY_3 0x3
472 #define PCIE_FREQ_ENTRY_2 0x2
473 #define PCIE_FREQ_ENTRY_1 0x1
474 #define PCIE_FREQ_ENTRY_0 0x0
476 #define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8
477 #define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \
487 #define PCIE_FREQ_PRECISION 2
488 #define PCIE_FREQ_VALUE_7 10924
489 #define PCIE_FREQ_VALUE_6 10792
490 #define PCIE_FREQ_VALUE_5 10660
491 #define PCIE_FREQ_VALUE_4 10528
492 #define PCIE_FREQ_VALUE_3 10396
493 #define PCIE_FREQ_VALUE_2 10264
494 #define PCIE_FREQ_VALUE_1 10132
495 #define PCIE_FREQ_VALUE_0 10000
497 #define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \
507 // Memory Frequency Definitions
509 #define MEMORY_REF_FREQ_ENTRY_DEF 0x08
511 #define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE
512 #define MEMORY_REF_FREQ_ENTRY_3 0x04
513 #define MEMORY_REF_FREQ_ENTRY_2 0x00
514 #define MEMORY_REF_FREQ_ENTRY_1 0x02
515 #define MEMORY_REF_FREQ_ENTRY_0 0x01
517 #define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4
518 #define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \
519 MEMORY_REF_FREQ_ENTRY_1, \
520 MEMORY_REF_FREQ_ENTRY_2, \
521 MEMORY_REF_FREQ_ENTRY_3 }
523 #define MEMORY_REF_FREQ_PRECISION 0
524 #define MEMORY_REF_FREQ_VALUE_3 333
525 #define MEMORY_REF_FREQ_VALUE_2 267
526 #define MEMORY_REF_FREQ_VALUE_1 200
527 #define MEMORY_REF_FREQ_VALUE_0 133
529 #define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \
530 MEMORY_REF_FREQ_VALUE_1, \
531 MEMORY_REF_FREQ_VALUE_2, \
532 MEMORY_REF_FREQ_VALUE_3 }
536 // Memory Reference Frequency Definitions
539 #define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE
540 #define MEMORY_FREQ_ENTRY_3 0x4
541 #define MEMORY_FREQ_ENTRY_2 0x3
542 #define MEMORY_FREQ_ENTRY_1 0x2
543 #define MEMORY_FREQ_ENTRY_0 0x1
545 #define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4
546 #define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \
547 MEMORY_FREQ_ENTRY_1, \
548 MEMORY_FREQ_ENTRY_2, \
549 MEMORY_FREQ_ENTRY_3 }
552 #define MEMORY_FREQ_MULT_PRECISION 2
553 #define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240
554 #define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200
555 #define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160
556 #define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120
558 #define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300
559 #define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250
560 #define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200
561 #define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150
563 #define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400
564 #define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333
565 #define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267
566 #define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200
568 #define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600
569 #define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500
570 #define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400
571 #define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300
573 #define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \
574 MEMORY_FREQ_MULT_333MHZ_VALUE_1, \
575 MEMORY_FREQ_MULT_333MHZ_VALUE_2, \
576 MEMORY_FREQ_MULT_333MHZ_VALUE_3 }
578 #define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \
579 MEMORY_FREQ_MULT_266MHZ_VALUE_1, \
580 MEMORY_FREQ_MULT_266MHZ_VALUE_2, \
581 MEMORY_FREQ_MULT_266MHZ_VALUE_3 }
583 #define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \
584 MEMORY_FREQ_MULT_200MHZ_VALUE_1, \
585 MEMORY_FREQ_MULT_200MHZ_VALUE_2, \
586 MEMORY_FREQ_MULT_200MHZ_VALUE_3 }
588 #define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \
589 MEMORY_FREQ_MULT_133MHZ_VALUE_1, \
590 MEMORY_FREQ_MULT_133MHZ_VALUE_2, \
591 MEMORY_FREQ_MULT_133MHZ_VALUE_3 }
594 // CAS Memory Timing Definitions
597 #define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE
598 #define MEMORY_TCL_ENTRY_3 0x2
599 #define MEMORY_TCL_ENTRY_2 0x1
600 #define MEMORY_TCL_ENTRY_1 0x0
601 #define MEMORY_TCL_ENTRY_0 0x3
603 #define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4
604 #define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \
605 MEMORY_TCL_ENTRY_1, \
606 MEMORY_TCL_ENTRY_2, \
610 #define MEMORY_TCL_PRECISION 0
611 #define MEMORY_TCL_VALUE_3 3
612 #define MEMORY_TCL_VALUE_2 4
613 #define MEMORY_TCL_VALUE_1 5
614 #define MEMORY_TCL_VALUE_0 6
616 #define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \
617 MEMORY_TCL_VALUE_1, \
618 MEMORY_TCL_VALUE_2, \
623 // TRCD Memory Timing Definitions
626 #define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE
627 #define MEMORY_TRCD_ENTRY_3 0x0
628 #define MEMORY_TRCD_ENTRY_2 0x1
629 #define MEMORY_TRCD_ENTRY_1 0x2
630 #define MEMORY_TRCD_ENTRY_0 0x3
632 #define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4
633 #define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \
634 MEMORY_TRCD_ENTRY_1, \
635 MEMORY_TRCD_ENTRY_2, \
636 MEMORY_TRCD_ENTRY_3 }
639 #define MEMORY_TRCD_PRECISION 0
640 #define MEMORY_TRCD_VALUE_3 2
641 #define MEMORY_TRCD_VALUE_2 3
642 #define MEMORY_TRCD_VALUE_1 4
643 #define MEMORY_TRCD_VALUE_0 5
645 #define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \
646 MEMORY_TRCD_VALUE_1, \
647 MEMORY_TRCD_VALUE_2, \
648 MEMORY_TRCD_VALUE_3 }
652 // TRP Memory Timing Definitions
655 #define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE
656 #define MEMORY_TRP_ENTRY_3 0x0
657 #define MEMORY_TRP_ENTRY_2 0x1
658 #define MEMORY_TRP_ENTRY_1 0x2
659 #define MEMORY_TRP_ENTRY_0 0x3
661 #define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4
662 #define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \
663 MEMORY_TRP_ENTRY_1, \
664 MEMORY_TRP_ENTRY_2, \
668 #define MEMORY_TRP_PRECISION 0
669 #define MEMORY_TRP_VALUE_3 2
670 #define MEMORY_TRP_VALUE_2 3
671 #define MEMORY_TRP_VALUE_1 4
672 #define MEMORY_TRP_VALUE_0 5
674 #define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \
675 MEMORY_TRP_VALUE_1, \
676 MEMORY_TRP_VALUE_2, \
681 // TRAS Memory Timing Definitions
683 #define MEMORY_TRAS_MIN 4
684 #define MEMORY_TRAS_MAX 18
685 #define MEMORY_TRAS_STEP 1
686 #define MEMORY_TRAS_DEFAULT 13
687 #define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1
688 #define MEMORY_TRAS_TYPE UINT8_TYPE
691 // Uncore Multiplier Definitions
693 #define UCLK_RATIO_MIN 12
694 #define UCLK_RATIO_MAX 30
695 #define UCLK_RATIO_DEFAULT 20
697 #endif // #ifndef _CONFIGURATION_H