3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Register initialization table for Ich.
27 #include <Library/EfiRegTableLib.h>
28 #include "PlatformDxe.h"
29 extern EFI_PLATFORM_INFO_HOB mPlatformInfo
;
31 #define R_EFI_PCI_SVID 0x2C
33 EFI_REG_TABLE mSubsystemIdRegs
[] = {
36 // Program SVID and SID for PCI devices.
37 // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
40 MC_BUS
, MC_DEV
, MC_FUN
, R_EFI_PCI_SVID
, EfiPciWidthUint32
,
41 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
45 IGD_BUS
, IGD_DEV
, IGD_FUN_0
, R_EFI_PCI_SVID
, EfiPciWidthUint32
,
46 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
50 DEFAULT_PCI_BUS_NUMBER_PCH
, 0, 0, R_EFI_PCI_SVID
, EfiPciWidthUint32
,
51 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
54 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, PCI_FUNCTION_NUMBER_PCH_LPC
, R_PCH_LPC_SS
, EfiPciWidthUint32
,
55 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
58 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_SATA
, PCI_FUNCTION_NUMBER_PCH_SATA
, R_PCH_SATA_SS
, EfiPciWidthUint32
,
59 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
62 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_SMBUS
, PCI_FUNCTION_NUMBER_PCH_SMBUS
, R_PCH_SMBUS_SVID
, EfiPciWidthUint32
,
63 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
66 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_USB
, PCI_FUNCTION_NUMBER_PCH_EHCI
, R_PCH_EHCI_SVID
, EfiPciWidthUint32
,
67 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
70 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS
, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1
, R_PCH_PCIE_SVID
, EfiPciWidthUint32
,
71 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
74 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS
, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2
, R_PCH_PCIE_SVID
, EfiPciWidthUint32
,
75 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
78 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS
, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3
, R_PCH_PCIE_SVID
, EfiPciWidthUint32
,
79 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
82 DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS
, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4
, R_PCH_PCIE_SVID
, EfiPciWidthUint32
,
83 V_PCH_DEFAULT_SVID_SID
, OPCODE_FLAG_S3SAVE
89 Updates the mSubsystemIdRegs table, and processes it. This should program
90 the Subsystem Vendor and Device IDs.
96 InitializeSubsystemIds (
100 EFI_REG_TABLE
*RegTablePtr
;
101 UINT32 SubsystemVidDid
;
102 UINT32 SubsystemAudioVidDid
;
104 SubsystemVidDid
= mPlatformInfo
.SsidSvid
;
105 SubsystemAudioVidDid
= mPlatformInfo
.SsidSvid
;
107 RegTablePtr
= mSubsystemIdRegs
;
110 // While we are not at the end of the table
112 while (RegTablePtr
->Generic
.OpCode
!= OP_TERMINATE_TABLE
) {
114 // If the data to write is the original SSID
116 if (RegTablePtr
->PciWrite
.Data
==
117 ((V_PCH_DEFAULT_SID
<< 16) |
118 V_PCH_INTEL_VENDOR_ID
)
122 // Then overwrite it to use the alternate SSID
124 RegTablePtr
->PciWrite
.Data
= SubsystemVidDid
;
128 // Go to next table entry
133 RegTablePtr
= mSubsystemIdRegs
;
137 // Program the SSVID/SSDID
139 ProcessRegTablePci (mSubsystemIdRegs
, mPciRootBridgeIo
, NULL
);