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1 /** @file
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7
8
9 Module Name:
10
11
12 IchRegTable.c
13
14 Abstract:
15
16 Register initialization table for Ich.
17
18
19
20 --*/
21
22 #include <Library/EfiRegTableLib.h>
23 #include "PlatformDxe.h"
24 extern EFI_PLATFORM_INFO_HOB mPlatformInfo;
25
26 #define R_EFI_PCI_SVID 0x2C
27
28 EFI_REG_TABLE mSubsystemIdRegs [] = {
29
30 //
31 // Program SVID and SID for PCI devices.
32 // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
33 //
34 PCI_WRITE (
35 MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
36 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
37 ),
38
39 PCI_WRITE (
40 IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
41 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
42 ),
43
44 PCI_WRITE(
45 DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,
46 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
47 ),
48 PCI_WRITE (
49 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,
50 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
51 ),
52 PCI_WRITE (
53 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,
54 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
55 ),
56 PCI_WRITE (
57 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,
58 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
59 ),
60 PCI_WRITE (
61 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,
62 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
63 ),
64 PCI_WRITE (
65 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,
66 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
67 ),
68 PCI_WRITE (
69 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,
70 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
71 ),
72 PCI_WRITE (
73 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,
74 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
75 ),
76 PCI_WRITE (
77 DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,
78 V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
79 ),
80 TERMINATE_TABLE
81 };
82
83 /**
84 Updates the mSubsystemIdRegs table, and processes it. This should program
85 the Subsystem Vendor and Device IDs.
86
87 @retval Returns VOID
88
89 **/
90 VOID
91 InitializeSubsystemIds (
92 )
93 {
94
95 EFI_REG_TABLE *RegTablePtr;
96 UINT32 SubsystemVidDid;
97
98 SubsystemVidDid = mPlatformInfo.SsidSvid;
99
100 RegTablePtr = mSubsystemIdRegs;
101
102 //
103 // While we are not at the end of the table
104 //
105 while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
106 //
107 // If the data to write is the original SSID
108 //
109 if (RegTablePtr->PciWrite.Data ==
110 ((V_PCH_DEFAULT_SID << 16) |
111 V_PCH_INTEL_VENDOR_ID)
112 ) {
113
114 //
115 // Then overwrite it to use the alternate SSID
116 //
117 RegTablePtr->PciWrite.Data = SubsystemVidDid;
118 }
119
120 //
121 // Go to next table entry
122 //
123 RegTablePtr++;
124 }
125
126 RegTablePtr = mSubsystemIdRegs;
127
128
129 //
130 // Program the SSVID/SSDID
131 //
132 ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);
133
134 }