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MdeModulePkg/PiSmmCore: Control S3 related functionality through flag.
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / Platform.c
1 /** @file
2
3 Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
4
5
6 This program and the accompanying materials are licensed and made available under
7
8 the terms and conditions of the BSD License that accompanies this distribution.
9
10 The full text of the license may be found at
11
12 http://opensource.org/licenses/bsd-license.php.
13
14
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23 Module Name:
24
25
26 Platform.c
27
28 Abstract:
29
30 Platform Initialization Driver.
31
32
33 --*/
34
35 #include "PlatformDxe.h"
36 #include "Platform.h"
37 #include "PchCommonDefinitions.h"
38 #include <Protocol/UsbPolicy.h>
39 #include <Protocol/PchPlatformPolicy.h>
40 #include <Protocol/TpmMp.h>
41 #include <Protocol/CpuIo2.h>
42 #include <Library/S3BootScriptLib.h>
43 #include <Guid/PciLanInfo.h>
44 #include <Guid/ItkData.h>
45 #include <Library/PciLib.h>
46 #include <PlatformBootMode.h>
47 #include <Guid/EventGroup.h>
48 #include <Guid/Vlv2Variable.h>
49 #include <Protocol/GlobalNvsArea.h>
50 #include <Protocol/IgdOpRegion.h>
51 #include <Library/PcdLib.h>
52 #include <Protocol/VariableLock.h>
53
54
55 //
56 // VLV2 GPIO GROUP OFFSET
57 //
58 #define GPIO_SCORE_OFFSET 0x0000
59 #define GPIO_NCORE_OFFSET 0x1000
60 #define GPIO_SSUS_OFFSET 0x2000
61
62 typedef struct {
63 UINT32 offset;
64 UINT32 val;
65 } CFIO_PNP_INIT;
66
67 GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
68 {
69 // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
70 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
71 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
72 };
73
74
75 EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
76 EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
77 SYSTEM_CONFIGURATION mSystemConfiguration;
78 SYSTEM_PASSWORDS mSystemPassword;
79 EFI_HANDLE mImageHandle;
80 BOOLEAN mMfgMode = FALSE;
81 VOID *mDxePlatformStringPack;
82 UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
83 extern CHAR16 gItkDataVarName[];
84
85
86 EFI_PLATFORM_INFO_HOB mPlatformInfo;
87 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
88 EFI_EVENT mReadyToBootEvent;
89
90 UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
91 UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
92 UINT32 mSubsystemVidDid;
93 UINT32 mSubsystemAudioVidDid;
94
95 UINTN mPciLanCount = 0;
96 VOID *mPciLanInfo = NULL;
97 UINTN SpiBase;
98
99 static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
100 ProgramToneFrequency,
101 GenerateBeepTone
102 };
103
104 EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
105
106
107 CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
108 {
109 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
110 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
111 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
112 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
113 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
114 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
115 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
116 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
117 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
118 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
119 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
120 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
121 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
122 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
123 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
124 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
125 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
126 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
127 };
128
129 VOID
130 EfiOrMem (
131 IN VOID *Destination,
132 IN VOID *Source,
133 IN UINTN Length
134 );
135
136 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
137 STATIC
138 VOID
139 InitFirmwareId();
140 #endif
141
142
143 VOID
144 InitializeClockRouting(
145 );
146
147 VOID
148 InitializeSlotInfo (
149 );
150
151 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
152 VOID
153 InitializeSensorInfoVariable (
154 );
155 #endif
156
157 VOID
158 InitTcoReset (
159 );
160
161 VOID
162 InitExI ();
163
164 VOID
165 InitItk();
166
167 VOID
168 InitPlatformBootMode();
169
170 VOID
171 InitMfgAndConfigModeStateVar();
172
173 VOID
174 InitPchPlatformPolicy (
175 IN EFI_PLATFORM_INFO_HOB *PlatformInfo
176 );
177
178 VOID
179 InitVlvPlatformPolicy (
180 );
181
182 VOID
183 InitSioPlatformPolicy(
184 );
185
186 VOID
187 PchInitBeforeBoot(
188 );
189
190 VOID
191 UpdateDVMTSetup(
192 );
193
194 VOID
195 InitPlatformUsbPolicy (
196 VOID
197 );
198
199 VOID
200 InitRC6Policy(
201 VOID
202 );
203
204
205 EFI_STATUS
206 EFIAPI
207 SaveSetupRecoveryVar(
208 VOID
209 )
210 {
211 EFI_STATUS Status = EFI_SUCCESS;
212 UINTN SizeOfNvStore = 0;
213 UINTN SizeOfSetupVar = 0;
214 SYSTEM_CONFIGURATION *SetupData = NULL;
215 SYSTEM_CONFIGURATION *RecoveryNvData = NULL;
216 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL;
217
218
219 DEBUG ((EFI_D_INFO, "SaveSetupRecoveryVar() Entry \n"));
220 SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);
221 RecoveryNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
222 if (NULL == RecoveryNvData) {
223 Status = EFI_OUT_OF_RESOURCES;
224 goto Exit;
225 }
226
227 Status = gRT->GetVariable(
228 L"SetupRecovery",
229 &gEfiNormalSetupGuid,
230 NULL,
231 &SizeOfNvStore,
232 RecoveryNvData
233 );
234
235 if (EFI_ERROR (Status)) {
236 // Don't find the "SetupRecovery" variable.
237 // have to copy "Setup" variable to "SetupRecovery" variable.
238 SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
239 if (NULL == SetupData) {
240 Status = EFI_OUT_OF_RESOURCES;
241 goto Exit;
242 }
243 SizeOfSetupVar = sizeof(SYSTEM_CONFIGURATION);
244 Status = gRT->GetVariable(
245 NORMAL_SETUP_NAME,
246 &gEfiNormalSetupGuid,
247 NULL,
248 &SizeOfSetupVar,
249 SetupData
250 );
251 ASSERT_EFI_ERROR (Status);
252
253 Status = gRT->SetVariable (
254 L"SetupRecovery",
255 &gEfiNormalSetupGuid,
256 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
257 sizeof(SYSTEM_CONFIGURATION),
258 SetupData
259 );
260 ASSERT_EFI_ERROR (Status);
261
262 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
263 if (!EFI_ERROR (Status)) {
264 Status = VariableLock->RequestToLock (VariableLock, L"SetupRecovery", &gEfiNormalSetupGuid);
265 ASSERT_EFI_ERROR (Status);
266 }
267
268 }
269
270 Exit:
271 if (RecoveryNvData)
272 FreePool (RecoveryNvData);
273 if (SetupData)
274 FreePool (SetupData);
275
276 return Status;
277
278 }
279
280
281 VOID
282 TristateLpcGpioConfig (
283 IN UINT32 Gpio_Mmio_Offset,
284 IN UINT32 Gpio_Pin_Num,
285 GPIO_CONF_PAD_INIT* Gpio_Conf_Data
286 )
287
288 {
289 UINT32 index;
290 UINT32 mmio_conf0;
291 UINT32 mmio_padval;
292 PAD_CONF0 conf0_val;
293 PAD_VAL pad_val;
294
295 //
296 // GPIO WELL -- Memory base registers
297 //
298
299 //
300 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
301 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
302 //
303
304 for(index=0; index < Gpio_Pin_Num; index++)
305 {
306 //
307 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
308 //
309 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
310 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
311
312 #ifdef EFI_DEBUG
313 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
314
315 #endif
316 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
317 Gpio_Conf_Data[index].usage,
318 Gpio_Conf_Data[index].func,
319 Gpio_Conf_Data[index].int_type,
320 Gpio_Conf_Data[index].pull,
321 mmio_conf0));
322
323 //
324 // Step 1: PadVal Programming
325 //
326 pad_val.dw = MmioRead32(mmio_padval);
327
328 //
329 // Config PAD_VAL only for GPIO (Non-Native) Pin
330 //
331 if(Native != Gpio_Conf_Data[index].usage)
332 {
333 pad_val.dw &= ~0x6; // Clear bits 1:2
334 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
335
336 //
337 // set GPO default value
338 //
339 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
340 {
341 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
342 }
343 }
344
345
346 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
347
348 MmioWrite32(mmio_padval, pad_val.dw);
349
350 //
351 // Step 2: CONF0 Programming
352 // Read GPIO default CONF0 value, which is assumed to be default value after reset.
353 //
354 conf0_val.dw = MmioRead32(mmio_conf0);
355
356 //
357 // Set Function #
358 //
359 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
360
361 if(GPO == Gpio_Conf_Data[index].usage)
362 {
363 //
364 // If used as GPO, then internal pull need to be disabled
365 //
366 conf0_val.r.Pull_assign = 0; // Non-pull
367 }
368 else
369 {
370 //
371 // Set PullUp / PullDown
372 //
373 if(P_20K_H == Gpio_Conf_Data[index].pull)
374 {
375 conf0_val.r.Pull_assign = 0x1; // PullUp
376 conf0_val.r.Pull_strength = 0x2;// 20K
377 }
378 else if(P_20K_L == Gpio_Conf_Data[index].pull)
379 {
380 conf0_val.r.Pull_assign = 0x2; // PullDown
381 conf0_val.r.Pull_strength = 0x2;// 20K
382 }
383 else if(P_NONE == Gpio_Conf_Data[index].pull)
384 {
385 conf0_val.r.Pull_assign = 0; // Non-pull
386 }
387 else
388 {
389 ASSERT(FALSE); // Invalid value
390 }
391 }
392
393 //
394 // Set INT Trigger Type
395 //
396 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
397
398 //
399 // Set INT Trigger Type
400 //
401 if(TRIG_ == Gpio_Conf_Data[index].int_type)
402 {
403 //
404 // Interrupt not capable, clear bits 27:24
405 //
406 }
407 else
408 {
409 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
410 }
411
412 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
413
414 //
415 // Write back the targeted GPIO config value according to platform (board) GPIO setting
416 //
417 MmioWrite32 (mmio_conf0, conf0_val.dw);
418 }
419
420 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
421 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
422 //
423 }
424
425 VOID
426 EFIAPI
427 SpiBiosProtectionFunction(
428 EFI_EVENT Event,
429 VOID *Context
430 )
431 {
432
433 UINTN mPciD31F0RegBase;
434 UINTN BiosFlaLower0;
435 UINTN BiosFlaLimit0;
436 UINTN BiosFlaLower1;
437 UINTN BiosFlaLimit1;
438
439
440 BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
441 BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
442 #ifdef MINNOW2_FSP_BUILD
443 BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);
444 BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
445 #else
446 BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
447 BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
448 #endif
449
450
451 mPciD31F0RegBase = MmPciAddress (0,
452 DEFAULT_PCI_BUS_NUMBER_PCH,
453 PCI_DEVICE_NUMBER_PCH_LPC,
454 PCI_FUNCTION_NUMBER_PCH_LPC,
455 0
456 );
457 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
458
459 //
460 //Set SMM_BWP, WPD and LE bit
461 //
462 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
463 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
464 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
465
466 //
467 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
468 //
469 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
470 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
471 //
472 //Already locked. we could take no action here
473 //
474 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
475 return;
476 }
477
478 //
479 //Set PR0
480 //
481 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
482 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
483 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
484
485 //
486 //Set PR1
487 //
488
489 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
490 B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
491 (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
492
493 //
494 //Lock down PRx
495 //
496 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
497
498 //
499 // Verify if it's really locked.
500 //
501 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
502 DEBUG((EFI_D_ERROR, "Failed to lock down PRx.\n"));
503 }
504 return;
505
506 }
507
508 VOID
509 EFIAPI
510 InitPciDevPME (
511 EFI_EVENT Event,
512 VOID *Context
513 )
514 {
515 UINTN VarSize;
516
517 VarSize = sizeof(SYSTEM_CONFIGURATION);
518 gRT->GetVariable(
519 NORMAL_SETUP_NAME,
520 &gEfiNormalSetupGuid,
521 NULL,
522 &VarSize,
523 &mSystemConfiguration
524 );
525
526 //
527 //Program HDA PME_EN
528 //
529 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
530
531 //
532 //Program SATA PME_EN
533 //
534 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
535
536 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
537 if (mSystemConfiguration.EhciPllCfgEnable != 1) {
538 //
539 //Program EHCI PME_EN
540 //
541 PchMmPci32Or (
542 0,
543 0,
544 PCI_DEVICE_NUMBER_PCH_USB,
545 PCI_FUNCTION_NUMBER_PCH_EHCI,
546 R_PCH_EHCI_PWR_CNTL_STS,
547 B_PCH_EHCI_PWR_CNTL_STS_PME_EN
548 );
549 }
550 {
551 UINTN EhciPciMmBase;
552 UINT32 Buffer32 = 0;
553
554 EhciPciMmBase = MmPciAddress (0,
555 0,
556 PCI_DEVICE_NUMBER_PCH_USB,
557 PCI_FUNCTION_NUMBER_PCH_EHCI,
558 0
559 );
560 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
561 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
562 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
563 }
564 }
565
566 VOID
567 EFIAPI
568 InitThermalZone (
569 EFI_EVENT Event,
570 VOID *Context
571 )
572 {
573 UINTN VarSize;
574 EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
575 VarSize = sizeof(SYSTEM_CONFIGURATION);
576 gRT->GetVariable(
577 NORMAL_SETUP_NAME,
578 &gEfiNormalSetupGuid,
579 NULL,
580 &VarSize,
581 &mSystemConfiguration
582 );
583 gBS->LocateProtocol (
584 &gEfiGlobalNvsAreaProtocolGuid,
585 NULL,
586 (void **)&GlobalNvsArea
587 );
588 GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
589 GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
590 }
591 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
592
593 #endif
594
595
596 EFI_STATUS
597 EFIAPI
598 TristateLpcGpioS0i3Config (
599 UINT32 Gpio_Mmio_Offset,
600 UINT32 Gpio_Pin_Num,
601 CFIO_PNP_INIT* Gpio_Conf_Data
602 )
603 {
604
605 UINT32 index;
606 UINT32 mmio_reg;
607 UINT32 mmio_val;
608
609 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
610
611 for(index=0; index < Gpio_Pin_Num; index++)
612 {
613 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
614
615 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
616 mmio_val = 0;
617 mmio_val = MmioRead32(mmio_reg);
618
619 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
620 }
621
622 return EFI_SUCCESS;
623 }
624
625
626 EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
627
628 /**
629 Event Notification during exit boot service to enabel ACPI mode
630
631 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
632
633 Clear all ACPI event status and disable all ACPI events
634 Disable PM sources except power button
635 Clear status bits
636
637 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
638
639 Update EC to disable SMI and enable SCI
640
641 Enable SCI
642
643 Enable PME_B0_EN in GPE0a_EN
644
645 @param Event - EFI Event Handle
646 @param Context - Pointer to Notify Context
647
648 @retval Nothing
649
650 **/
651 VOID
652 EFIAPI
653 EnableAcpiCallback (
654 IN EFI_EVENT Event,
655 IN VOID *Context
656 )
657 {
658 UINT32 RegData32;
659 UINT16 Pm1Cnt;
660 UINT16 AcpiBase;
661 UINT32 Gpe0aEn;
662
663 AcpiBase = MmioRead16 (
664 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
665 PCI_DEVICE_NUMBER_PCH_LPC,
666 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
667 ) & B_PCH_LPC_ACPI_BASE_BAR;
668
669 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
670
671 //
672 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
673 //
674 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
675 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
676 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
677
678 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
679 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
680 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
681
682 //
683 // Disable PM sources except power button
684 // power button is enabled only for PCAT. Disabled it on Tablet platform
685 //
686
687 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
688 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
689
690 //
691 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
692 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
693 //
694 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
695 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
696
697 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
698 RegData32 &= ~(BIT7);
699 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
700
701 //
702 // Enable SCI
703 //
704 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
705 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
706 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
707
708 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
709
710 //
711 // Enable PME_B0_EN in GPE0a_EN
712 // Caution: Enable PME_B0_EN must be placed after enabling SCI.
713 // Otherwise, USB PME could not be handled as SMI event since no handler is there.
714 //
715 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
716 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
717 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
718
719 }
720
721 /**
722
723 Routine Description:
724
725 This is the standard EFI driver point for the Driver. This
726 driver is responsible for setting up any platform specific policy or
727 initialization information.
728
729 @param ImageHandle Handle for the image of this driver.
730 @param SystemTable Pointer to the EFI System Table.
731
732 @retval EFI_SUCCESS Policy decisions set.
733
734 **/
735 EFI_STATUS
736 EFIAPI
737 InitializePlatform (
738 IN EFI_HANDLE ImageHandle,
739 IN EFI_SYSTEM_TABLE *SystemTable
740 )
741 {
742 EFI_STATUS Status;
743 UINTN VarSize;
744 EFI_HANDLE Handle = NULL;
745 EFI_EVENT mEfiExitBootServicesEvent;
746 EFI_EVENT RtcEvent;
747 VOID *RtcCallbackReg = NULL;
748
749 mImageHandle = ImageHandle;
750
751 Status = gBS->InstallProtocolInterface (
752 &Handle,
753 &gEfiSpeakerInterfaceProtocolGuid,
754 EFI_NATIVE_INTERFACE,
755 &mSpeakerInterface
756 );
757
758 Status = gBS->LocateProtocol (
759 &gEfiPciRootBridgeIoProtocolGuid,
760 NULL,
761 (VOID **) &mPciRootBridgeIo
762 );
763 ASSERT_EFI_ERROR (Status);
764
765 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
766 Status = gRT->GetVariable(
767 L"PlatformInfo",
768 &gEfiVlv2VariableGuid,
769 NULL,
770 &VarSize,
771 &mPlatformInfo
772 );
773
774 //
775 // Initialize Product Board ID variable
776 //
777 InitMfgAndConfigModeStateVar();
778 InitPlatformBootMode();
779
780 //
781 // Install Observable protocol
782 //
783 InitializeObservableProtocol();
784
785 Status = SaveSetupRecoveryVar();
786 if (EFI_ERROR (Status)) {
787 DEBUG ((EFI_D_ERROR, "InitializePlatform() Save SetupRecovery variable failed \n"));
788 }
789
790 VarSize = sizeof(SYSTEM_CONFIGURATION);
791 Status = gRT->GetVariable(
792 NORMAL_SETUP_NAME,
793 &gEfiNormalSetupGuid,
794 NULL,
795 &VarSize,
796 &mSystemConfiguration
797 );
798 if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
799 //The setup variable is corrupted
800 VarSize = sizeof(SYSTEM_CONFIGURATION);
801 Status = gRT->GetVariable(
802 L"SetupRecovery",
803 &gEfiNormalSetupGuid,
804 NULL,
805 &VarSize,
806 &mSystemConfiguration
807 );
808 ASSERT_EFI_ERROR (Status);
809 Status = gRT->SetVariable (
810 NORMAL_SETUP_NAME,
811 &gEfiNormalSetupGuid,
812 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
813 sizeof(SYSTEM_CONFIGURATION),
814 &mSystemConfiguration
815 );
816 }
817
818 Status = EfiCreateEventReadyToBootEx (
819 TPL_CALLBACK,
820 ReadyToBootFunction,
821 NULL,
822 &mReadyToBootEvent
823 );
824
825 //
826 // Create a ReadyToBoot Event to run the PME init process
827 //
828 Status = EfiCreateEventReadyToBootEx (
829 TPL_CALLBACK,
830 InitPciDevPME,
831 NULL,
832 &mReadyToBootEvent
833 );
834 //
835 // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
836 //
837 if(mSystemConfiguration.SpiRwProtect==1) {
838 Status = EfiCreateEventReadyToBootEx (
839 TPL_CALLBACK,
840 SpiBiosProtectionFunction,
841 NULL,
842 &mReadyToBootEvent
843 );
844 }
845 //
846 // Create a ReadyToBoot Event to run the thermalzone init process
847 //
848 Status = EfiCreateEventReadyToBootEx (
849 TPL_CALLBACK,
850 InitThermalZone,
851 NULL,
852 &mReadyToBootEvent
853 );
854
855 ReportStatusCodeEx (
856 EFI_PROGRESS_CODE,
857 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
858 0,
859 &gEfiCallerIdGuid,
860 NULL,
861 NULL,
862 0
863 );
864
865 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
866 //
867 // Initialize Sensor Info variable
868 //
869 InitializeSensorInfoVariable();
870 #endif
871 InitPchPlatformPolicy(&mPlatformInfo);
872 InitVlvPlatformPolicy();
873
874 //
875 // Add usb policy
876 //
877 InitPlatformUsbPolicy();
878 InitSioPlatformPolicy();
879 InitializeClockRouting();
880 InitializeSlotInfo();
881 InitTcoReset();
882
883 //
884 //Init ExI
885 //
886 InitExI();
887
888 ReportStatusCodeEx (
889 EFI_PROGRESS_CODE,
890 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
891 0,
892 &gEfiCallerIdGuid,
893 NULL,
894 NULL,
895 0
896 );
897
898 //
899 // Install PCI Bus Driver Hook
900 //
901 PciBusDriverHook();
902
903 InitItk();
904
905 ReportStatusCodeEx (
906 EFI_PROGRESS_CODE,
907 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
908 0,
909 &gEfiCallerIdGuid,
910 NULL,
911 NULL,
912 0
913 );
914
915
916 //
917 // Initialize Password States and Callbacks
918 //
919 PchInitBeforeBoot();
920
921 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
922
923 #endif
924
925 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
926 //
927 // Re-write Firmware ID if it is changed
928 //
929 InitFirmwareId();
930 #endif
931
932 ReportStatusCodeEx (
933 EFI_PROGRESS_CODE,
934 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
935 0,
936 &gEfiCallerIdGuid,
937 NULL,
938 NULL,
939 0
940 );
941
942
943 Status = gBS->CreateEventEx (
944 EVT_NOTIFY_SIGNAL,
945 TPL_NOTIFY,
946 EnableAcpiCallback,
947 NULL,
948 &gEfiEventExitBootServicesGuid,
949 &mEfiExitBootServicesEvent
950 );
951
952 //
953 // Adjust RTC deafult time to be BIOS-built time.
954 //
955 Status = gBS->CreateEvent (
956 EVT_NOTIFY_SIGNAL,
957 TPL_CALLBACK,
958 AdjustDefaultRtcTimeCallback,
959 NULL,
960 &RtcEvent
961 );
962 if (!EFI_ERROR (Status)) {
963 Status = gBS->RegisterProtocolNotify (
964 &gExitPmAuthProtocolGuid,
965 RtcEvent,
966 &RtcCallbackReg
967 );
968
969 }
970
971 return EFI_SUCCESS;
972 }
973
974 /**
975 Source Or Destination with Length bytes.
976
977 @param[in] Destination Target memory
978 @param[in] Source Source memory
979 @param[in] Length Number of bytes
980
981 @retval None
982
983 **/
984 VOID
985 EfiOrMem (
986 IN VOID *Destination,
987 IN VOID *Source,
988 IN UINTN Length
989 )
990 {
991 CHAR8 *Destination8;
992 CHAR8 *Source8;
993
994 if (Source < Destination) {
995 Destination8 = (CHAR8 *) Destination + Length - 1;
996 Source8 = (CHAR8 *) Source + Length - 1;
997 while (Length--) {
998 *(Destination8--) |= *(Source8--);
999 }
1000 } else {
1001 Destination8 = (CHAR8 *) Destination;
1002 Source8 = (CHAR8 *) Source;
1003 while (Length--) {
1004 *(Destination8++) |= *(Source8++);
1005 }
1006 }
1007 }
1008
1009 VOID
1010 PchInitBeforeBoot()
1011 {
1012 //
1013 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
1014 //
1015 S3BootScriptSaveMemWrite (
1016 EfiBootScriptWidthUint32,
1017 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
1018 1,
1019 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
1020
1021 S3BootScriptSaveMemWrite (
1022 EfiBootScriptWidthUint32,
1023 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
1024 1,
1025 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
1026
1027 S3BootScriptSaveMemWrite (
1028 EfiBootScriptWidthUint16,
1029 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
1030 1,
1031 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
1032
1033 S3BootScriptSaveMemWrite (
1034 EfiBootScriptWidthUint16,
1035 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
1036 1,
1037 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
1038
1039 //
1040 // Saved MTPMC_1 for S3 resume.
1041 //
1042 S3BootScriptSaveMemWrite (
1043 EfiBootScriptWidthUint32,
1044 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
1045 1,
1046 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
1047 return;
1048 }
1049
1050 VOID
1051 EFIAPI
1052 ReadyToBootFunction (
1053 EFI_EVENT Event,
1054 VOID *Context
1055 )
1056 {
1057 EFI_STATUS Status;
1058 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
1059 EFI_ISA_ACPI_DEVICE_ID IsaDevice;
1060 UINTN Size;
1061 UINT16 State;
1062 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
1063 EFI_CPU_IO_PROTOCOL *CpuIo;
1064 UINT8 Data;
1065 UINT8 ReceiveBuffer [64];
1066 UINT32 ReceiveBufferSize;
1067
1068 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
1069 0x00, 0x00, 0x00, 0x0A,
1070 0x00, 0x00, 0x00, 0x5D};
1071 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
1072 0x00, 0x00, 0x00, 0x0C,
1073 0x40, 0x00, 0x00, 0x0A,
1074 0x00, 0x00};
1075 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
1076 0x00, 0x00, 0x00, 0x0A,
1077 0x00, 0x00, 0x00, 0x70};
1078 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
1079 0x00, 0x00, 0x00, 0x0A,
1080 0x00, 0x00, 0x00, 0x6F};
1081 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
1082 0x00, 0x00, 0x00, 0x0B,
1083 0x00, 0x00, 0x00, 0x72,
1084 0x00};
1085 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
1086 0x00, 0x00, 0x00, 0x0B,
1087 0x00, 0x00, 0x00, 0x71,
1088 0x00};
1089
1090 Size = sizeof(UINT16);
1091 Status = gRT->GetVariable (
1092 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
1093 &gEfiNormalSetupGuid,
1094 NULL,
1095 &Size,
1096 &State
1097 );
1098
1099 //
1100 // Disable Floppy Controller if needed
1101 //
1102 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);
1103 if (!EFI_ERROR(Status) && (State == 0x00)) {
1104 IsaDevice.HID = EISA_PNP_ID(0x604);
1105 IsaDevice.UID = 0;
1106 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
1107 }
1108
1109 //
1110 // save LAN info to a variable
1111 //
1112 if (NULL != mPciLanInfo) {
1113 gRT->SetVariable (
1114 L"PciLanInfo",
1115 &gEfiPciLanInfoGuid,
1116 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
1117 mPciLanCount * sizeof(PCI_LAN_INFO),
1118 mPciLanInfo
1119 );
1120 }
1121
1122 if (NULL != mPciLanInfo) {
1123 gBS->FreePool (mPciLanInfo);
1124 mPciLanInfo = NULL;
1125 }
1126
1127
1128 //
1129 // Handle ACPI OS TPM requests here
1130 //
1131 Status = gBS->LocateProtocol (
1132 &gEfiCpuIoProtocolGuid,
1133 NULL,
1134 (VOID **)&CpuIo
1135 );
1136 Status = gBS->LocateProtocol (
1137 &gEfiTpmMpDriverProtocolGuid,
1138 NULL,
1139 (VOID **)&TpmMpDriver
1140 );
1141 if (!EFI_ERROR (Status))
1142 {
1143 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
1144
1145 //
1146 // Clear pending ACPI TPM request indicator
1147 //
1148 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
1149 if (Data != 0)
1150 {
1151 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
1152
1153 //
1154 // Assert Physical Presence for these commands
1155 //
1156 TpmPhysicalPresenceCommand [11] = 0x20;
1157 ReceiveBufferSize = sizeof(ReceiveBuffer);
1158 Status = TpmMpDriver->Transmit (
1159 TpmMpDriver, TpmPhysicalPresenceCommand,
1160 sizeof (TpmPhysicalPresenceCommand),
1161 ReceiveBuffer, &ReceiveBufferSize
1162 );
1163 //
1164 // PF PhysicalPresence = TRUE
1165 //
1166 TpmPhysicalPresenceCommand [11] = 0x08;
1167 ReceiveBufferSize = sizeof(ReceiveBuffer);
1168 Status = TpmMpDriver->Transmit (
1169 TpmMpDriver, TpmPhysicalPresenceCommand,
1170 sizeof (TpmPhysicalPresenceCommand),
1171 ReceiveBuffer,
1172 &ReceiveBufferSize
1173 );
1174 if (Data == 0x01)
1175 {
1176 //
1177 // TPM_PhysicalEnable
1178 //
1179 ReceiveBufferSize = sizeof(ReceiveBuffer);
1180 Status = TpmMpDriver->Transmit (
1181 TpmMpDriver, TpmPhysicalEnableCommand,
1182 sizeof (TpmPhysicalEnableCommand),
1183 ReceiveBuffer, &ReceiveBufferSize
1184 );
1185 }
1186 if (Data == 0x02)
1187 {
1188 //
1189 // TPM_PhysicalDisable
1190 //
1191 ReceiveBufferSize = sizeof(ReceiveBuffer);
1192 Status = TpmMpDriver->Transmit (
1193 TpmMpDriver, TpmPhysicalDisableCommand,
1194 sizeof (TpmPhysicalDisableCommand),
1195 ReceiveBuffer,
1196 &ReceiveBufferSize
1197 );
1198 }
1199 if (Data == 0x03)
1200 {
1201 //
1202 // TPM_PhysicalSetDeactivated=FALSE
1203 //
1204 ReceiveBufferSize = sizeof(ReceiveBuffer);
1205 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1206 Status = TpmMpDriver->Transmit (
1207 TpmMpDriver,
1208 TpmPhysicalSetDeactivatedCommand,
1209 sizeof (TpmPhysicalSetDeactivatedCommand),
1210 ReceiveBuffer, &ReceiveBufferSize
1211 );
1212 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
1213 }
1214 if (Data == 0x04)
1215 {
1216 //
1217 // TPM_PhysicalSetDeactivated=TRUE
1218 //
1219 ReceiveBufferSize = sizeof(ReceiveBuffer);
1220 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1221 Status = TpmMpDriver->Transmit (
1222 TpmMpDriver,
1223 TpmPhysicalSetDeactivatedCommand,
1224 sizeof (TpmPhysicalSetDeactivatedCommand),
1225 ReceiveBuffer,
1226 &ReceiveBufferSize
1227 );
1228 gRT->ResetSystem (
1229 EfiResetWarm,
1230 EFI_SUCCESS,
1231 0,
1232 NULL
1233 );
1234 }
1235 if (Data == 0x05)
1236 {
1237 //
1238 // TPM_ForceClear
1239 //
1240 ReceiveBufferSize = sizeof(ReceiveBuffer);
1241 Status = TpmMpDriver->Transmit (
1242 TpmMpDriver,
1243 TpmForceClearCommand,
1244 sizeof (TpmForceClearCommand),
1245 ReceiveBuffer,
1246 &ReceiveBufferSize
1247 );
1248 gRT->ResetSystem (
1249 EfiResetWarm,
1250 EFI_SUCCESS,
1251 0,
1252 NULL
1253 );
1254 }
1255 if (Data == 0x06)
1256 {
1257 //
1258 // TPM_PhysicalEnable
1259 //
1260 ReceiveBufferSize = sizeof(ReceiveBuffer);
1261 Status = TpmMpDriver->Transmit (
1262 TpmMpDriver,
1263 TpmPhysicalEnableCommand,
1264 sizeof (TpmPhysicalEnableCommand),
1265 ReceiveBuffer,
1266 &ReceiveBufferSize
1267 );
1268 //
1269 // TPM_PhysicalSetDeactivated=FALSE
1270 //
1271 ReceiveBufferSize = sizeof(ReceiveBuffer);
1272 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1273 Status = TpmMpDriver->Transmit (
1274 TpmMpDriver,
1275 TpmPhysicalSetDeactivatedCommand,
1276 sizeof (TpmPhysicalSetDeactivatedCommand),
1277 ReceiveBuffer,
1278 &ReceiveBufferSize
1279 );
1280 gRT->ResetSystem (
1281 EfiResetWarm,
1282 EFI_SUCCESS,
1283 0,
1284 NULL
1285 );
1286 }
1287 if (Data == 0x07)
1288 {
1289 //
1290 // TPM_PhysicalSetDeactivated=TRUE
1291 //
1292 ReceiveBufferSize = sizeof(ReceiveBuffer);
1293 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1294 Status = TpmMpDriver->Transmit (
1295 TpmMpDriver,
1296 TpmPhysicalSetDeactivatedCommand,
1297 sizeof (TpmPhysicalSetDeactivatedCommand),
1298 ReceiveBuffer,
1299 &ReceiveBufferSize
1300 );
1301 //
1302 // TPM_PhysicalDisable
1303 //
1304 ReceiveBufferSize = sizeof(ReceiveBuffer);
1305 Status = TpmMpDriver->Transmit (
1306 TpmMpDriver,
1307 TpmPhysicalDisableCommand,
1308 sizeof (TpmPhysicalDisableCommand),
1309 ReceiveBuffer,
1310 &ReceiveBufferSize
1311 );
1312 gRT->ResetSystem (
1313 EfiResetWarm,
1314 EFI_SUCCESS,
1315 0,
1316 NULL
1317 );
1318 }
1319 if (Data == 0x08)
1320 {
1321 //
1322 // TPM_SetOwnerInstall=TRUE
1323 //
1324 ReceiveBufferSize = sizeof(ReceiveBuffer);
1325 TpmSetOwnerInstallCommand [10] = 0x01;
1326 Status = TpmMpDriver->Transmit (
1327 TpmMpDriver,
1328 TpmSetOwnerInstallCommand,
1329 sizeof (TpmSetOwnerInstallCommand),
1330 ReceiveBuffer,
1331 &ReceiveBufferSize
1332 );
1333 }
1334 if (Data == 0x09)
1335 {
1336 //
1337 // TPM_SetOwnerInstall=FALSE
1338 //
1339 ReceiveBufferSize = sizeof(ReceiveBuffer);
1340 TpmSetOwnerInstallCommand [10] = 0x00;
1341 Status = TpmMpDriver->Transmit (
1342 TpmMpDriver,
1343 TpmSetOwnerInstallCommand,
1344 sizeof (TpmSetOwnerInstallCommand),
1345 ReceiveBuffer,
1346 &ReceiveBufferSize
1347 );
1348 }
1349 if (Data == 0x0A)
1350 {
1351 //
1352 // TPM_PhysicalEnable
1353 //
1354 ReceiveBufferSize = sizeof(ReceiveBuffer);
1355 Status = TpmMpDriver->Transmit (
1356 TpmMpDriver,
1357 TpmPhysicalEnableCommand,
1358 sizeof (TpmPhysicalEnableCommand),
1359 ReceiveBuffer,
1360 &ReceiveBufferSize
1361 );
1362 //
1363 // TPM_PhysicalSetDeactivated=FALSE
1364 //
1365 ReceiveBufferSize = sizeof(ReceiveBuffer);
1366 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1367 Status = TpmMpDriver->Transmit (
1368 TpmMpDriver,
1369 TpmPhysicalSetDeactivatedCommand,
1370 sizeof (TpmPhysicalSetDeactivatedCommand),
1371 ReceiveBuffer,
1372 &ReceiveBufferSize
1373 );
1374 //
1375 // Do TPM_SetOwnerInstall=TRUE on next reboot
1376 //
1377
1378 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
1379
1380 gRT->ResetSystem (
1381 EfiResetWarm,
1382 EFI_SUCCESS,
1383 0,
1384 NULL
1385 );
1386 }
1387 if (Data == 0x0B)
1388 {
1389 //
1390 // TPM_SetOwnerInstall=FALSE
1391 //
1392 ReceiveBufferSize = sizeof(ReceiveBuffer);
1393 TpmSetOwnerInstallCommand [10] = 0x00;
1394 Status = TpmMpDriver->Transmit (
1395 TpmMpDriver,
1396 TpmSetOwnerInstallCommand,
1397 sizeof (TpmSetOwnerInstallCommand),
1398 ReceiveBuffer,
1399 &ReceiveBufferSize
1400 );
1401 //
1402 // TPM_PhysicalSetDeactivated=TRUE
1403 //
1404 ReceiveBufferSize = sizeof(ReceiveBuffer);
1405 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1406 Status = TpmMpDriver->Transmit (
1407 TpmMpDriver,
1408 TpmPhysicalSetDeactivatedCommand,
1409 sizeof (TpmPhysicalSetDeactivatedCommand),
1410 ReceiveBuffer,
1411 &ReceiveBufferSize
1412 );
1413 //
1414 // TPM_PhysicalDisable
1415 //
1416 ReceiveBufferSize = sizeof(ReceiveBuffer);
1417 Status = TpmMpDriver->Transmit (
1418 TpmMpDriver,
1419 TpmPhysicalDisableCommand,
1420 sizeof (TpmPhysicalDisableCommand),
1421 ReceiveBuffer,
1422 &ReceiveBufferSize
1423 );
1424 gRT->ResetSystem (
1425 EfiResetWarm,
1426 EFI_SUCCESS,
1427 0,
1428 NULL
1429 );
1430 }
1431 if (Data == 0x0E)
1432 {
1433 //
1434 // TPM_ForceClear
1435 //
1436 ReceiveBufferSize = sizeof(ReceiveBuffer);
1437 Status = TpmMpDriver->Transmit (
1438 TpmMpDriver,
1439 TpmForceClearCommand,
1440 sizeof (TpmForceClearCommand),
1441 ReceiveBuffer,
1442 &ReceiveBufferSize
1443 );
1444 //
1445 // TPM_PhysicalEnable
1446 //
1447 ReceiveBufferSize = sizeof(ReceiveBuffer);
1448 Status = TpmMpDriver->Transmit (
1449 TpmMpDriver,
1450 TpmPhysicalEnableCommand,
1451 sizeof (TpmPhysicalEnableCommand),
1452 ReceiveBuffer,
1453 &ReceiveBufferSize
1454 );
1455 //
1456 // TPM_PhysicalSetDeactivated=FALSE
1457 //
1458 ReceiveBufferSize = sizeof(ReceiveBuffer);
1459 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1460 Status = TpmMpDriver->Transmit (
1461 TpmMpDriver,
1462 TpmPhysicalSetDeactivatedCommand,
1463 sizeof (TpmPhysicalSetDeactivatedCommand),
1464 ReceiveBuffer,
1465 &ReceiveBufferSize
1466 );
1467 gRT->ResetSystem (
1468 EfiResetWarm,
1469 EFI_SUCCESS,
1470 0,
1471 NULL
1472 );
1473 }
1474 if (Data == 0xF0)
1475 {
1476 //
1477 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
1478 //
1479 ReceiveBufferSize = sizeof(ReceiveBuffer);
1480 TpmSetOwnerInstallCommand [10] = 0x01;
1481 Status = TpmMpDriver->Transmit (
1482 TpmMpDriver,
1483 TpmSetOwnerInstallCommand,
1484 sizeof (TpmSetOwnerInstallCommand),
1485 ReceiveBuffer,
1486 &ReceiveBufferSize
1487 );
1488 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
1489 }
1490 //
1491 // Deassert Physical Presence
1492 //
1493 TpmPhysicalPresenceCommand [11] = 0x10;
1494 ReceiveBufferSize = sizeof(ReceiveBuffer);
1495 Status = TpmMpDriver->Transmit (
1496 TpmMpDriver,
1497 TpmPhysicalPresenceCommand,
1498 sizeof (TpmPhysicalPresenceCommand),
1499 ReceiveBuffer,
1500 &ReceiveBufferSize
1501 );
1502 }
1503 }
1504
1505 return;
1506 }
1507
1508 /**
1509
1510 Initializes manufacturing and config mode setting.
1511
1512 **/
1513 VOID
1514 InitMfgAndConfigModeStateVar()
1515 {
1516 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1517 VOID *HobList;
1518
1519
1520 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1521 if (HobList != NULL) {
1522 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1523
1524 //
1525 // Check if in Manufacturing mode
1526 //
1527 if ( !CompareMem (
1528 &BootModeBuffer->SetupName,
1529 MANUFACTURE_SETUP_NAME,
1530 StrSize (MANUFACTURE_SETUP_NAME)
1531 ) ) {
1532 mMfgMode = TRUE;
1533 }
1534
1535
1536
1537 }
1538
1539 }
1540
1541 /**
1542
1543 Initializes manufacturing and config mode setting.
1544
1545 **/
1546 VOID
1547 InitPlatformBootMode()
1548 {
1549 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1550 VOID *HobList;
1551
1552 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1553 if (HobList != NULL) {
1554 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1555 mPlatformBootMode = BootModeBuffer->PlatformBootMode;
1556 }
1557 }
1558
1559 /**
1560
1561 Initializes ITK.
1562
1563 **/
1564 VOID
1565 InitItk(
1566 )
1567 {
1568 EFI_STATUS Status;
1569 UINT16 ItkModBiosState;
1570 UINT8 Value;
1571 UINTN DataSize;
1572 UINT32 Attributes;
1573
1574 //
1575 // Setup local variable according to ITK variable
1576 //
1577 //
1578 // Read ItkBiosModVar to determine if BIOS has been modified by ITK
1579 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
1580 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
1581 //
1582 DataSize = sizeof (Value);
1583 Status = gRT->GetVariable (
1584 ITK_BIOS_MOD_VAR_NAME,
1585 &gItkDataVarGuid,
1586 &Attributes,
1587 &DataSize,
1588 &Value
1589 );
1590 if (Status == EFI_NOT_FOUND) {
1591 //
1592 // Variable not found, hasn't been initialized, intialize to 0
1593 //
1594 Value=0x00;
1595 //
1596 // Write variable to flash.
1597 //
1598 gRT->SetVariable (
1599 ITK_BIOS_MOD_VAR_NAME,
1600 &gItkDataVarGuid,
1601 EFI_VARIABLE_RUNTIME_ACCESS |
1602 EFI_VARIABLE_NON_VOLATILE |
1603 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1604 sizeof (Value),
1605 &Value
1606 );
1607
1608 }
1609 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
1610 if (Value == 0x00) {
1611 ItkModBiosState = 0x00;
1612 } else {
1613 ItkModBiosState = 0x01;
1614 }
1615 gRT->SetVariable (
1616 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
1617 &gEfiNormalSetupGuid,
1618 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1619 2,
1620 (void *)&ItkModBiosState
1621 );
1622 }
1623 }
1624
1625 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
1626
1627 /**
1628
1629 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
1630
1631 **/
1632 STATIC
1633 VOID
1634 InitFirmwareId(
1635 )
1636 {
1637 EFI_STATUS Status;
1638 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
1639
1640 //
1641 // First try writing the variable without a password in case we are
1642 // upgrading from a BIOS without password protection on the FirmwareId
1643 //
1644 Status = gRT->SetVariable(
1645 (CHAR16 *)&gFirmwareIdName,
1646 &gFirmwareIdGuid,
1647 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1648 EFI_VARIABLE_RUNTIME_ACCESS,
1649 sizeof( FIRMWARE_ID ) - 1,
1650 FIRMWARE_ID
1651 );
1652
1653 if (Status == EFI_INVALID_PARAMETER) {
1654
1655 //
1656 // Since setting the firmware id without the password failed,
1657 // a password must be required.
1658 //
1659 Status = gRT->SetVariable(
1660 (CHAR16 *)&FirmwareIdNameWithPassword,
1661 &gFirmwareIdGuid,
1662 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1663 EFI_VARIABLE_RUNTIME_ACCESS,
1664 sizeof( FIRMWARE_ID ) - 1,
1665 FIRMWARE_ID
1666 );
1667 }
1668 }
1669 #endif
1670
1671 VOID
1672 UpdateDVMTSetup(
1673 )
1674 {
1675 //
1676 // Workaround to support IIA bug.
1677 // IIA request to change option value to 4, 5 and 7 relatively
1678 // instead of 1, 2, and 3 which follow Lakeport Specs.
1679 // Check option value, temporary hardcode GraphicsDriverMemorySize
1680 // Option value to fulfill IIA requirment. So that user no need to
1681 // load default and update setupvariable after update BIOS.
1682 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
1683 // *This is for broadwater and above product only.
1684 //
1685
1686 SYSTEM_CONFIGURATION SystemConfiguration;
1687 UINTN VarSize;
1688 EFI_STATUS Status;
1689
1690 VarSize = sizeof(SYSTEM_CONFIGURATION);
1691 Status = gRT->GetVariable(
1692 NORMAL_SETUP_NAME,
1693 &gEfiNormalSetupGuid,
1694 NULL,
1695 &VarSize,
1696 &SystemConfiguration
1697 );
1698
1699 if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
1700 //The setup variable is corrupted
1701 VarSize = sizeof(SYSTEM_CONFIGURATION);
1702 Status = gRT->GetVariable(
1703 L"SetupRecovery",
1704 &gEfiNormalSetupGuid,
1705 NULL,
1706 &VarSize,
1707 &SystemConfiguration
1708 );
1709 ASSERT_EFI_ERROR (Status);
1710 }
1711
1712 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
1713 switch (SystemConfiguration.GraphicsDriverMemorySize){
1714 case 1:
1715 SystemConfiguration.GraphicsDriverMemorySize = 4;
1716 break;
1717 case 2:
1718 SystemConfiguration.GraphicsDriverMemorySize = 5;
1719 break;
1720 case 3:
1721 SystemConfiguration.GraphicsDriverMemorySize = 7;
1722 break;
1723 default:
1724 break;
1725 }
1726
1727 Status = gRT->SetVariable (
1728 NORMAL_SETUP_NAME,
1729 &gEfiNormalSetupGuid,
1730 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
1731 sizeof(SYSTEM_CONFIGURATION),
1732 &SystemConfiguration
1733 );
1734 }
1735 }
1736
1737 VOID
1738 InitPlatformUsbPolicy (
1739 VOID
1740 )
1741
1742 {
1743 EFI_HANDLE Handle;
1744 EFI_STATUS Status;
1745
1746 Handle = NULL;
1747
1748 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
1749 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
1750 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
1751 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
1752 } else {
1753 mUsbPolicyData.UsbEmulationSize = 0;
1754 }
1755 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;
1756 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
1757
1758 //
1759 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
1760 //
1761 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
1762
1763 //
1764 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
1765 //
1766 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
1767
1768 //
1769 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
1770 //
1771 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
1772
1773 //
1774 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
1775 // default is Ich acpibase =0x040. acpitimerreg=0x08.
1776 mUsbPolicyData.LpcAcpiBase = 0x40;
1777 mUsbPolicyData.AcpiTimerReg = 0x08;
1778
1779 //
1780 // Set for reduce usb post time
1781 //
1782 mUsbPolicyData.UsbTimeTue = 0x00;
1783 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH
1784 mUsbPolicyData.EnumWaitPortStableStall = 100;
1785
1786
1787 Status = gBS->InstallProtocolInterface (
1788 &Handle,
1789 &gUsbPolicyGuid,
1790 EFI_NATIVE_INTERFACE,
1791 &mUsbPolicyData
1792 );
1793 ASSERT_EFI_ERROR(Status);
1794
1795 }
1796
1797 UINT8
1798 ReadCmosBank1Byte (
1799 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1800 IN UINT8 Index
1801 )
1802 {
1803 UINT8 Data;
1804
1805 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
1806 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
1807 return Data;
1808 }
1809
1810 VOID
1811 WriteCmosBank1Byte (
1812 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1813 IN UINT8 Index,
1814 IN UINT8 Data
1815 )
1816 {
1817 CpuIo->Io.Write (
1818 CpuIo,
1819 EfiCpuIoWidthUint8,
1820 0x72,
1821 1,
1822 &Index
1823 );
1824 CpuIo->Io.Write (
1825 CpuIo,
1826 EfiCpuIoWidthUint8,
1827 0x73,
1828 1,
1829 &Data
1830 );
1831 }
1832
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