3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.
24 #include "PlatformEarlyInit.h"
28 UpdateDefaultSetupValue (
29 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
36 PEI termination callback.
38 @param PeiServices General purpose services available to every PEIM.
39 @param NotifyDescriptor Not uesed.
42 @retval EFI_SUCCESS If the interface could be successfully
48 EndOfPeiPpiNotifyCallback (
49 IN CONST EFI_PEI_SERVICES
**PeiServices
,
50 IN EFI_PEI_NOTIFY_DESCRIPTOR
*NotifyDescriptor
,
56 UINT64 LowUncableBase
;
57 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
59 EFI_BOOT_MODE BootMode
;
60 EFI_PEI_HOB_POINTERS Hob
;
62 Status
= (*PeiServices
)->GetBootMode(
67 ASSERT_EFI_ERROR (Status
);
70 // Set the some PCI and chipset range as UC
71 // And align to 1M at leaset
73 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
74 ASSERT (Hob
.Raw
!= NULL
);
75 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
77 UpdateDefaultSetupValue (PlatformInfo
);
79 DEBUG ((EFI_D_ERROR
, "Memory TOLM: %X\n", PlatformInfo
->MemData
.MemTolm
));
80 DEBUG ((EFI_D_ERROR
, "PCIE OSBASE: %lX\n", PlatformInfo
->PciData
.PciExpressBase
));
83 "PCIE BASE: %lX Size : %X\n",
84 PlatformInfo
->PciData
.PciExpressBase
,
85 PlatformInfo
->PciData
.PciExpressSize
)
89 "PCI32 BASE: %X Limit: %X\n",
90 PlatformInfo
->PciData
.PciResourceMem32Base
,
91 PlatformInfo
->PciData
.PciResourceMem32Limit
)
95 "PCI64 BASE: %lX Limit: %lX\n",
96 PlatformInfo
->PciData
.PciResourceMem64Base
,
97 PlatformInfo
->PciData
.PciResourceMem64Limit
)
99 DEBUG ((EFI_D_ERROR
, "UC START: %lX End : %lX\n", PlatformInfo
->MemData
.MemMir0
, PlatformInfo
->MemData
.MemMir1
));
101 LowUncableBase
= PlatformInfo
->MemData
.MemMaxTolm
;
102 LowUncableBase
&= (0x0FFF00000);
103 MemoryTop
= (0x100000000);
105 if (BootMode
!= BOOT_ON_S3_RESUME
) {
107 // In BIOS, HECBASE will be always below 4GB
109 HecBaseHigh
= (UINT32
) RShiftU64 (PlatformInfo
->PciData
.PciExpressBase
, 28);
110 ASSERT (HecBaseHigh
< 16);
117 Install Firmware Volume Hob's once there is main memory
119 @param PeiServices General purpose services available to every PEIM.
120 @param NotifyDescriptor Notify that this module published.
121 @param Ppi PPI that was installed.
123 @retval EFI_SUCCESS The function completed successfully.
128 MemoryDiscoveredPpiNotifyCallback (
129 IN CONST EFI_PEI_SERVICES
**PeiServices
,
130 IN EFI_PEI_NOTIFY_DESCRIPTOR
*NotifyDescriptor
,
135 EFI_BOOT_MODE BootMode
;
136 EFI_CPUID_REGISTER FeatureInfo
;
137 UINT8 CpuAddressWidth
;
139 EFI_PEI_HOB_POINTERS Hob
;
140 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
141 UINT32 RootComplexBar
;
149 // Get Platform Info HOB
151 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
152 ASSERT (Hob
.Raw
!= NULL
);
153 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
155 Status
= (*PeiServices
)->GetBootMode (PeiServices
, &BootMode
);
158 // Check if user wants to turn off in PEI phase
160 if ((BootMode
!= BOOT_ON_S3_RESUME
) && (BootMode
!= BOOT_ON_FLASH_UPDATE
)) {
163 Pm1Cnt
= IoRead16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_CNT
);
164 Pm1Cnt
&= ~B_PCH_ACPI_PM1_CNT_SLP_TYP
;
165 IoWrite16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_CNT
, Pm1Cnt
);
168 #ifndef MINNOW2_FSP_BUILD
170 // Set PEI cache mode here
172 SetPeiCacheMode (PeiServices
);
176 // Pulish memory tyoe info
178 PublishMemoryTypeInfo ();
181 // Work done if on a S3 resume
183 if (BootMode
== BOOT_ON_S3_RESUME
) {
185 //Program the side band packet register to send a sideband message to Punit
186 //To indicate that DRAM has been initialized and PUNIT FW base address in memory.
191 RootComplexBar
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_RCBA
) & B_PCH_LPC_RCBA_BAR
;
192 BuildResourceDescriptorHob (
193 EFI_RESOURCE_MEMORY_MAPPED_IO
,
194 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
198 DEBUG ((EFI_D_INFO
, "RootComplexBar : 0x%x\n", RootComplexBar
));
200 PmcBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_PMC_BASE
) & B_PCH_LPC_PMC_BASE_BAR
;
201 BuildResourceDescriptorHob (
202 EFI_RESOURCE_MEMORY_MAPPED_IO
,
203 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
207 DEBUG ((EFI_D_INFO
, "PmcBase : 0x%x\n", PmcBase
));
209 IoBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_IO_BASE
) & B_PCH_LPC_IO_BASE_BAR
;
210 BuildResourceDescriptorHob (
211 EFI_RESOURCE_MEMORY_MAPPED_IO
,
212 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
216 DEBUG ((EFI_D_INFO
, "IoBase : 0x%x\n", IoBase
));
218 IlbBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_ILB_BASE
) & B_PCH_LPC_ILB_BASE_BAR
;
219 BuildResourceDescriptorHob (
220 EFI_RESOURCE_MEMORY_MAPPED_IO
,
221 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
225 DEBUG ((EFI_D_INFO
, "IlbBase : 0x%x\n", IlbBase
));
227 SpiBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_SPI_BASE
) & B_PCH_LPC_SPI_BASE_BAR
;
228 BuildResourceDescriptorHob (
229 EFI_RESOURCE_MEMORY_MAPPED_IO
,
230 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
234 DEBUG ((EFI_D_INFO
, "SpiBase : 0x%x\n", SpiBase
));
236 MphyBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_MPHY_BASE
) & B_PCH_LPC_MPHY_BASE_BAR
;
237 BuildResourceDescriptorHob (
238 EFI_RESOURCE_MEMORY_MAPPED_IO
,
239 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
243 DEBUG ((EFI_D_INFO
, "MphyBase : 0x%x\n", MphyBase
));
248 BuildResourceDescriptorHob (
249 EFI_RESOURCE_MEMORY_MAPPED_IO
,
250 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
254 DEBUG ((EFI_D_INFO
, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS
));
259 BuildResourceDescriptorHob (
260 EFI_RESOURCE_MEMORY_MAPPED_IO
,
261 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
265 DEBUG ((EFI_D_INFO
, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS
));
268 // Adding the PCIE Express area to the E820 memory table as type 2 memory.
270 BuildResourceDescriptorHob (
271 EFI_RESOURCE_MEMORY_MAPPED_IO
,
272 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
273 PlatformInfo
->PciData
.PciExpressBase
,
274 PlatformInfo
->PciData
.PciExpressSize
276 DEBUG ((EFI_D_INFO
, "PciExpressBase : 0x%x\n", PlatformInfo
->PciData
.PciExpressBase
));
279 // Adding the Flashpart to the E820 memory table as type 2 memory.
281 BuildResourceDescriptorHob (
282 EFI_RESOURCE_FIRMWARE_DEVICE
,
283 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
284 FixedPcdGet32 (PcdFlashAreaBaseAddress
),
285 FixedPcdGet32 (PcdFlashAreaSize
)
287 DEBUG ((EFI_D_INFO
, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress
)));
290 // Create a CPU hand-off information
292 CpuAddressWidth
= 32;
293 AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION
, &FeatureInfo
.RegEax
, &FeatureInfo
.RegEbx
, &FeatureInfo
.RegEcx
, &FeatureInfo
.RegEdx
);
294 if (FeatureInfo
.RegEax
>= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE
) {
295 AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE
, &FeatureInfo
.RegEax
, &FeatureInfo
.RegEbx
, &FeatureInfo
.RegEcx
, &FeatureInfo
.RegEdx
);
296 CpuAddressWidth
= (UINT8
) (FeatureInfo
.RegEax
& 0xFF);
299 BuildCpuHob(CpuAddressWidth
, 16);
300 ASSERT_EFI_ERROR (Status
);
309 IN EFI_FIRMWARE_VOLUME_HEADER
*FwVolHeader
317 // Verify the header revision, header signature, length
318 // Length of FvBlock cannot be 2**64-1
319 // HeaderLength cannot be an odd number
321 if ((FwVolHeader
->Revision
!= EFI_FVH_REVISION
) ||
322 (FwVolHeader
->Signature
!= EFI_FVH_SIGNATURE
) ||
323 (FwVolHeader
->FvLength
== ((UINT64
) -1)) ||
324 ((FwVolHeader
->HeaderLength
& 0x01) != 0)
326 return EFI_NOT_FOUND
;
330 // Verify the header checksum
332 HeaderLength
= (UINT16
) (FwVolHeader
->HeaderLength
/ 2);
333 Ptr
= (UINT16
*) FwVolHeader
;
335 while (HeaderLength
> 0) {
341 return EFI_NOT_FOUND
;