3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.
24 #include "PlatformEarlyInit.h"
28 UpdateDefaultSetupValue (
29 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
36 PEI termination callback.
38 @param PeiServices General purpose services available to every PEIM.
39 @param NotifyDescriptor Not uesed.
42 @retval EFI_SUCCESS If the interface could be successfully
48 EndOfPeiPpiNotifyCallback (
49 IN CONST EFI_PEI_SERVICES
**PeiServices
,
50 IN EFI_PEI_NOTIFY_DESCRIPTOR
*NotifyDescriptor
,
55 UINT64 LowUncableBase
;
56 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
58 EFI_BOOT_MODE BootMode
;
59 EFI_PEI_HOB_POINTERS Hob
;
61 Status
= (*PeiServices
)->GetBootMode(
66 ASSERT_EFI_ERROR (Status
);
69 // Set the some PCI and chipset range as UC
70 // And align to 1M at leaset
72 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
73 ASSERT (Hob
.Raw
!= NULL
);
74 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
76 UpdateDefaultSetupValue (PlatformInfo
);
78 DEBUG ((EFI_D_ERROR
, "Memory TOLM: %X\n", PlatformInfo
->MemData
.MemTolm
));
79 DEBUG ((EFI_D_ERROR
, "PCIE OSBASE: %lX\n", PlatformInfo
->PciData
.PciExpressBase
));
82 "PCIE BASE: %lX Size : %X\n",
83 PlatformInfo
->PciData
.PciExpressBase
,
84 PlatformInfo
->PciData
.PciExpressSize
)
88 "PCI32 BASE: %X Limit: %X\n",
89 PlatformInfo
->PciData
.PciResourceMem32Base
,
90 PlatformInfo
->PciData
.PciResourceMem32Limit
)
94 "PCI64 BASE: %lX Limit: %lX\n",
95 PlatformInfo
->PciData
.PciResourceMem64Base
,
96 PlatformInfo
->PciData
.PciResourceMem64Limit
)
98 DEBUG ((EFI_D_ERROR
, "UC START: %lX End : %lX\n", PlatformInfo
->MemData
.MemMir0
, PlatformInfo
->MemData
.MemMir1
));
100 LowUncableBase
= PlatformInfo
->MemData
.MemMaxTolm
;
101 LowUncableBase
&= (0x0FFF00000);
103 if (BootMode
!= BOOT_ON_S3_RESUME
) {
105 // In BIOS, HECBASE will be always below 4GB
107 HecBaseHigh
= (UINT32
) RShiftU64 (PlatformInfo
->PciData
.PciExpressBase
, 28);
108 ASSERT (HecBaseHigh
< 16);
115 Install Firmware Volume Hob's once there is main memory
117 @param PeiServices General purpose services available to every PEIM.
118 @param NotifyDescriptor Notify that this module published.
119 @param Ppi PPI that was installed.
121 @retval EFI_SUCCESS The function completed successfully.
126 MemoryDiscoveredPpiNotifyCallback (
127 IN CONST EFI_PEI_SERVICES
**PeiServices
,
128 IN EFI_PEI_NOTIFY_DESCRIPTOR
*NotifyDescriptor
,
133 EFI_BOOT_MODE BootMode
;
134 EFI_CPUID_REGISTER FeatureInfo
;
135 UINT8 CpuAddressWidth
;
137 EFI_PEI_HOB_POINTERS Hob
;
138 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
139 UINT32 RootComplexBar
;
147 // Get Platform Info HOB
149 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
150 ASSERT (Hob
.Raw
!= NULL
);
151 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
153 Status
= (*PeiServices
)->GetBootMode (PeiServices
, &BootMode
);
156 // Check if user wants to turn off in PEI phase
158 if ((BootMode
!= BOOT_ON_S3_RESUME
) && (BootMode
!= BOOT_ON_FLASH_UPDATE
)) {
161 Pm1Cnt
= IoRead16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_CNT
);
162 Pm1Cnt
&= ~B_PCH_ACPI_PM1_CNT_SLP_TYP
;
163 IoWrite16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_CNT
, Pm1Cnt
);
166 #ifndef MINNOW2_FSP_BUILD
168 // Set PEI cache mode here
170 SetPeiCacheMode (PeiServices
);
174 // Pulish memory tyoe info
176 PublishMemoryTypeInfo ();
179 // Work done if on a S3 resume
181 if (BootMode
== BOOT_ON_S3_RESUME
) {
183 //Program the side band packet register to send a sideband message to Punit
184 //To indicate that DRAM has been initialized and PUNIT FW base address in memory.
189 RootComplexBar
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_RCBA
) & B_PCH_LPC_RCBA_BAR
;
190 BuildResourceDescriptorHob (
191 EFI_RESOURCE_MEMORY_MAPPED_IO
,
192 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
196 DEBUG ((EFI_D_INFO
, "RootComplexBar : 0x%x\n", RootComplexBar
));
198 PmcBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_PMC_BASE
) & B_PCH_LPC_PMC_BASE_BAR
;
199 BuildResourceDescriptorHob (
200 EFI_RESOURCE_MEMORY_MAPPED_IO
,
201 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
205 DEBUG ((EFI_D_INFO
, "PmcBase : 0x%x\n", PmcBase
));
207 IoBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_IO_BASE
) & B_PCH_LPC_IO_BASE_BAR
;
208 BuildResourceDescriptorHob (
209 EFI_RESOURCE_MEMORY_MAPPED_IO
,
210 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
214 DEBUG ((EFI_D_INFO
, "IoBase : 0x%x\n", IoBase
));
216 IlbBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_ILB_BASE
) & B_PCH_LPC_ILB_BASE_BAR
;
217 BuildResourceDescriptorHob (
218 EFI_RESOURCE_MEMORY_MAPPED_IO
,
219 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
223 DEBUG ((EFI_D_INFO
, "IlbBase : 0x%x\n", IlbBase
));
225 SpiBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_SPI_BASE
) & B_PCH_LPC_SPI_BASE_BAR
;
226 BuildResourceDescriptorHob (
227 EFI_RESOURCE_MEMORY_MAPPED_IO
,
228 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
232 DEBUG ((EFI_D_INFO
, "SpiBase : 0x%x\n", SpiBase
));
234 MphyBase
= MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH
, PCI_DEVICE_NUMBER_PCH_LPC
, 0, R_PCH_LPC_MPHY_BASE
) & B_PCH_LPC_MPHY_BASE_BAR
;
235 BuildResourceDescriptorHob (
236 EFI_RESOURCE_MEMORY_MAPPED_IO
,
237 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
241 DEBUG ((EFI_D_INFO
, "MphyBase : 0x%x\n", MphyBase
));
246 BuildResourceDescriptorHob (
247 EFI_RESOURCE_MEMORY_MAPPED_IO
,
248 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
252 DEBUG ((EFI_D_INFO
, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS
));
257 BuildResourceDescriptorHob (
258 EFI_RESOURCE_MEMORY_MAPPED_IO
,
259 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
263 DEBUG ((EFI_D_INFO
, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS
));
266 // Adding the PCIE Express area to the E820 memory table as type 2 memory.
268 BuildResourceDescriptorHob (
269 EFI_RESOURCE_MEMORY_MAPPED_IO
,
270 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
271 PlatformInfo
->PciData
.PciExpressBase
,
272 PlatformInfo
->PciData
.PciExpressSize
274 DEBUG ((EFI_D_INFO
, "PciExpressBase : 0x%x\n", PlatformInfo
->PciData
.PciExpressBase
));
277 // Adding the Flashpart to the E820 memory table as type 2 memory.
279 BuildResourceDescriptorHob (
280 EFI_RESOURCE_FIRMWARE_DEVICE
,
281 (EFI_RESOURCE_ATTRIBUTE_PRESENT
| EFI_RESOURCE_ATTRIBUTE_INITIALIZED
| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
),
282 FixedPcdGet32 (PcdFlashAreaBaseAddress
),
283 FixedPcdGet32 (PcdFlashAreaSize
)
285 DEBUG ((EFI_D_INFO
, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress
)));
288 // Create a CPU hand-off information
290 CpuAddressWidth
= 32;
291 AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION
, &FeatureInfo
.RegEax
, &FeatureInfo
.RegEbx
, &FeatureInfo
.RegEcx
, &FeatureInfo
.RegEdx
);
292 if (FeatureInfo
.RegEax
>= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE
) {
293 AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE
, &FeatureInfo
.RegEax
, &FeatureInfo
.RegEbx
, &FeatureInfo
.RegEcx
, &FeatureInfo
.RegEdx
);
294 CpuAddressWidth
= (UINT8
) (FeatureInfo
.RegEax
& 0xFF);
297 BuildCpuHob(CpuAddressWidth
, 16);
298 ASSERT_EFI_ERROR (Status
);
307 IN EFI_FIRMWARE_VOLUME_HEADER
*FwVolHeader
315 // Verify the header revision, header signature, length
316 // Length of FvBlock cannot be 2**64-1
317 // HeaderLength cannot be an odd number
319 if ((FwVolHeader
->Revision
!= EFI_FVH_REVISION
) ||
320 (FwVolHeader
->Signature
!= EFI_FVH_SIGNATURE
) ||
321 (FwVolHeader
->FvLength
== ((UINT64
) -1)) ||
322 ((FwVolHeader
->HeaderLength
& 0x01) != 0)
324 return EFI_NOT_FOUND
;
328 // Verify the header checksum
330 HeaderLength
= (UINT16
) (FwVolHeader
->HeaderLength
/ 2);
331 Ptr
= (UINT16
*) FwVolHeader
;
333 while (HeaderLength
> 0) {
339 return EFI_NOT_FOUND
;