3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Do platform specific PEI stage initializations.
26 #include "PlatformEarlyInit.h"
29 #pragma GCC push_options
30 #pragma GCC optimize ("O0")
32 #pragma optimize ("", off)
37 static EFI_PEI_STALL_PPI mStallPpi
= {
42 static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi
= {
43 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
49 // The reserved SMBus addresses are defined in PlatformDxe.h file.
51 static UINT8 mSmbusRsvdAddresses
[] = PLATFORM_SMBUS_RSVD_ADDRESSES
;
52 static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi
= {
55 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES
,
59 static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi
= {
60 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
61 &gPeiSmbusPolicyPpiGuid
,
64 static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi
= {
69 static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi
= {
70 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
71 &gPeiSpeakerInterfacePpiGuid
,
75 static EFI_PEI_RESET_PPI mResetPpi
= { IchReset
};
78 static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi
= {
79 (EFI_PEI_FIND_FV_FINDFV
)FindFv
82 static EFI_PEI_PPI_DESCRIPTOR mPpiList
[] = {
84 EFI_PEI_PPI_DESCRIPTOR_PPI
,
85 &gEfiPeiMasterBootModePpiGuid
,
89 EFI_PEI_PPI_DESCRIPTOR_PPI
,
94 (EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
),
100 static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList
[] = {
102 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK
,
103 &gEfiEndOfPeiSignalPpiGuid
,
104 (EFI_PEIM_NOTIFY_ENTRY_POINT
)EndOfPeiPpiNotifyCallback
107 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
),
108 &gEfiPeiMemoryDiscoveredPpiGuid
,
109 (EFI_PEIM_NOTIFY_ENTRY_POINT
)MemoryDiscoveredPpiNotifyCallback
117 Parse the status registers for figuring out the wake-up event and save it into
118 an GUID HOB which will be referenced later. However, modification is required
119 to meet the chipset register definition and the practical hardware design. Thus,
120 this is just an example.
123 @param PeiServices pointer to the PEI Service Table
124 @param EFI_SUCCESS Always return Success
132 GetWakeupEventAndSaveToHob (
133 IN CONST EFI_PEI_SERVICES
**PeiServices
141 // Read the ACPI registers
143 Pm1Sts
= IoRead16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_STS
);
144 Gpe0Sts
= IoRead32 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_GPE0a_STS
);
147 // Figure out the wake-up event
149 if ((Pm1Sts
& B_PCH_ACPI_PM1_STS_PWRBTN
) != 0) {
150 WakeEventData
= SMBIOS_WAKEUP_TYPE_POWER_SWITCH
;
151 } else if (((Pm1Sts
& B_PCH_ACPI_PM1_STS_WAK
) != 0)) {
152 WakeEventData
= SMBIOS_WAKEUP_TYPE_PCI_PME
;
153 } else if (Gpe0Sts
!= 0) {
154 WakeEventData
= SMBIOS_WAKEUP_TYPE_OTHERS
;
156 WakeEventData
= SMBIOS_WAKEUP_TYPE_UNKNOWN
;
159 DEBUG ((EFI_D_ERROR
, "ACPI Wake Status Register: %04x\n", Pm1Sts
));
166 IN CONST EFI_PEI_SERVICES
**PeiServices
,
167 IN SYSTEM_CONFIGURATION
*SystemConfiguration
172 EFI_PEI_READ_ONLY_VARIABLE2_PPI
*Variable
;
174 VariableSize
= sizeof (SYSTEM_CONFIGURATION
);
175 ZeroMem (SystemConfiguration
, sizeof (SYSTEM_CONFIGURATION
));
177 Status
= (*PeiServices
)->LocatePpi (
179 &gEfiPeiReadOnlyVariable2PpiGuid
,
184 ASSERT_EFI_ERROR (Status
);
187 // Use normal setup default from NVRAM variable,
188 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
190 VariableSize
= sizeof(SYSTEM_CONFIGURATION
);
191 Status
= Variable
->GetVariable (
194 &gEfiSetupVariableGuid
,
199 if (EFI_ERROR (Status
) || VariableSize
!= sizeof(SYSTEM_CONFIGURATION
)) {
200 //The setup variable is corrupted
201 VariableSize
= sizeof(SYSTEM_CONFIGURATION
);
202 Status
= Variable
->GetVariable(
205 &gEfiSetupVariableGuid
,
210 ASSERT_EFI_ERROR (Status
);
217 IN CONST EFI_PEI_SERVICES
**PeiServices
,
218 IN SYSTEM_CONFIGURATION
*SystemConfiguration
222 EFI_PEI_PPI_DESCRIPTOR
*mVlvPolicyPpiDesc
;
223 VLV_POLICY_PPI
*mVlvPolicyPpi
;
225 Status
= (*PeiServices
)->AllocatePool(
227 sizeof (EFI_PEI_PPI_DESCRIPTOR
),
228 (void **)&mVlvPolicyPpiDesc
230 ASSERT_EFI_ERROR (Status
);
232 Status
= (*PeiServices
)->AllocatePool(
234 sizeof (VLV_POLICY_PPI
),
235 (void **)&mVlvPolicyPpi
237 ASSERT_EFI_ERROR (Status
);
242 (*PeiServices
)->SetMem ((VOID
*)mVlvPolicyPpi
, sizeof (VLV_POLICY_PPI
), 0);
243 mVlvPolicyPpiDesc
->Flags
= EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
;
244 mVlvPolicyPpiDesc
->Guid
= &gVlvPolicyPpiGuid
;
245 mVlvPolicyPpiDesc
->Ppi
= mVlvPolicyPpi
;
246 mVlvPolicyPpi
->GtConfig
.PrimaryDisplay
= SystemConfiguration
->PrimaryVideoAdaptor
;
247 mVlvPolicyPpi
->GtConfig
.IgdDvmt50PreAlloc
= SystemConfiguration
->IgdDvmt50PreAlloc
;
248 mVlvPolicyPpi
->GtConfig
.ApertureSize
= SystemConfiguration
->IgdApertureSize
;
249 mVlvPolicyPpi
->GtConfig
.GttSize
= SystemConfiguration
->GTTSize
;
250 if (SystemConfiguration
->PrimaryVideoAdaptor
!= 2) {
251 mVlvPolicyPpi
->GtConfig
.InternalGraphics
= SystemConfiguration
->Igd
;
253 mVlvPolicyPpi
->GtConfig
.InternalGraphics
= 0;
257 mVlvPolicyPpi
->GtConfig
.IgdTurboEn
= 1;
260 mVlvPolicyPpi
->PlatformData
.FastBoot
= SystemConfiguration
->FastBoot
;
261 mVlvPolicyPpi
->PlatformData
.DynSR
= 1;
262 DEBUG ((EFI_D_ERROR
, "Setup Option ISPEn: 0x%x\n", SystemConfiguration
->ISPEn
));
263 mVlvPolicyPpi
->ISPEn
= SystemConfiguration
->ISPEn
;
264 DEBUG ((EFI_D_ERROR
, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration
->ISPDevSel
));
265 mVlvPolicyPpi
->ISPPciDevConfig
= SystemConfiguration
->ISPDevSel
;
266 if (SystemConfiguration
->ISPEn
== 0) {
267 mVlvPolicyPpi
->ISPPciDevConfig
= 0;
268 DEBUG ((EFI_D_ERROR
, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi
->ISPPciDevConfig
));
270 Status
= (*PeiServices
)->InstallPpi(
274 ASSERT_EFI_ERROR (Status
);
282 IN SYSTEM_CONFIGURATION
*SystemConfiguration
286 DEBUG ((EFI_D_ERROR
, "ConfigureSoCGpio------------start\n"));
287 if (SystemConfiguration
->eMMCBootMode
== 1) {// Auto detection mode
288 DEBUG ((EFI_D_ERROR
, "Auto detection mode------------start\n"));
293 switch (PchStepping()) {
294 case PchA0
: // SOC A0 and A1
296 DEBUG ((EFI_D_ERROR
, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
297 SystemConfiguration
->LpsseMMCEnabled
= 1;
298 SystemConfiguration
->LpsseMMC45Enabled
= 0;
300 case PchB0
: // SOC B0 and later
302 DEBUG ((EFI_D_ERROR
, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
303 SystemConfiguration
->LpsseMMCEnabled
= 0;
304 SystemConfiguration
->LpsseMMC45Enabled
= 1;
307 } else if (SystemConfiguration
->eMMCBootMode
== 2) { // eMMC 4.41
308 DEBUG ((EFI_D_ERROR
, "Force to eMMC 4.41 GPIO Configuration\n"));
309 SystemConfiguration
->LpsseMMCEnabled
= 1;
310 SystemConfiguration
->LpsseMMC45Enabled
= 0;
311 } else if (SystemConfiguration
->eMMCBootMode
== 3) { // eMMC 4.5
312 DEBUG ((EFI_D_ERROR
, "Force to eMMC 4.5 GPIO Configuration\n"));
313 SystemConfiguration
->LpsseMMCEnabled
= 0;
314 SystemConfiguration
->LpsseMMC45Enabled
= 1;
316 } else { // Disable eMMC controllers
317 DEBUG ((EFI_D_ERROR
, "Disable eMMC GPIO controllers\n"));
318 SystemConfiguration
->LpsseMMCEnabled
= 0;
319 SystemConfiguration
->LpsseMMC45Enabled
= 0;
324 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
325 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
326 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
327 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
328 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
329 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
330 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
331 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
332 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
333 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
334 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
336 if (SystemConfiguration
->LpsseMMCEnabled
== 1) {
337 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03E0, 0x2003ED01); //EMMC 4.41
338 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0390, 0x2003EC81);
339 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03D0, 0x2003EC81);
340 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0400, 0x2003EC81);
341 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03B0, 0x2003EC81);
342 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0360, 0x2003EC81);
343 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0380, 0x2003EC81);
344 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03C0, 0x2003EC81);
345 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0370, 0x2003EC81);
346 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03F0, 0x2003EC81);
347 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0330, 0x2003ED01);
352 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
353 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
354 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
355 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
356 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
357 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
358 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
359 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
360 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
361 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
362 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
364 if (SystemConfiguration
->LpsseMMC45Enabled
== 1) {
365 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03E0, 0x2003ED03); // EMMC 4.5
366 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0390, 0x2003EC83);
367 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03D0, 0x2003EC83);
368 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0400, 0x2003EC83);
369 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03B0, 0x2003EC83);
370 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0360, 0x2003EC83);
371 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0380, 0x2003EC83);
372 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03C0, 0x2003EC83);
373 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0370, 0x2003EC83);
374 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03F0, 0x2003EC83);
375 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0330, 0x2003ED03);
380 // Change GPIOC_0 setting to allow MMIO access under Android.
382 IoWrite32 (GPIO_BASE_ADDRESS
+ R_PCH_GPIO_SC_USE_SEL
,
383 (IoRead32(GPIO_BASE_ADDRESS
+ R_PCH_GPIO_SC_USE_SEL
) & (UINT32
)~BIT0
));
384 DEBUG ((EFI_D_ERROR
, "ConfigureSoCGpio------------end\n"));
390 IN CONST EFI_PEI_SERVICES
**PeiServices
,
391 IN SYSTEM_CONFIGURATION
*SystemConfiguration
394 if (SystemConfiguration
->MeasuredBootEnable
) {
395 PcdSetBool (PcdMeasuredBootEnable
, TRUE
);
397 PcdSetBool (PcdMeasuredBootEnable
, FALSE
);
405 ConfigureLpssAndSccGpio (
406 IN SYSTEM_CONFIGURATION
*SystemConfiguration
,
407 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
410 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
411 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
412 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
413 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
415 DEBUG ((EFI_D_ERROR
, "ConfigureLpssAndSccGpio------------start\n"));
419 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
421 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
423 if (SystemConfiguration
->LpssPwm0Enabled
== 1) {
424 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00A0, 0x2003CD01);
425 } else if (SystemConfiguration
->LpssPwm0Enabled
== 0) {
426 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00A0, 0x2003CD00);
429 if (SystemConfiguration
->LpssPwm1Enabled
== 1) {
430 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00B0, 0x2003CC01);
431 } else if (SystemConfiguration
->LpssPwm1Enabled
== 0) {
432 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00B0, 0x2003CD00);
437 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
438 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
439 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
440 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
442 if (SystemConfiguration
->LpssHsuart0Enabled
== 1) {
443 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0020, 0x2003CC81); // uart1
444 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0010, 0x2003CC81);
445 if (SystemConfiguration
->LpssHsuart0FlowControlEnabled
== 0) {
446 DEBUG ((EFI_D_ERROR
, "LpssHsuart0FlowControlEnabled[0]\n"));
447 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0000, 0x2003CC80);
448 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0040, 0x2003CC80);
450 DEBUG ((EFI_D_ERROR
, "LpssHsuart0FlowControlEnabled[1]\n"));
451 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0000, 0x2003CC81);
452 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
454 } else if (SystemConfiguration
->LpssHsuart0Enabled
== 0) {
455 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0020, 0x2003CC80); // uart1
456 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0010, 0x2003CC80);
462 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
463 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
464 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
465 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
467 if (SystemConfiguration
->LpssHsuart1Enabled
== 1) {
468 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0060, 0x2003CC81);
469 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0070, 0x2003CC81);
471 if (SystemConfiguration
->LpssHsuart1FlowControlEnabled
== 0) {
472 DEBUG ((EFI_D_ERROR
, "LpssHsuart1FlowControlEnabled[0]\n"));
473 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0090, 0x2003CC80); // UART2_RTS_B
474 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0080, 0x2003CC80); // UART2_CTS_B
476 DEBUG ((EFI_D_ERROR
, "LpssHsuart1FlowControlEnabled[1]\n"));
477 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0090, 0x2003CC81); // uart2
478 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
480 } else if (SystemConfiguration
->LpssHsuart1Enabled
== 0) {
481 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0060, 0x2003CC80);
482 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0070, 0x2003CC80);
487 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
488 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
489 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
490 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
492 if (SystemConfiguration
->LpssSpiEnabled
== 1) {
493 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0110, 0x2003CC81); // SPI
494 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0100, 0x2003CD01);
495 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0130, 0x2003CC81);
496 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0120, 0x2003CC81);
497 } else if (SystemConfiguration
->LpssSpiEnabled
== 0) {
498 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0110, 0x2003cc80);
499 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0100, 0x2003cc80);
500 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0130, 0x2003cc80);
501 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0120, 0x2003cc80);
506 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
507 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
509 if (SystemConfiguration
->LpssI2C0Enabled
== 1) {
510 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0210, 0x2003C881);
511 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0200, 0x2003C881);
515 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
516 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
519 if (SystemConfiguration
->LpssI2C1Enabled
== 1) {
520 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01F0, 0x2003C881);
521 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01E0, 0x2003C881);
525 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
526 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
528 if (SystemConfiguration
->LpssI2C2Enabled
== 1) {
529 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01D0, 0x2003C881);
530 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01B0, 0x2003C881);
534 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
535 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
537 if (SystemConfiguration
->LpssI2C3Enabled
== 1) {
538 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0190, 0x2003C881);
539 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01C0, 0x2003C881);
543 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
544 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
546 if (SystemConfiguration
->LpssI2C4Enabled
== 1) {
547 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01A0, 0x2003C881);
548 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0170, 0x2003C881);
552 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
553 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
555 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
556 if (SystemConfiguration
->LpssI2C5Enabled
== 1) {
557 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0150, 0x2003C881);
558 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0140, 0x2003C881);
559 } else if(SystemConfiguration
->LpssI2C5Enabled
== 0) {
560 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0150, 0x2003C880);
561 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0140, 0x2003C880);
565 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
566 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
568 if (SystemConfiguration
->LpssI2C6Enabled
== 1) {
569 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0180, 0x2003C881);
570 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0160, 0x2003C881);
571 } else if (SystemConfiguration
->LpssI2C6Enabled
== 0) {
572 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0180, 0x2003C880);
573 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0160, 0x2003C880);
579 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
580 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
581 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
582 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
583 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
584 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
586 if (SystemConfiguration
->LpssSdioEnabled
== 1) {
587 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0320, 0x2003ED01);//SDIO
588 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0300, 0x2003EC81);
589 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0350, 0x2003EC81);
590 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02F0, 0x2003EC81);
591 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0340, 0x2003EC81);
592 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0310, 0x2003EC81);
597 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
598 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
599 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
600 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
601 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
602 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
603 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
604 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
605 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
606 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
608 if (SystemConfiguration
->LpssSdcardEnabled
== 1) {
609 if (!((PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD
&& PlatformInfo
->BoardRev
== PR11
) && (SystemConfiguration
->CfioPnpSettings
== 1))) {
610 MmioWrite32 (IO_BASE_ADDRESS
+ 0x05F0, 0x2003CD01);//SDCARD
611 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02B0, 0x2003CD01);
612 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02C0, 0x2003CC81);
613 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02E0, 0x2003CC81);
614 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0290, 0x2003CC81);
615 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02D0, 0x2003CC81);
616 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02A0, 0x2003CC81);
617 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0690, 0x2003CC81);
618 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
623 DEBUG ((EFI_D_ERROR
, "ConfigureLpssAndSccGpio------------end\n"));
629 IN SYSTEM_CONFIGURATION
*SystemConfiguration
632 DEBUG ((EFI_D_ERROR
, "ConfigureLpeGpio------------start\n"));
634 if (SystemConfiguration
->PchAzalia
== 0) {
635 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x220, (UINT32
)~(0x7), (UINT32
) (0x01));
636 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x250, (UINT32
)~(0x7), (UINT32
) (0x01));
637 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x240, (UINT32
)~(0x7), (UINT32
) (0x01));
638 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x260, (UINT32
)~(0x7), (UINT32
) (0x01));
639 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x270, (UINT32
)~(0x7), (UINT32
) (0x01));
640 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x230, (UINT32
)~(0x7), (UINT32
) (0x01));
641 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x280, (UINT32
)~(0x7), (UINT32
) (0x01));
642 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x540, (UINT32
)~(0x7), (UINT32
) (0x01));
645 DEBUG ((EFI_D_ERROR
, "ConfigureLpeGpio------------end\n"));
651 ConfigureSciSmiGpioRout (
652 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
)
656 GPI_Routing
= MmioRead32 (PMC_BASE_ADDRESS
+ R_PCH_PMC_GPI_ROUT
);
659 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
661 if(PlatformInfo
->BoardRev
== 3) {
662 GPI_Routing
= GPI_Routing
& 0xfffc3ffc;
663 GPI_Routing
= GPI_Routing
| 0x00024002;
667 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
670 GPI_Routing
= GPI_Routing
& 0x3fff3ffc;
671 GPI_Routing
= GPI_Routing
| 0x80004002;
673 MmioWrite32((PMC_BASE_ADDRESS
+ R_PCH_PMC_GPI_ROUT
), GPI_Routing
);
683 //Configure the platform clock for MIPI-CSI usage
686 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x6a0, (UINT32
)~(0x7), (UINT32
) (0x01));
691 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x570, (UINT32
)~(0x7), (UINT32
) (0x01));
696 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x5B0, (UINT32
)~(0x7), (UINT32
) (0x01));
709 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x338, (UINT32
)~(0x7), (UINT32
) (GPI
));
710 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x330, (UINT32
)~(0x187), (UINT32
) (0x101));
715 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x388, (UINT32
)~(0x7), (UINT32
) (GPI
));
716 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x380, (UINT32
)~(0x187), (UINT32
) (0x101));
721 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x368, (UINT32
)~(0x7), (UINT32
) (GPI
));
722 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x360, (UINT32
)~(0x187), (UINT32
) (0x101));
727 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x318, (UINT32
)~(0x7), (UINT32
) (GPI
));
728 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x310, (UINT32
)~(0x187), (UINT32
) (0x101));
733 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x378, (UINT32
)~(0x7), (UINT32
) (GPI
));
734 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x370, (UINT32
)~(0x187), (UINT32
) (0x101));
739 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x308, (UINT32
)~(0x7), (UINT32
) (GPI
));
740 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x300, (UINT32
)~(0x187), (UINT32
) (0x101));
745 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x398, (UINT32
)~(0x7), (UINT32
) (GPI
));
746 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x390, (UINT32
)~(0x187), (UINT32
) (0x101));
751 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x328, (UINT32
)~(0x7), (UINT32
) (GPI
));
752 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x320, (UINT32
)~(0x187), (UINT32
) (0x101));
757 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3a8, (UINT32
)~(0x7), (UINT32
) (GPI
));
758 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3a0, (UINT32
)~(0x187), (UINT32
) (0x101));
763 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x348, (UINT32
)~(0x7), (UINT32
) (GPI
));
764 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x340, (UINT32
)~(0x187), (UINT32
) (0x81));
769 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x358, (UINT32
)~(0x7), (UINT32
) (GPI
));
770 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x350, (UINT32
)~(0x187), (UINT32
) (0x101));
775 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3b8, (UINT32
)~(0x7), (UINT32
) (GPI
));
776 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3b0, (UINT32
)~(0x187), (UINT32
) (0x81));
781 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x288, (UINT32
)~(0x7), (UINT32
) (GPI
));
782 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x280, (UINT32
)~(0x187), (UINT32
) (0x101));
794 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x210, (UINT32
)~(0x0f000007), (UINT32
) (0x00));
795 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x1e0, (UINT32
)~(0x0f000007), (UINT32
) (0x00));
801 Platform specific initializations in stage1.
803 @param FfsHeader Pointer to the PEIM FFS file header.
804 @param PeiServices General purpose services available to every PEIM.
806 @retval EFI_SUCCESS Operation completed successfully.
807 @retval Otherwise Platform initialization failed.
811 PlatformEarlyInitEntry (
813 IN EFI_PEI_FILE_HANDLE FileHandle
,
814 IN CONST EFI_PEI_SERVICES
**PeiServices
818 SYSTEM_CONFIGURATION SystemConfiguration
;
819 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
820 EFI_PEI_HOB_POINTERS Hob
;
821 EFI_PLATFORM_CPU_INFO PlatformCpuInfo
;
824 // Initialize SmbusPolicy PPI
826 Status
= (*PeiServices
)->InstallPpi(PeiServices
, &mInstallSmbusPolicyPpi
);
827 ASSERT_EFI_ERROR (Status
);
830 // Initialize Stall PPIs
832 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mInstallStallPpi
);
833 ASSERT_EFI_ERROR (Status
);
836 // Initialize platform PPIs
838 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mInstallSpeakerInterfacePpi
);
839 ASSERT_EFI_ERROR (Status
);
842 // Variable initialization
844 ZeroMem(&PlatformCpuInfo
, sizeof(EFI_PLATFORM_CPU_INFO
));
847 // Set the some PCI and chipset range as UC
848 // And align to 1M at leaset
850 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
851 ASSERT (Hob
.Raw
!= NULL
);
852 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
855 // Initialize PlatformInfo HOB
857 MultiPlatformInfoInit(PeiServices
, PlatformInfo
);
862 MchInit (PeiServices
);
865 // Set the new boot mode
867 Status
= UpdateBootMode (PeiServices
, PlatformInfo
);
868 ASSERT_EFI_ERROR (Status
);
870 SetPlatformBootMode (PeiServices
, PlatformInfo
);
873 // Get setup variable. This can only be done after BootMode is updated
875 GetSetupVariable (PeiServices
, &SystemConfiguration
);
877 CheckOsSelection(PeiServices
, &SystemConfiguration
);
880 // Update PlatformInfo HOB according to setup variable
882 PlatformInfoUpdate(PeiServices
, PlatformInfo
, &SystemConfiguration
);
884 InitializePlatform (PeiServices
, PlatformInfo
, &SystemConfiguration
);
887 // Initialize VlvPolicy PPI
889 Status
= VlvPolicyInit (PeiServices
, &SystemConfiguration
);
890 ASSERT_EFI_ERROR (Status
);
893 // Soc specific GPIO setting
895 ConfigureSoCGpio(&SystemConfiguration
);
898 // Baylake Board specific.
900 if (PlatformInfo
->BoardId
== BOARD_ID_BL_RVP
||
901 PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD
||
902 PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD8
||
903 PlatformInfo
->BoardId
== BOARD_ID_BL_RVP_DDR3L
||
904 PlatformInfo
->BoardId
== BOARD_ID_BL_STHI
||
905 PlatformInfo
->BoardId
== BOARD_ID_BB_RVP
||
906 PlatformInfo
->BoardId
== BOARD_ID_BS_RVP
||
907 PlatformInfo
->BoardId
== BOARD_ID_MINNOW2
||
908 PlatformInfo
->BoardId
== BOARD_ID_MINNOW2_TURBOT
||
909 PlatformInfo
->BoardId
== BOARD_ID_CVH
) {
910 ConfigureLpssAndSccGpio(&SystemConfiguration
, PlatformInfo
);
917 // Alpine Valley and Bayley Bay board specific
919 ConfigureLpeGpio(&SystemConfiguration
);
922 // Bayley Bay Board specific.
924 ConfigureSciSmiGpioRout(PlatformInfo
);
925 if (SystemConfiguration
.LpssI2C3Enabled
== 1) {
933 Status
= PlatformCpuInit (PeiServices
, &SystemConfiguration
, &PlatformCpuInfo
);
936 // Perform basic SSA related platform initialization
938 PlatformSsaInit (&SystemConfiguration
,PeiServices
);
944 Status
= PlatformPchInit (&SystemConfiguration
, PeiServices
, PlatformInfo
->PlatformType
);
945 ASSERT_EFI_ERROR (Status
);
948 // Initialize platform PPIs
950 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mPpiList
[0]);
951 ASSERT_EFI_ERROR (Status
);
953 if (PlatformInfo
->BoardId
!= BOARD_ID_CVH
) {
954 InstallPlatformClocksNotify (PeiServices
);
955 InstallPlatformSysCtrlGPIONotify(PeiServices
);
959 // Initialize platform PPIs
961 Status
= (*PeiServices
)->NotifyPpi(PeiServices
, &mNotifyList
[0]);
962 ASSERT_EFI_ERROR (Status
);
965 // Initialize Measured Boot
967 Status
= MeasuredBootInit (PeiServices
, &SystemConfiguration
);
968 ASSERT_EFI_ERROR (Status
);
975 Return the mainblockcompact Fv.
977 @param FvNumber Our enumeration of the firmware volumes we care about.
979 @param FvAddress Base Address of the memory containing the firmware volume
982 @retval EFI_NOT_FOUND
988 IN EFI_PEI_FIND_FV_PPI
*This
,
989 IN CONST EFI_PEI_SERVICES
**PeiServices
,
990 IN OUT UINT8
*FvNumber
,
991 OUT EFI_FIRMWARE_VOLUME_HEADER
**FVAddress
995 // At present, we only have one Fv to search
997 if (*FvNumber
== 0) {
999 *FVAddress
= (EFI_FIRMWARE_VOLUME_HEADER
*)(UINTN
)FixedPcdGet32 (PcdFlashFvMainBase
);
1002 else if (*FvNumber
== 1) {
1004 *FVAddress
= (EFI_FIRMWARE_VOLUME_HEADER
*)(UINTN
)FixedPcdGet32 (PcdFlashFvRecovery2Base
);
1007 else { // Not the one Fv we care about
1008 return EFI_NOT_FOUND
;
1015 IN CONST EFI_PEI_SERVICES
**PeiServices
1018 // MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
1037 // If we get here we need to mark it as a failure.
1039 return EFI_UNSUPPORTED
;
1044 #pragma GCC pop_options
1046 #pragma optimize ("", on)