3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 SMM S3 handler Driver implementation file
26 #include "SmmPlatform.h"
28 extern UINT16 mAcpiBaseAddr
;
29 EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase
;
32 InitRuntimeScriptTable (
33 IN EFI_SYSTEM_TABLE
*SystemTable
39 ACPI_VARIABLE_SET_COMPATIBILITY
*AcpiVariableBase
;
42 // Allocate runtime ACPI script table space. We need it to save some
43 // settings done by CSM, which runs after normal script table closed
45 Status
= gBS
->AllocatePages (
49 &mRuntimeScriptTableBase
51 if (EFI_ERROR(Status
)) {
52 return EFI_OUT_OF_RESOURCES
;
56 // Save runtime script table base into global ACPI variable
58 VarAttrib
= EFI_VARIABLE_BOOTSERVICE_ACCESS
| EFI_VARIABLE_RUNTIME_ACCESS
59 | EFI_VARIABLE_NON_VOLATILE
;
60 VarSize
= sizeof (UINTN
);
61 Status
= SystemTable
->RuntimeServices
->GetVariable (
63 &gEfiAcpiVariableCompatiblityGuid
,
68 if (EFI_ERROR(Status
)) {
72 AcpiVariableBase
->RuntimeScriptTableBase
= mRuntimeScriptTableBase
;
78 SaveRuntimeScriptTable (
82 SMM_PCI_IO_ADDRESS PciAddress
;
92 //Bus , Dev, Func, DMI
97 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
99 0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,
102 //Bus , Dev, Func, LPC device
107 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
109 0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,
112 //Bus , Dev, Func, PCIE device
117 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
119 0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
122 //Bus , Dev, Func, PCIE device
127 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
129 0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
132 //Bus , Dev, Func, SATA device
137 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
139 0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,
142 //Bus , Dev, Func, EHCI device
147 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
149 0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
152 //Bus , Dev, Func, SMBUS device
157 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
159 0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
162 //Bus , Dev, Func, SMBUS device
167 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
169 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
172 //Bus , Dev, Func, VGA bus1
177 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
179 0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,
182 //Bus , Dev, Func, VGA bus1
187 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
189 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 //Bus , Dev, Func, VGA bus1 function 1
197 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
199 0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
202 //Bus , Dev, Func, VGA bus1 function 1
207 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
209 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
212 //Bus , Dev, Func, IGD bus0 function 0
217 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
219 0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
222 //Bus , Dev, Func, USB bus0 function 0
227 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
229 0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
232 //Bus , Dev, Func, HD Audio bus0 function 0
237 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
239 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
242 //0xFF indicates the end of the table
248 // These registers have to set in byte order
250 UINT8 ExtReg
[] = { 0x9E, 0x9D }; // SMRAM settings
255 // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
256 // and vital to S3 resume. That's why we put save code here
259 PciAddress
.Device
= 0;
260 PciAddress
.Function
= 0;
261 PciAddress
.ExtendedRegister
= 0;
263 for (Index
= 0; Index
< 2; Index
++) {
265 // Read SRAM setting from Pci(0, 0, 0)
267 PciAddress
.Register
= ExtReg
[Index
];
278 // Save latest settings to runtime script table
280 S3BootScriptSavePciCfgWrite(
281 S3BootScriptWidthUint8
,
282 *(UINT64
*)&PciAddress
,
290 // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
291 // and vital to S3 resume. That's why we put save code here
294 while (RegTable
[Index
] != 0xFF) {
296 PciAddress
.Bus
= RegTable
[Index
++];
297 PciAddress
.Device
= RegTable
[Index
++];
298 PciAddress
.Function
= RegTable
[Index
++];
299 PciAddress
.Register
= 0;
300 PciAddress
.ExtendedRegister
= 0;
302 Data16
= MmioRead16 (
311 if (Data16
== 0xFFFF) {
316 for (Offset
= 0, Mask
= 0x01; Offset
< 256; Offset
+=4, Mask
<<=1) {
322 if (RegTable
[Index
+ Offset
/32] & Mask
) {
324 PciAddress
.Register
= (UINT8
)Offset
;
325 Data32
= MmioRead32 (MmPciAddress (0, PciAddress
.Bus
, PciAddress
.Device
, PciAddress
.Function
, PciAddress
.Register
));
328 // Save latest settings to runtime script table
330 S3BootScriptSavePciCfgWrite (
331 S3BootScriptWidthUint32
,
332 *(UINT64
*)&PciAddress
,
345 // Save I/O ports to S3 script table
352 S3BootScriptSaveIoWrite (
353 S3BootScriptWidthUint8
,
359 Data32
= IoRead32(mAcpiBaseAddr
+ R_PCH_SMI_EN
);
361 S3BootScriptSaveIoWrite (
362 S3BootScriptWidthUint32
,
363 (mAcpiBaseAddr
+ R_PCH_SMI_EN
),
369 // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.
371 Data16
= IoRead16(mAcpiBaseAddr
+ R_PCH_TCO_CNT
);
373 S3BootScriptSaveIoWrite (
374 S3BootScriptWidthUint16
,
375 mAcpiBaseAddr
+ R_PCH_TCO_CNT
,