4 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
6 SPDX-License-Identifier: BSD-2-Clause-Patent
17 This is the driver that initializes the Intel ValleyView.
21 #include "VlvPlatformInit.h"
22 #include <Protocol/VlvPlatformPolicy.h>
24 extern DXE_VLV_PLATFORM_POLICY_PROTOCOL
*DxePlatformSaPolicy
;
27 DXE_VLV_PLATFORM_POLICY_PROTOCOL
*DxePlatformSaPolicy
;
30 "Poll Status" for GT Readiness
32 @param Base Base address of MMIO
33 @param Offset MMIO Offset
35 @param Result Value to wait for
53 GtStatus
= MmioRead32 ((UINTN
)Base
+ Offset
);
55 while (((GtStatus
& Mask
) != Result
)) {
57 GtStatus
= MmioRead32 ((UINTN
)Base
+ Offset
);
63 Do Post GT PM Init Steps after VBIOS Initialization.
65 @param Event A pointer to the Event that triggered the callback.
66 @param Context A pointer to private data registered with the callback function.
68 @retval EFI_SUCCESS GC_TODO
79 UINT64 OriginalGTTMMADR
;
80 UINT32 LoGTBaseAddress
;
81 UINT32 HiGTBaseAddress
;
84 // Enable Bus Master, I/O and Memory access on 0:2:0
86 PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_CMD
), (BIT2
| BIT1
));
89 // only 32bit read/write is legal for device 0:2:0
91 OriginalGTTMMADR
= (UINT64
) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_GTTMMADR
));
92 OriginalGTTMMADR
= LShiftU64 ((UINT64
) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_GTTMMADR
+ 4)), 32) | (OriginalGTTMMADR
);
95 // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase
96 // Program temporarily 32bits GTTMMADR for POST and S3 resume
98 LoGTBaseAddress
= (UINT32
) (GTTMMADR
& 0xFFFFFFFF);
99 HiGTBaseAddress
= (UINT32
) RShiftU64 ((GTTMMADR
& 0xFFFFFFFF00000000), 32);
100 S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_GTTMMADR
), LoGTBaseAddress
);
101 S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_GTTMMADR
+4), HiGTBaseAddress
);
106 // Restore original GTTMMADR
108 LoGTBaseAddress
= (UINT32
) (OriginalGTTMMADR
& 0xFFFFFFFF);
109 HiGTBaseAddress
= (UINT32
) RShiftU64 ((OriginalGTTMMADR
& 0xFFFFFFFF00000000), 32);
111 S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_GTTMMADR
), LoGTBaseAddress
);
112 S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_GTTMMADR
+4), HiGTBaseAddress
);
116 // Lock the following registers, GGC, BDSM, BGSM
118 PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_MGGC_OFFSET
), LockBit
);
119 PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_BSM_OFFSET
), LockBit
);
120 PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0,IGD_R_BGSM
), LockBit
);
122 gBS
->CloseEvent (Event
);
125 // Return final status
134 Initialize GT Post Routines.
136 @param ImageHandle Handle for the image of this driver
137 @param DxePlatformSaPolicy SA DxePlatformPolicy protocol
139 @retval EFI_SUCCESS GT POST initialization complete
144 IN EFI_HANDLE ImageHandle
,
145 IN DXE_VLV_PLATFORM_POLICY_PROTOCOL
*DxePlatformSaPolicyParam
149 EFI_EVENT mConOutEvent
;
150 VOID
*gConOutNotifyReg
;
154 EFI_PHYSICAL_ADDRESS MemBaseAddress
;
155 UINT32 LoGTBaseAddress
;
156 UINT32 HiGTBaseAddress
;
159 Status
= EFI_SUCCESS
;
162 // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,
164 if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV
, 0, IGD_R_VID
)) != 0xFFFF) {
169 // Enable Bus Master, I/O and Memory access on 0:2:0
171 PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV
, 0, IGD_R_CMD
), (BIT2
| BIT1
| BIT0
));
174 // Means Allocate 4MB for GTTMADDR
176 MemBaseAddress
= 0x0ffffffff;
178 Status
= gDS
->AllocateMemorySpace (
179 EfiGcdAllocateMaxAddressSearchBottomUp
,
180 EfiGcdMemoryTypeMemoryMappedIo
,
187 ASSERT_EFI_ERROR (Status
);
190 // Program GT PM Settings if GTTMMADR allocation is Successful
192 GTTMMADR
= (UINTN
) MemBaseAddress
;
194 LoGTBaseAddress
= (UINT32
) (MemBaseAddress
& 0xFFFFFFFF);
195 HiGTBaseAddress
= (UINT32
) RShiftU64 ((MemBaseAddress
& 0xFFFFFFFF00000000), 32);
197 PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0, IGD_R_GTTMMADR
), LoGTBaseAddress
);
198 PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV
, 0, IGD_R_GTTMMADR
+4), HiGTBaseAddress
);
201 S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV
, 0, IGD_R_GTTMMADR
));
204 S3MmioRead32(IGD_R_GTTMMADR
+ 4);
207 S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV
, 0, IGD_R_CMD
));
210 // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack
212 Status
= gBS
->CreateEvent (
215 (EFI_EVENT_NOTIFY
)PostPmInitCallBack
,
220 ASSERT_EFI_ERROR (Status
);
221 if (EFI_ERROR (Status
)) {
226 Status
= gBS
->RegisterProtocolNotify (
227 &gEfiGraphicsOutputProtocolGuid
,
234 MmioWrite64 (IGD_R_GTTMMADR
, 0);
237 // Free allocated resources
239 gDS
->FreeMemorySpace (
251 This is the standard EFI driver point that detects
252 whether there is an ICH southbridge in the system
253 and if so, initializes the chip.
255 @param ImageHandle Handle for the image of this driver
256 @param SystemTable Pointer to the EFI System Table
258 @retval EFI_SUCCESS The function completed successfully
263 VlvPlatformInitEntryPoint (
264 IN EFI_HANDLE ImageHandle
,
265 IN EFI_SYSTEM_TABLE
*SystemTable
270 Status
= gBS
->LocateProtocol (&gDxeVlvPlatformPolicyGuid
, NULL
, (void **)&DxePlatformSaPolicy
);
271 ASSERT_EFI_ERROR (Status
);
274 // GtPostInit Initialization
276 DEBUG ((EFI_D_ERROR
, "Initializing GT PowerManagement and other GT POST related\n"));
277 IgdPmHook (ImageHandle
, DxePlatformSaPolicy
);
280 // IgdOpRegion Install Initialization
282 DEBUG ((EFI_D_ERROR
, "Initializing IGD OpRegion\n"));