arch/arm/boot/dts/exynos5420-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5420 and Exynos5800
   8  * boards: CPU[0123] being the A15.
   9  *
  10  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  11  * but particular boards choose different booting order.
  12  *
  13  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  14  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  15  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  16  * from the LITTLE: Cortex-A7.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 / {
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a15";
  31                         reg = <0x0>;
  32                         clocks = <&clock CLK_ARM_CLK>;
  33                         clock-frequency = <1800000000>;
  34                         cci-control-port = <&cci_control1>;
  35                         operating-points-v2 = <&cluster_a15_opp_table>;
  36                         #cooling-cells = <2>; /* min followed by max */
  37                         capacity-dmips-mhz = <1024>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x1>;
  44                         clock-frequency = <1800000000>;
  45                         cci-control-port = <&cci_control1>;
  46                         operating-points-v2 = <&cluster_a15_opp_table>;
  47                         #cooling-cells = <2>; /* min followed by max */
  48                         capacity-dmips-mhz = <1024>;
  49                 };
  50
  51                 cpu2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0x2>;
  55                         clock-frequency = <1800000000>;
  56                         cci-control-port = <&cci_control1>;
  57                         operating-points-v2 = <&cluster_a15_opp_table>;
  58                         #cooling-cells = <2>; /* min followed by max */
  59                         capacity-dmips-mhz = <1024>;
  60                 };
  61
  62                 cpu3: cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x3>;
  66                         clock-frequency = <1800000000>;
  67                         cci-control-port = <&cci_control1>;
  68                         operating-points-v2 = <&cluster_a15_opp_table>;
  69                         #cooling-cells = <2>; /* min followed by max */
  70                         capacity-dmips-mhz = <1024>;
  71                 };
  72
  73                 cpu4: cpu@100 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a7";
  76                         reg = <0x100>;
  77                         clocks = <&clock CLK_KFC_CLK>;
  78                         clock-frequency = <1000000000>;
  79                         cci-control-port = <&cci_control0>;
  80                         operating-points-v2 = <&cluster_a7_opp_table>;
  81                         #cooling-cells = <2>; /* min followed by max */
  82                         capacity-dmips-mhz = <539>;
  83                 };
  84
  85                 cpu5: cpu@101 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0x101>;
  89                         clock-frequency = <1000000000>;
  90                         cci-control-port = <&cci_control0>;
  91                         operating-points-v2 = <&cluster_a7_opp_table>;
  92                         #cooling-cells = <2>; /* min followed by max */
  93                         capacity-dmips-mhz = <539>;
  94                 };
  95
  96                 cpu6: cpu@102 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a7";
  99                         reg = <0x102>;
 100                         clock-frequency = <1000000000>;
 101                         cci-control-port = <&cci_control0>;
 102                         operating-points-v2 = <&cluster_a7_opp_table>;
 103                         #cooling-cells = <2>; /* min followed by max */
 104                         capacity-dmips-mhz = <539>;
 105                 };
 106
 107                 cpu7: cpu@103 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a7";
 110                         reg = <0x103>;
 111                         clock-frequency = <1000000000>;
 112                         cci-control-port = <&cci_control0>;
 113                         operating-points-v2 = <&cluster_a7_opp_table>;
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         capacity-dmips-mhz = <539>;
 116                 };
 117         };
 118 };