2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3328-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3328";
55 interrupt-parent = <&gic>;
68 ethernet1 = &gmac2phy;
77 compatible = "arm,cortex-a53", "arm,armv8";
79 clocks = <&cru ARMCLK>;
81 dynamic-power-coefficient = <120>;
82 enable-method = "psci";
83 next-level-cache = <&l2>;
84 operating-points-v2 = <&cpu0_opp_table>;
89 compatible = "arm,cortex-a53", "arm,armv8";
91 clocks = <&cru ARMCLK>;
92 dynamic-power-coefficient = <120>;
93 enable-method = "psci";
94 next-level-cache = <&l2>;
95 operating-points-v2 = <&cpu0_opp_table>;
100 compatible = "arm,cortex-a53", "arm,armv8";
102 clocks = <&cru ARMCLK>;
103 dynamic-power-coefficient = <120>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 operating-points-v2 = <&cpu0_opp_table>;
111 compatible = "arm,cortex-a53", "arm,armv8";
113 clocks = <&cru ARMCLK>;
114 dynamic-power-coefficient = <120>;
115 enable-method = "psci";
116 next-level-cache = <&l2>;
117 operating-points-v2 = <&cpu0_opp_table>;
121 compatible = "cache";
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
130 opp-hz = /bits/ 64 <408000000>;
131 opp-microvolt = <950000>;
132 clock-latency-ns = <40000>;
136 opp-hz = /bits/ 64 <600000000>;
137 opp-microvolt = <950000>;
138 clock-latency-ns = <40000>;
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
143 clock-latency-ns = <40000>;
146 opp-hz = /bits/ 64 <1008000000>;
147 opp-microvolt = <1100000>;
148 clock-latency-ns = <40000>;
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1225000>;
153 clock-latency-ns = <40000>;
156 opp-hz = /bits/ 64 <1296000000>;
157 opp-microvolt = <1300000>;
158 clock-latency-ns = <40000>;
163 compatible = "simple-bus";
164 #address-cells = <2>;
168 dmac: dmac@ff1f0000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x0 0xff1f0000 0x0 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru ACLK_DMAC>;
174 clock-names = "apb_pclk";
180 compatible = "arm,cortex-a53-pmu";
181 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
189 compatible = "arm,psci-1.0", "arm,psci-0.2";
194 compatible = "arm,armv8-timer";
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
202 compatible = "fixed-clock";
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
209 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
210 reg = <0x0 0xff000000 0x0 0x1000>;
211 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
213 clock-names = "i2s_clk", "i2s_hclk";
214 dmas = <&dmac 11>, <&dmac 12>;
215 dma-names = "tx", "rx";
220 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
221 reg = <0x0 0xff010000 0x0 0x1000>;
222 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
224 clock-names = "i2s_clk", "i2s_hclk";
225 dmas = <&dmac 14>, <&dmac 15>;
226 dma-names = "tx", "rx";
231 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
232 reg = <0x0 0xff020000 0x0 0x1000>;
233 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
235 clock-names = "i2s_clk", "i2s_hclk";
236 dmas = <&dmac 0>, <&dmac 1>;
237 dma-names = "tx", "rx";
241 spdif: spdif@ff030000 {
242 compatible = "rockchip,rk3328-spdif";
243 reg = <0x0 0xff030000 0x0 0x1000>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
246 clock-names = "mclk", "hclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&spdifm2_tx>;
255 compatible = "rockchip,pdm";
256 reg = <0x0 0xff040000 0x0 0x1000>;
257 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
258 clock-names = "pdm_clk", "pdm_hclk";
261 pinctrl-names = "default", "sleep";
262 pinctrl-0 = <&pdmm0_clk
267 pinctrl-1 = <&pdmm0_clk_sleep
275 grf: syscon@ff100000 {
276 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
277 reg = <0x0 0xff100000 0x0 0x1000>;
278 #address-cells = <1>;
281 io_domains: io-domains {
282 compatible = "rockchip,rk3328-io-voltage-domain";
286 power: power-controller {
287 compatible = "rockchip,rk3328-power-controller";
288 #power-domain-cells = <1>;
289 #address-cells = <1>;
292 pd_hevc@RK3328_PD_HEVC {
293 reg = <RK3328_PD_HEVC>;
295 pd_video@RK3328_PD_VIDEO {
296 reg = <RK3328_PD_VIDEO>;
298 pd_vpu@RK3328_PD_VPU {
299 reg = <RK3328_PD_VPU>;
304 compatible = "syscon-reboot-mode";
306 mode-normal = <BOOT_NORMAL>;
307 mode-recovery = <BOOT_RECOVERY>;
308 mode-bootloader = <BOOT_FASTBOOT>;
309 mode-loader = <BOOT_BL_DOWNLOAD>;
314 uart0: serial@ff110000 {
315 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff110000 0x0 0x100>;
317 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 2>, <&dmac 3>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
329 uart1: serial@ff120000 {
330 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
331 reg = <0x0 0xff120000 0x0 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
334 clock-names = "sclk_uart", "pclk_uart";
335 dmas = <&dmac 4>, <&dmac 5>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
344 uart2: serial@ff130000 {
345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
346 reg = <0x0 0xff130000 0x0 0x100>;
347 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 dmas = <&dmac 6>, <&dmac 7>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart2m1_xfer>;
360 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
361 reg = <0x0 0xff150000 0x0 0x1000>;
362 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
365 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
366 clock-names = "i2c", "pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c0_xfer>;
373 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
374 reg = <0x0 0xff160000 0x0 0x1000>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
378 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c1_xfer>;
386 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
387 reg = <0x0 0xff170000 0x0 0x1000>;
388 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
391 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
392 clock-names = "i2c", "pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c2_xfer>;
399 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
400 reg = <0x0 0xff180000 0x0 0x1000>;
401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
404 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
405 clock-names = "i2c", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c3_xfer>;
412 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
413 reg = <0x0 0xff190000 0x0 0x1000>;
414 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
417 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
418 clock-names = "spiclk", "apb_pclk";
419 dmas = <&dmac 8>, <&dmac 9>;
420 dma-names = "tx", "rx";
421 pinctrl-names = "default";
422 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
426 wdt: watchdog@ff1a0000 {
427 compatible = "snps,dw-wdt";
428 reg = <0x0 0xff1a0000 0x0 0x100>;
429 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
433 compatible = "rockchip,rk3328-pwm";
434 reg = <0x0 0xff1b0000 0x0 0x10>;
435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
436 clock-names = "pwm", "pclk";
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm0_pin>;
444 compatible = "rockchip,rk3328-pwm";
445 reg = <0x0 0xff1b0010 0x0 0x10>;
446 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
447 clock-names = "pwm", "pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm1_pin>;
455 compatible = "rockchip,rk3328-pwm";
456 reg = <0x0 0xff1b0020 0x0 0x10>;
457 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
458 clock-names = "pwm", "pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>;
466 compatible = "rockchip,rk3328-pwm";
467 reg = <0x0 0xff1b0030 0x0 0x10>;
468 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwmir_pin>;
478 soc_thermal: soc-thermal {
479 polling-delay-passive = <20>;
480 polling-delay = <1000>;
481 sustainable-power = <1000>;
483 thermal-sensors = <&tsadc 0>;
486 threshold: trip-point0 {
487 temperature = <70000>;
491 target: trip-point1 {
492 temperature = <85000>;
497 temperature = <95000>;
506 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 contribution = <4096>;
514 tsadc: tsadc@ff250000 {
515 compatible = "rockchip,rk3328-tsadc";
516 reg = <0x0 0xff250000 0x0 0x100>;
517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
518 assigned-clocks = <&cru SCLK_TSADC>;
519 assigned-clock-rates = <50000>;
520 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
521 clock-names = "tsadc", "apb_pclk";
522 pinctrl-names = "init", "default", "sleep";
523 pinctrl-0 = <&otp_gpio>;
524 pinctrl-1 = <&otp_out>;
525 pinctrl-2 = <&otp_gpio>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 rockchip,grf = <&grf>;
529 rockchip,hw-tshut-temp = <100000>;
530 #thermal-sensor-cells = <1>;
534 saradc: adc@ff280000 {
535 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
536 reg = <0x0 0xff280000 0x0 0x100>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538 #io-channel-cells = <1>;
539 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
540 clock-names = "saradc", "apb_pclk";
541 resets = <&cru SRST_SARADC_P>;
542 reset-names = "saradc-apb";
546 h265e_mmu: iommu@ff330200 {
547 compatible = "rockchip,iommu";
548 reg = <0x0 0xff330200 0 0x100>;
549 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "h265e_mmu";
555 vepu_mmu: iommu@ff340800 {
556 compatible = "rockchip,iommu";
557 reg = <0x0 0xff340800 0x0 0x40>;
558 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-names = "vepu_mmu";
564 vpu_mmu: iommu@ff350800 {
565 compatible = "rockchip,iommu";
566 reg = <0x0 0xff350800 0x0 0x40>;
567 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-names = "vpu_mmu";
573 rkvdec_mmu: iommu@ff360480 {
574 compatible = "rockchip,iommu";
575 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
576 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "rkvdec_mmu";
582 vop_mmu: iommu@ff373f00 {
583 compatible = "rockchip,iommu";
584 reg = <0x0 0xff373f00 0x0 0x100>;
585 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-names = "vop_mmu";
591 cru: clock-controller@ff440000 {
592 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
593 reg = <0x0 0xff440000 0x0 0x1000>;
594 rockchip,grf = <&grf>;
599 * CPLL should run at 1200, but that is to high for
600 * the initial dividers of most of its children.
601 * We need set cpll child clk div first,
602 * and then set the cpll frequency.
604 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
605 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
606 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
607 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
608 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
609 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
610 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
611 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
612 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
613 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
614 <&cru SCLK_WIFI>, <&cru ARMCLK>,
615 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
616 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
617 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
618 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
620 assigned-clock-parents =
621 <&cru HDMIPHY>, <&cru PLL_APLL>,
622 <&cru PLL_GPLL>, <&xin24m>,
623 <&xin24m>, <&xin24m>;
624 assigned-clock-rates =
627 <24000000>, <24000000>,
628 <15000000>, <15000000>,
629 <100000000>, <100000000>,
630 <100000000>, <100000000>,
631 <50000000>, <100000000>,
632 <100000000>, <100000000>,
633 <50000000>, <50000000>,
634 <50000000>, <50000000>,
635 <24000000>, <600000000>,
636 <491520000>, <1200000000>,
637 <150000000>, <75000000>,
638 <75000000>, <150000000>,
639 <75000000>, <75000000>,
643 usb2phy_grf: syscon@ff450000 {
644 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
646 reg = <0x0 0xff450000 0x0 0x10000>;
647 #address-cells = <1>;
650 u2phy: usb2-phy@100 {
651 compatible = "rockchip,rk3328-usb2phy";
654 clock-names = "phyclk";
655 clock-output-names = "usb480m_phy";
657 assigned-clocks = <&cru USB480M>;
658 assigned-clock-parents = <&u2phy>;
661 u2phy_otg: otg-port {
663 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666 interrupt-names = "otg-bvalid", "otg-id",
671 u2phy_host: host-port {
673 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "linestate";
680 sdmmc: dwmmc@ff500000 {
681 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
682 reg = <0x0 0xff500000 0x0 0x4000>;
683 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
685 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
686 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
687 fifo-depth = <0x100>;
691 sdio: dwmmc@ff510000 {
692 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
693 reg = <0x0 0xff510000 0x0 0x4000>;
694 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
696 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
697 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
698 fifo-depth = <0x100>;
702 emmc: dwmmc@ff520000 {
703 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
704 reg = <0x0 0xff520000 0x0 0x4000>;
705 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
707 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
708 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
709 fifo-depth = <0x100>;
713 gmac2io: ethernet@ff540000 {
714 compatible = "rockchip,rk3328-gmac";
715 reg = <0x0 0xff540000 0x0 0x10000>;
716 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
717 interrupt-names = "macirq";
718 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
719 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
720 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
722 clock-names = "stmmaceth", "mac_clk_rx",
723 "mac_clk_tx", "clk_mac_ref",
724 "clk_mac_refout", "aclk_mac",
726 resets = <&cru SRST_GMAC2IO_A>;
727 reset-names = "stmmaceth";
728 rockchip,grf = <&grf>;
732 gmac2phy: ethernet@ff550000 {
733 compatible = "rockchip,rk3328-gmac";
734 reg = <0x0 0xff550000 0x0 0x10000>;
735 rockchip,grf = <&grf>;
736 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
737 interrupt-names = "macirq";
738 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
739 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
740 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
741 <&cru SCLK_MAC2PHY_OUT>;
742 clock-names = "stmmaceth", "mac_clk_rx",
743 "mac_clk_tx", "clk_mac_ref",
744 "aclk_mac", "pclk_mac",
746 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
747 reset-names = "stmmaceth", "mac-phy";
753 compatible = "snps,dwmac-mdio";
754 #address-cells = <1>;
758 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
760 clocks = <&cru SCLK_MAC2PHY_OUT>;
761 resets = <&cru SRST_MACPHY>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
769 usb20_otg: usb@ff580000 {
770 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
772 reg = <0x0 0xff580000 0x0 0x40000>;
773 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cru HCLK_OTG>;
777 g-np-tx-fifo-size = <16>;
778 g-rx-fifo-size = <280>;
779 g-tx-fifo-size = <256 128 128 64 32 16>;
782 phy-names = "usb2-phy";
786 usb_host0_ehci: usb@ff5c0000 {
787 compatible = "generic-ehci";
788 reg = <0x0 0xff5c0000 0x0 0x10000>;
789 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru HCLK_HOST0>, <&u2phy>;
791 clock-names = "usbhost", "utmi";
792 phys = <&u2phy_host>;
797 usb_host0_ohci: usb@ff5d0000 {
798 compatible = "generic-ohci";
799 reg = <0x0 0xff5d0000 0x0 0x10000>;
800 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cru HCLK_HOST0>, <&u2phy>;
802 clock-names = "usbhost", "utmi";
803 phys = <&u2phy_host>;
808 gic: interrupt-controller@ff811000 {
809 compatible = "arm,gic-400";
810 #interrupt-cells = <3>;
811 #address-cells = <0>;
812 interrupt-controller;
813 reg = <0x0 0xff811000 0 0x1000>,
814 <0x0 0xff812000 0 0x2000>,
815 <0x0 0xff814000 0 0x2000>,
816 <0x0 0xff816000 0 0x2000>;
817 interrupts = <GIC_PPI 9
818 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
822 compatible = "rockchip,rk3328-pinctrl";
823 rockchip,grf = <&grf>;
824 #address-cells = <2>;
828 gpio0: gpio0@ff210000 {
829 compatible = "rockchip,gpio-bank";
830 reg = <0x0 0xff210000 0x0 0x100>;
831 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cru PCLK_GPIO0>;
837 interrupt-controller;
838 #interrupt-cells = <2>;
841 gpio1: gpio1@ff220000 {
842 compatible = "rockchip,gpio-bank";
843 reg = <0x0 0xff220000 0x0 0x100>;
844 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru PCLK_GPIO1>;
850 interrupt-controller;
851 #interrupt-cells = <2>;
854 gpio2: gpio2@ff230000 {
855 compatible = "rockchip,gpio-bank";
856 reg = <0x0 0xff230000 0x0 0x100>;
857 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cru PCLK_GPIO2>;
863 interrupt-controller;
864 #interrupt-cells = <2>;
867 gpio3: gpio3@ff240000 {
868 compatible = "rockchip,gpio-bank";
869 reg = <0x0 0xff240000 0x0 0x100>;
870 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru PCLK_GPIO3>;
876 interrupt-controller;
877 #interrupt-cells = <2>;
880 pcfg_pull_up: pcfg-pull-up {
884 pcfg_pull_down: pcfg-pull-down {
888 pcfg_pull_none: pcfg-pull-none {
892 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
894 drive-strength = <2>;
897 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
899 drive-strength = <2>;
902 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
904 drive-strength = <4>;
907 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
909 drive-strength = <4>;
912 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
914 drive-strength = <4>;
917 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
919 drive-strength = <8>;
922 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
924 drive-strength = <8>;
927 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
929 drive-strength = <12>;
932 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
934 drive-strength = <12>;
937 pcfg_output_high: pcfg-output-high {
941 pcfg_output_low: pcfg-output-low {
945 pcfg_input_high: pcfg-input-high {
950 pcfg_input: pcfg-input {
955 i2c0_xfer: i2c0-xfer {
956 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
957 <2 RK_PD1 1 &pcfg_pull_none>;
962 i2c1_xfer: i2c1-xfer {
963 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
964 <2 RK_PA5 2 &pcfg_pull_none>;
969 i2c2_xfer: i2c2-xfer {
970 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
971 <2 RK_PB6 1 &pcfg_pull_none>;
976 i2c3_xfer: i2c3-xfer {
977 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
978 <0 RK_PA6 2 &pcfg_pull_none>;
980 i2c3_gpio: i2c3-gpio {
982 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
983 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
988 hdmii2c_xfer: hdmii2c-xfer {
989 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
990 <0 RK_PA6 1 &pcfg_pull_none>;
995 pdmm0_clk: pdmm0-clk {
996 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
999 pdmm0_fsync: pdmm0-fsync {
1000 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1003 pdmm0_sdi0: pdmm0-sdi0 {
1004 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1007 pdmm0_sdi1: pdmm0-sdi1 {
1008 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1011 pdmm0_sdi2: pdmm0-sdi2 {
1012 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1015 pdmm0_sdi3: pdmm0-sdi3 {
1016 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1019 pdmm0_clk_sleep: pdmm0-clk-sleep {
1021 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1024 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1026 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1029 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1031 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1034 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1036 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1039 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1041 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1044 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1046 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1051 otp_gpio: otp-gpio {
1052 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1056 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1061 uart0_xfer: uart0-xfer {
1062 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1063 <1 RK_PB0 1 &pcfg_pull_none>;
1066 uart0_cts: uart0-cts {
1067 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1070 uart0_rts: uart0-rts {
1071 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1074 uart0_rts_gpio: uart0-rts-gpio {
1075 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1080 uart1_xfer: uart1-xfer {
1081 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1082 <3 RK_PA6 4 &pcfg_pull_none>;
1085 uart1_cts: uart1-cts {
1086 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1089 uart1_rts: uart1-rts {
1090 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1093 uart1_rts_gpio: uart1-rts-gpio {
1094 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1099 uart2m0_xfer: uart2m0-xfer {
1100 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1101 <1 RK_PA1 2 &pcfg_pull_none>;
1106 uart2m1_xfer: uart2m1-xfer {
1107 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1108 <2 RK_PA1 1 &pcfg_pull_none>;
1113 spi0m0_clk: spi0m0-clk {
1114 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1117 spi0m0_cs0: spi0m0-cs0 {
1118 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1121 spi0m0_tx: spi0m0-tx {
1122 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1125 spi0m0_rx: spi0m0-rx {
1126 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1129 spi0m0_cs1: spi0m0-cs1 {
1130 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1135 spi0m1_clk: spi0m1-clk {
1136 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1139 spi0m1_cs0: spi0m1-cs0 {
1140 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1143 spi0m1_tx: spi0m1-tx {
1144 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1147 spi0m1_rx: spi0m1-rx {
1148 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1151 spi0m1_cs1: spi0m1-cs1 {
1152 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1157 spi0m2_clk: spi0m2-clk {
1158 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1161 spi0m2_cs0: spi0m2-cs0 {
1162 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1165 spi0m2_tx: spi0m2-tx {
1166 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1169 spi0m2_rx: spi0m2-rx {
1170 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1175 i2s1_mclk: i2s1-mclk {
1176 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1179 i2s1_sclk: i2s1-sclk {
1180 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1183 i2s1_lrckrx: i2s1-lrckrx {
1184 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1187 i2s1_lrcktx: i2s1-lrcktx {
1188 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1191 i2s1_sdi: i2s1-sdi {
1192 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1195 i2s1_sdo: i2s1-sdo {
1196 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1199 i2s1_sdio1: i2s1-sdio1 {
1200 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1203 i2s1_sdio2: i2s1-sdio2 {
1204 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1207 i2s1_sdio3: i2s1-sdio3 {
1208 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1211 i2s1_sleep: i2s1-sleep {
1213 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1214 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1215 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1216 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1217 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1218 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1219 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1220 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1221 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1226 i2s2m0_mclk: i2s2m0-mclk {
1227 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1230 i2s2m0_sclk: i2s2m0-sclk {
1231 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1234 i2s2m0_lrckrx: i2s2m0-lrckrx {
1235 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1238 i2s2m0_lrcktx: i2s2m0-lrcktx {
1239 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1242 i2s2m0_sdi: i2s2m0-sdi {
1243 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1246 i2s2m0_sdo: i2s2m0-sdo {
1247 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1250 i2s2m0_sleep: i2s2m0-sleep {
1252 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1253 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1254 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1255 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1256 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1257 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1262 i2s2m1_mclk: i2s2m1-mclk {
1263 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1266 i2s2m1_sclk: i2s2m1-sclk {
1267 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1270 i2s2m1_lrckrx: i2sm1-lrckrx {
1271 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1274 i2s2m1_lrcktx: i2s2m1-lrcktx {
1275 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1278 i2s2m1_sdi: i2s2m1-sdi {
1279 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1282 i2s2m1_sdo: i2s2m1-sdo {
1283 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1286 i2s2m1_sleep: i2s2m1-sleep {
1288 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1289 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1290 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1291 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1292 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1297 spdifm0_tx: spdifm0-tx {
1298 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1303 spdifm1_tx: spdifm1-tx {
1304 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1309 spdifm2_tx: spdifm2-tx {
1310 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1315 sdmmc0m0_pwren: sdmmc0m0-pwren {
1316 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1319 sdmmc0m0_gpio: sdmmc0m0-gpio {
1320 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1325 sdmmc0m1_pwren: sdmmc0m1-pwren {
1326 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1329 sdmmc0m1_gpio: sdmmc0m1-gpio {
1330 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1335 sdmmc0_clk: sdmmc0-clk {
1336 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1339 sdmmc0_cmd: sdmmc0-cmd {
1340 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1343 sdmmc0_dectn: sdmmc0-dectn {
1344 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1347 sdmmc0_wrprt: sdmmc0-wrprt {
1348 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1351 sdmmc0_bus1: sdmmc0-bus1 {
1352 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1355 sdmmc0_bus4: sdmmc0-bus4 {
1356 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1357 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1358 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1359 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1362 sdmmc0_gpio: sdmmc0-gpio {
1364 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1365 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1366 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1367 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1368 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1369 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1370 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1371 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1376 sdmmc0ext_clk: sdmmc0ext-clk {
1377 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1380 sdmmc0ext_cmd: sdmmc0ext-cmd {
1381 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1384 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1385 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1388 sdmmc0ext_dectn: sdmmc0ext-dectn {
1389 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1392 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1393 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1396 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1398 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1399 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1400 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1401 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1404 sdmmc0ext_gpio: sdmmc0ext-gpio {
1406 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1407 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1408 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1409 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1410 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1411 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1412 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1413 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1418 sdmmc1_clk: sdmmc1-clk {
1419 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1422 sdmmc1_cmd: sdmmc1-cmd {
1423 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1426 sdmmc1_pwren: sdmmc1-pwren {
1427 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1430 sdmmc1_wrprt: sdmmc1-wrprt {
1431 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1434 sdmmc1_dectn: sdmmc1-dectn {
1435 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1438 sdmmc1_bus1: sdmmc1-bus1 {
1439 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1442 sdmmc1_bus4: sdmmc1-bus4 {
1443 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1444 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1445 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1446 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1449 sdmmc1_gpio: sdmmc1-gpio {
1451 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1452 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1453 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1454 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1455 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1456 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1457 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1458 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1459 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1464 emmc_clk: emmc-clk {
1465 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1468 emmc_cmd: emmc-cmd {
1469 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1472 emmc_pwren: emmc-pwren {
1473 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1476 emmc_rstnout: emmc-rstnout {
1477 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1480 emmc_bus1: emmc-bus1 {
1481 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1484 emmc_bus4: emmc-bus4 {
1486 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1487 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1488 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1489 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1492 emmc_bus8: emmc-bus8 {
1494 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1495 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1496 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1497 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1498 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1499 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1500 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1501 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1506 pwm0_pin: pwm0-pin {
1507 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1512 pwm1_pin: pwm1-pin {
1513 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1518 pwm2_pin: pwm2-pin {
1519 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1524 pwmir_pin: pwmir-pin {
1525 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1530 rgmiim1_pins: rgmiim1-pins {
1533 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1535 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1537 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1539 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1541 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1543 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1545 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1547 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1549 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1551 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1553 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1555 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1557 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1559 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1561 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1564 <0 RK_PB0 1 &pcfg_pull_none>,
1566 <0 RK_PB4 1 &pcfg_pull_none>,
1568 <0 RK_PD0 1 &pcfg_pull_none>,
1570 <0 RK_PC0 1 &pcfg_pull_none>,
1572 <0 RK_PC1 1 &pcfg_pull_none>,
1574 <0 RK_PC7 1 &pcfg_pull_none>,
1576 <0 RK_PC6 1 &pcfg_pull_none>;
1579 rmiim1_pins: rmiim1-pins {
1582 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1584 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1586 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1588 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1590 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1592 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1594 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1596 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1598 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1600 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1603 <0 RK_PB3 1 &pcfg_pull_none>,
1605 <0 RK_PB4 1 &pcfg_pull_none>,
1607 <0 RK_PD0 1 &pcfg_pull_none>,
1609 <0 RK_PC3 1 &pcfg_pull_none>,
1611 <0 RK_PC0 1 &pcfg_pull_none>,
1613 <0 RK_PC1 1 &pcfg_pull_none>;
1618 fephyled_speed100: fephyled-speed100 {
1619 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1622 fephyled_speed10: fephyled-speed10 {
1623 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1626 fephyled_duplex: fephyled-duplex {
1627 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1630 fephyled_rxm0: fephyled-rxm0 {
1631 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1634 fephyled_txm0: fephyled-txm0 {
1635 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1638 fephyled_linkm0: fephyled-linkm0 {
1639 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1642 fephyled_rxm1: fephyled-rxm1 {
1643 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1646 fephyled_txm1: fephyled-txm1 {
1647 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1650 fephyled_linkm1: fephyled-linkm1 {
1651 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1656 tsadc_int: tsadc-int {
1657 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1659 tsadc_gpio: tsadc-gpio {
1660 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1665 hdmi_cec: hdmi-cec {
1666 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1669 hdmi_hpd: hdmi-hpd {
1670 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1675 dvp_d2d9_m0:dvp-d2d9-m0 {
1678 <3 RK_PA4 2 &pcfg_pull_none>,
1680 <3 RK_PA5 2 &pcfg_pull_none>,
1682 <3 RK_PA6 2 &pcfg_pull_none>,
1684 <3 RK_PA7 2 &pcfg_pull_none>,
1686 <3 RK_PB0 2 &pcfg_pull_none>,
1688 <3 RK_PB1 2 &pcfg_pull_none>,
1690 <3 RK_PB2 2 &pcfg_pull_none>,
1692 <3 RK_PB3 2 &pcfg_pull_none>,
1694 <3 RK_PA1 2 &pcfg_pull_none>,
1696 <3 RK_PA0 2 &pcfg_pull_none>,
1698 <3 RK_PA3 2 &pcfg_pull_none>,
1700 <3 RK_PA2 2 &pcfg_pull_none>;
1705 dvp_d2d9_m1:dvp-d2d9-m1 {
1708 <3 RK_PA4 2 &pcfg_pull_none>,
1710 <3 RK_PA5 2 &pcfg_pull_none>,
1712 <3 RK_PA6 2 &pcfg_pull_none>,
1714 <3 RK_PA7 2 &pcfg_pull_none>,
1716 <3 RK_PB0 2 &pcfg_pull_none>,
1718 <2 RK_PC0 4 &pcfg_pull_none>,
1720 <2 RK_PC1 4 &pcfg_pull_none>,
1722 <2 RK_PC2 4 &pcfg_pull_none>,
1724 <3 RK_PA1 2 &pcfg_pull_none>,
1726 <3 RK_PA0 2 &pcfg_pull_none>,
1728 <2 RK_PB7 4 &pcfg_pull_none>,
1730 <3 RK_PA2 2 &pcfg_pull_none>;