arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD20 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 /memreserve/ 0x80000000 0x02000000;
  13
  14 / {
  15         compatible = "socionext,uniphier-ld20";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <2>;
  22                 #size-cells = <0>;
  23
  24                 cpu-map {
  25                         cluster0 {
  26                                 core0 {
  27                                         cpu = <&cpu0>;
  28                                 };
  29                                 core1 {
  30                                         cpu = <&cpu1>;
  31                                 };
  32                         };
  33
  34                         cluster1 {
  35                                 core0 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core1 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                 };
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a72", "arm,armv8";
  47                         reg = <0 0x000>;
  48                         clocks = <&sys_clk 32>;
  49                         enable-method = "psci";
  50                         operating-points-v2 = <&cluster0_opp>;
  51                         #cooling-cells = <2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a72", "arm,armv8";
  57                         reg = <0 0x001>;
  58                         clocks = <&sys_clk 32>;
  59                         enable-method = "psci";
  60                         operating-points-v2 = <&cluster0_opp>;
  61                         #cooling-cells = <2>;
  62                 };
  63
  64                 cpu2: cpu@100 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0 0x100>;
  68                         clocks = <&sys_clk 33>;
  69                         enable-method = "psci";
  70                         operating-points-v2 = <&cluster1_opp>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 cpu3: cpu@101 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53", "arm,armv8";
  77                         reg = <0 0x101>;
  78                         clocks = <&sys_clk 33>;
  79                         enable-method = "psci";
  80                         operating-points-v2 = <&cluster1_opp>;
  81                         #cooling-cells = <2>;
  82                 };
  83         };
  84
  85         cluster0_opp: opp-table0 {
  86                 compatible = "operating-points-v2";
  87                 opp-shared;
  88
  89                 opp-250000000 {
  90                         opp-hz = /bits/ 64 <250000000>;
  91                         clock-latency-ns = <300>;
  92                 };
  93                 opp-275000000 {
  94                         opp-hz = /bits/ 64 <275000000>;
  95                         clock-latency-ns = <300>;
  96                 };
  97                 opp-500000000 {
  98                         opp-hz = /bits/ 64 <500000000>;
  99                         clock-latency-ns = <300>;
 100                 };
 101                 opp-550000000 {
 102                         opp-hz = /bits/ 64 <550000000>;
 103                         clock-latency-ns = <300>;
 104                 };
 105                 opp-666667000 {
 106                         opp-hz = /bits/ 64 <666667000>;
 107                         clock-latency-ns = <300>;
 108                 };
 109                 opp-733334000 {
 110                         opp-hz = /bits/ 64 <733334000>;
 111                         clock-latency-ns = <300>;
 112                 };
 113                 opp-1000000000 {
 114                         opp-hz = /bits/ 64 <1000000000>;
 115                         clock-latency-ns = <300>;
 116                 };
 117                 opp-1100000000 {
 118                         opp-hz = /bits/ 64 <1100000000>;
 119                         clock-latency-ns = <300>;
 120                 };
 121         };
 122
 123         cluster1_opp: opp-table1 {
 124                 compatible = "operating-points-v2";
 125                 opp-shared;
 126
 127                 opp-250000000 {
 128                         opp-hz = /bits/ 64 <250000000>;
 129                         clock-latency-ns = <300>;
 130                 };
 131                 opp-275000000 {
 132                         opp-hz = /bits/ 64 <275000000>;
 133                         clock-latency-ns = <300>;
 134                 };
 135                 opp-500000000 {
 136                         opp-hz = /bits/ 64 <500000000>;
 137                         clock-latency-ns = <300>;
 138                 };
 139                 opp-550000000 {
 140                         opp-hz = /bits/ 64 <550000000>;
 141                         clock-latency-ns = <300>;
 142                 };
 143                 opp-666667000 {
 144                         opp-hz = /bits/ 64 <666667000>;
 145                         clock-latency-ns = <300>;
 146                 };
 147                 opp-733334000 {
 148                         opp-hz = /bits/ 64 <733334000>;
 149                         clock-latency-ns = <300>;
 150                 };
 151                 opp-1000000000 {
 152                         opp-hz = /bits/ 64 <1000000000>;
 153                         clock-latency-ns = <300>;
 154                 };
 155                 opp-1100000000 {
 156                         opp-hz = /bits/ 64 <1100000000>;
 157                         clock-latency-ns = <300>;
 158                 };
 159         };
 160
 161         psci {
 162                 compatible = "arm,psci-1.0";
 163                 method = "smc";
 164         };
 165
 166         clocks {
 167                 refclk: ref {
 168                         compatible = "fixed-clock";
 169                         #clock-cells = <0>;
 170                         clock-frequency = <25000000>;
 171                 };
 172         };
 173
 174         emmc_pwrseq: emmc-pwrseq {
 175                 compatible = "mmc-pwrseq-emmc";
 176                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 177         };
 178
 179         timer {
 180                 compatible = "arm,armv8-timer";
 181                 interrupts = <1 13 4>,
 182                              <1 14 4>,
 183                              <1 11 4>,
 184                              <1 10 4>;
 185         };
 186
 187         thermal-zones {
 188                 cpu-thermal {
 189                         polling-delay-passive = <250>;  /* 250ms */
 190                         polling-delay = <1000>;         /* 1000ms */
 191                         thermal-sensors = <&pvtctl>;
 192
 193                         trips {
 194                                 cpu_crit: cpu-crit {
 195                                         temperature = <110000>; /* 110C */
 196                                         hysteresis = <2000>;
 197                                         type = "critical";
 198                                 };
 199                                 cpu_alert: cpu-alert {
 200                                         temperature = <100000>; /* 100C */
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204                         };
 205
 206                         cooling-maps {
 207                                 map0 {
 208                                         trip = <&cpu_alert>;
 209                                         cooling-device = <&cpu0
 210                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 211                                 };
 212                                 map1 {
 213                                         trip = <&cpu_alert>;
 214                                         cooling-device = <&cpu2
 215                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 216                                 };
 217                         };
 218                 };
 219         };
 220
 221         soc@0 {
 222                 compatible = "simple-bus";
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 ranges = <0 0 0 0xffffffff>;
 226
 227                 spi0: spi@54006000 {
 228                         compatible = "socionext,uniphier-scssi";
 229                         status = "disabled";
 230                         reg = <0x54006000 0x100>;
 231                         interrupts = <0 39 4>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&pinctrl_spi0>;
 234                         clocks = <&peri_clk 11>;
 235                         resets = <&peri_rst 11>;
 236                 };
 237
 238                 spi1: spi@54006100 {
 239                         compatible = "socionext,uniphier-scssi";
 240                         status = "disabled";
 241                         reg = <0x54006100 0x100>;
 242                         interrupts = <0 216 4>;
 243                         pinctrl-names = "default";
 244                         pinctrl-0 = <&pinctrl_spi1>;
 245                         clocks = <&peri_clk 11>;
 246                         resets = <&peri_rst 11>;
 247                 };
 248
 249                 spi2: spi@54006200 {
 250                         compatible = "socionext,uniphier-scssi";
 251                         status = "disabled";
 252                         reg = <0x54006200 0x100>;
 253                         interrupts = <0 229 4>;
 254                         pinctrl-names = "default";
 255                         pinctrl-0 = <&pinctrl_spi2>;
 256                         clocks = <&peri_clk 11>;
 257                         resets = <&peri_rst 11>;
 258                 };
 259
 260                 spi3: spi@54006300 {
 261                         compatible = "socionext,uniphier-scssi";
 262                         status = "disabled";
 263                         reg = <0x54006300 0x100>;
 264                         interrupts = <0 230 4>;
 265                         pinctrl-names = "default";
 266                         pinctrl-0 = <&pinctrl_spi3>;
 267                         clocks = <&peri_clk 11>;
 268                         resets = <&peri_rst 11>;
 269                 };
 270
 271                 serial0: serial@54006800 {
 272                         compatible = "socionext,uniphier-uart";
 273                         status = "disabled";
 274                         reg = <0x54006800 0x40>;
 275                         interrupts = <0 33 4>;
 276                         pinctrl-names = "default";
 277                         pinctrl-0 = <&pinctrl_uart0>;
 278                         clocks = <&peri_clk 0>;
 279                         resets = <&peri_rst 0>;
 280                 };
 281
 282                 serial1: serial@54006900 {
 283                         compatible = "socionext,uniphier-uart";
 284                         status = "disabled";
 285                         reg = <0x54006900 0x40>;
 286                         interrupts = <0 35 4>;
 287                         pinctrl-names = "default";
 288                         pinctrl-0 = <&pinctrl_uart1>;
 289                         clocks = <&peri_clk 1>;
 290                         resets = <&peri_rst 1>;
 291                 };
 292
 293                 serial2: serial@54006a00 {
 294                         compatible = "socionext,uniphier-uart";
 295                         status = "disabled";
 296                         reg = <0x54006a00 0x40>;
 297                         interrupts = <0 37 4>;
 298                         pinctrl-names = "default";
 299                         pinctrl-0 = <&pinctrl_uart2>;
 300                         clocks = <&peri_clk 2>;
 301                         resets = <&peri_rst 2>;
 302                 };
 303
 304                 serial3: serial@54006b00 {
 305                         compatible = "socionext,uniphier-uart";
 306                         status = "disabled";
 307                         reg = <0x54006b00 0x40>;
 308                         interrupts = <0 177 4>;
 309                         pinctrl-names = "default";
 310                         pinctrl-0 = <&pinctrl_uart3>;
 311                         clocks = <&peri_clk 3>;
 312                         resets = <&peri_rst 3>;
 313                 };
 314
 315                 gpio: gpio@55000000 {
 316                         compatible = "socionext,uniphier-gpio";
 317                         reg = <0x55000000 0x200>;
 318                         interrupt-parent = <&aidet>;
 319                         interrupt-controller;
 320                         #interrupt-cells = <2>;
 321                         gpio-controller;
 322                         #gpio-cells = <2>;
 323                         gpio-ranges = <&pinctrl 0 0 0>,
 324                                       <&pinctrl 96 0 0>,
 325                                       <&pinctrl 160 0 0>;
 326                         gpio-ranges-group-names = "gpio_range0",
 327                                                   "gpio_range1",
 328                                                   "gpio_range2";
 329                         ngpios = <205>;
 330                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 331                                                      <21 217 3>;
 332                 };
 333
 334                 audio@56000000 {
 335                         compatible = "socionext,uniphier-ld20-aio";
 336                         reg = <0x56000000 0x80000>;
 337                         interrupts = <0 144 4>;
 338                         pinctrl-names = "default";
 339                         pinctrl-0 = <&pinctrl_aout1>,
 340                                     <&pinctrl_aoutiec1>;
 341                         clock-names = "aio";
 342                         clocks = <&sys_clk 40>;
 343                         reset-names = "aio";
 344                         resets = <&sys_rst 40>;
 345                         #sound-dai-cells = <1>;
 346                         socionext,syscon = <&soc_glue>;
 347
 348                         i2s_port0: port@0 {
 349                                 i2s_hdmi: endpoint {
 350                                 };
 351                         };
 352
 353                         i2s_port1: port@1 {
 354                                 i2s_pcmin2: endpoint {
 355                                 };
 356                         };
 357
 358                         i2s_port2: port@2 {
 359                                 i2s_line: endpoint {
 360                                         dai-format = "i2s";
 361                                         remote-endpoint = <&evea_line>;
 362                                 };
 363                         };
 364
 365                         i2s_port3: port@3 {
 366                                 i2s_hpcmout1: endpoint {
 367                                 };
 368                         };
 369
 370                         i2s_port4: port@4 {
 371                                 i2s_hp: endpoint {
 372                                         dai-format = "i2s";
 373                                         remote-endpoint = <&evea_hp>;
 374                                 };
 375                         };
 376
 377                         spdif_port0: port@5 {
 378                                 spdif_hiecout1: endpoint {
 379                                 };
 380                         };
 381
 382                         src_port0: port@6 {
 383                                 i2s_epcmout2: endpoint {
 384                                 };
 385                         };
 386
 387                         src_port1: port@7 {
 388                                 i2s_epcmout3: endpoint {
 389                                 };
 390                         };
 391
 392                         comp_spdif_port0: port@8 {
 393                                 comp_spdif_hiecout1: endpoint {
 394                                 };
 395                         };
 396                 };
 397
 398                 codec@57900000 {
 399                         compatible = "socionext,uniphier-evea";
 400                         reg = <0x57900000 0x1000>;
 401                         clock-names = "evea", "exiv";
 402                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 403                         reset-names = "evea", "exiv", "adamv";
 404                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 405                         #sound-dai-cells = <1>;
 406
 407                         port@0 {
 408                                 evea_line: endpoint {
 409                                         remote-endpoint = <&i2s_line>;
 410                                 };
 411                         };
 412
 413                         port@1 {
 414                                 evea_hp: endpoint {
 415                                         remote-endpoint = <&i2s_hp>;
 416                                 };
 417                         };
 418                 };
 419
 420                 adamv@57920000 {
 421                         compatible = "socionext,uniphier-ld20-adamv",
 422                                      "simple-mfd", "syscon";
 423                         reg = <0x57920000 0x1000>;
 424
 425                         adamv_rst: reset {
 426                                 compatible = "socionext,uniphier-ld20-adamv-reset";
 427                                 #reset-cells = <1>;
 428                         };
 429                 };
 430
 431                 i2c0: i2c@58780000 {
 432                         compatible = "socionext,uniphier-fi2c";
 433                         status = "disabled";
 434                         reg = <0x58780000 0x80>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         interrupts = <0 41 4>;
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&pinctrl_i2c0>;
 440                         clocks = <&peri_clk 4>;
 441                         resets = <&peri_rst 4>;
 442                         clock-frequency = <100000>;
 443                 };
 444
 445                 i2c1: i2c@58781000 {
 446                         compatible = "socionext,uniphier-fi2c";
 447                         status = "disabled";
 448                         reg = <0x58781000 0x80>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         interrupts = <0 42 4>;
 452                         pinctrl-names = "default";
 453                         pinctrl-0 = <&pinctrl_i2c1>;
 454                         clocks = <&peri_clk 5>;
 455                         resets = <&peri_rst 5>;
 456                         clock-frequency = <100000>;
 457                 };
 458
 459                 i2c2: i2c@58782000 {
 460                         compatible = "socionext,uniphier-fi2c";
 461                         reg = <0x58782000 0x80>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         interrupts = <0 43 4>;
 465                         clocks = <&peri_clk 6>;
 466                         resets = <&peri_rst 6>;
 467                         clock-frequency = <400000>;
 468                 };
 469
 470                 i2c3: i2c@58783000 {
 471                         compatible = "socionext,uniphier-fi2c";
 472                         status = "disabled";
 473                         reg = <0x58783000 0x80>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         interrupts = <0 44 4>;
 477                         pinctrl-names = "default";
 478                         pinctrl-0 = <&pinctrl_i2c3>;
 479                         clocks = <&peri_clk 7>;
 480                         resets = <&peri_rst 7>;
 481                         clock-frequency = <100000>;
 482                 };
 483
 484                 i2c4: i2c@58784000 {
 485                         compatible = "socionext,uniphier-fi2c";
 486                         status = "disabled";
 487                         reg = <0x58784000 0x80>;
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         interrupts = <0 45 4>;
 491                         pinctrl-names = "default";
 492                         pinctrl-0 = <&pinctrl_i2c4>;
 493                         clocks = <&peri_clk 8>;
 494                         resets = <&peri_rst 8>;
 495                         clock-frequency = <100000>;
 496                 };
 497
 498                 i2c5: i2c@58785000 {
 499                         compatible = "socionext,uniphier-fi2c";
 500                         reg = <0x58785000 0x80>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         interrupts = <0 25 4>;
 504                         clocks = <&peri_clk 9>;
 505                         resets = <&peri_rst 9>;
 506                         clock-frequency = <400000>;
 507                 };
 508
 509                 system_bus: system-bus@58c00000 {
 510                         compatible = "socionext,uniphier-system-bus";
 511                         status = "disabled";
 512                         reg = <0x58c00000 0x400>;
 513                         #address-cells = <2>;
 514                         #size-cells = <1>;
 515                         pinctrl-names = "default";
 516                         pinctrl-0 = <&pinctrl_system_bus>;
 517                 };
 518
 519                 smpctrl@59801000 {
 520                         compatible = "socionext,uniphier-smpctrl";
 521                         reg = <0x59801000 0x400>;
 522                 };
 523
 524                 sdctrl@59810000 {
 525                         compatible = "socionext,uniphier-ld20-sdctrl",
 526                                      "simple-mfd", "syscon";
 527                         reg = <0x59810000 0x400>;
 528
 529                         sd_clk: clock {
 530                                 compatible = "socionext,uniphier-ld20-sd-clock";
 531                                 #clock-cells = <1>;
 532                         };
 533
 534                         sd_rst: reset {
 535                                 compatible = "socionext,uniphier-ld20-sd-reset";
 536                                 #reset-cells = <1>;
 537                         };
 538                 };
 539
 540                 perictrl@59820000 {
 541                         compatible = "socionext,uniphier-ld20-perictrl",
 542                                      "simple-mfd", "syscon";
 543                         reg = <0x59820000 0x200>;
 544
 545                         peri_clk: clock {
 546                                 compatible = "socionext,uniphier-ld20-peri-clock";
 547                                 #clock-cells = <1>;
 548                         };
 549
 550                         peri_rst: reset {
 551                                 compatible = "socionext,uniphier-ld20-peri-reset";
 552                                 #reset-cells = <1>;
 553                         };
 554                 };
 555
 556                 emmc: sdhc@5a000000 {
 557                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 558                         reg = <0x5a000000 0x400>;
 559                         interrupts = <0 78 4>;
 560                         pinctrl-names = "default";
 561                         pinctrl-0 = <&pinctrl_emmc>;
 562                         clocks = <&sys_clk 4>;
 563                         resets = <&sys_rst 4>;
 564                         bus-width = <8>;
 565                         mmc-ddr-1_8v;
 566                         mmc-hs200-1_8v;
 567                         mmc-pwrseq = <&emmc_pwrseq>;
 568                         cdns,phy-input-delay-legacy = <9>;
 569                         cdns,phy-input-delay-mmc-highspeed = <2>;
 570                         cdns,phy-input-delay-mmc-ddr = <3>;
 571                         cdns,phy-dll-delay-sdclk = <21>;
 572                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 573                 };
 574
 575                 soc_glue: soc-glue@5f800000 {
 576                         compatible = "socionext,uniphier-ld20-soc-glue",
 577                                      "simple-mfd", "syscon";
 578                         reg = <0x5f800000 0x2000>;
 579
 580                         pinctrl: pinctrl {
 581                                 compatible = "socionext,uniphier-ld20-pinctrl";
 582                         };
 583                 };
 584
 585                 soc-glue@5f900000 {
 586                         compatible = "socionext,uniphier-ld20-soc-glue-debug",
 587                                      "simple-mfd";
 588                         #address-cells = <1>;
 589                         #size-cells = <1>;
 590                         ranges = <0 0x5f900000 0x2000>;
 591
 592                         efuse@100 {
 593                                 compatible = "socionext,uniphier-efuse";
 594                                 reg = <0x100 0x28>;
 595                         };
 596
 597                         efuse@200 {
 598                                 compatible = "socionext,uniphier-efuse";
 599                                 reg = <0x200 0x68>;
 600                         };
 601                 };
 602
 603                 aidet: aidet@5fc20000 {
 604                         compatible = "socionext,uniphier-ld20-aidet";
 605                         reg = <0x5fc20000 0x200>;
 606                         interrupt-controller;
 607                         #interrupt-cells = <2>;
 608                 };
 609
 610                 gic: interrupt-controller@5fe00000 {
 611                         compatible = "arm,gic-v3";
 612                         reg = <0x5fe00000 0x10000>,     /* GICD */
 613                               <0x5fe80000 0x80000>;     /* GICR */
 614                         interrupt-controller;
 615                         #interrupt-cells = <3>;
 616                         interrupts = <1 9 4>;
 617                 };
 618
 619                 sysctrl@61840000 {
 620                         compatible = "socionext,uniphier-ld20-sysctrl",
 621                                      "simple-mfd", "syscon";
 622                         reg = <0x61840000 0x10000>;
 623
 624                         sys_clk: clock {
 625                                 compatible = "socionext,uniphier-ld20-clock";
 626                                 #clock-cells = <1>;
 627                         };
 628
 629                         sys_rst: reset {
 630                                 compatible = "socionext,uniphier-ld20-reset";
 631                                 #reset-cells = <1>;
 632                         };
 633
 634                         watchdog {
 635                                 compatible = "socionext,uniphier-wdt";
 636                         };
 637
 638                         pvtctl: pvtctl {
 639                                 compatible = "socionext,uniphier-ld20-thermal";
 640                                 interrupts = <0 3 4>;
 641                                 #thermal-sensor-cells = <0>;
 642                                 socionext,tmod-calibration = <0x0f22 0x68ee>;
 643                         };
 644                 };
 645
 646                 eth: ethernet@65000000 {
 647                         compatible = "socionext,uniphier-ld20-ave4";
 648                         status = "disabled";
 649                         reg = <0x65000000 0x8500>;
 650                         interrupts = <0 66 4>;
 651                         pinctrl-names = "default";
 652                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 653                         clock-names = "ether";
 654                         clocks = <&sys_clk 6>;
 655                         reset-names = "ether";
 656                         resets = <&sys_rst 6>;
 657                         phy-mode = "rgmii";
 658                         local-mac-address = [00 00 00 00 00 00];
 659                         socionext,syscon-phy-mode = <&soc_glue 0>;
 660
 661                         mdio: mdio {
 662                                 #address-cells = <1>;
 663                                 #size-cells = <0>;
 664                         };
 665                 };
 666
 667                 nand: nand@68000000 {
 668                         compatible = "socionext,uniphier-denali-nand-v5b";
 669                         status = "disabled";
 670                         reg-names = "nand_data", "denali_reg";
 671                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 672                         interrupts = <0 65 4>;
 673                         pinctrl-names = "default";
 674                         pinctrl-0 = <&pinctrl_nand>;
 675                         clock-names = "nand", "nand_x", "ecc";
 676                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 677                         resets = <&sys_rst 2>;
 678                 };
 679         };
 680 };
 681
 682 #include "uniphier-pinctrl.dtsi"
 683
 684 &pinctrl_aout1 {
 685         drive-strength = <4>;   /* default: 3.5mA */
 686
 687         ao1dacck {
 688                 pins = "AO1DACCK";
 689                 drive-strength = <5>;   /* 5mA */
 690         };
 691 };
 692
 693 &pinctrl_aoutiec1 {
 694         drive-strength = <4>;   /* default: 3.5mA */
 695
 696         ao1arc {
 697                 pins = "AO1ARC";
 698                 drive-strength = <11>;  /* 11mA */
 699         };
 700 };