1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
5 // Copyright (C) 2017 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 /memreserve/ 0x80000000 0x02000000;
14 compatible = "socionext,uniphier-pxs3";
17 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 clocks = <&sys_clk 33>;
45 enable-method = "psci";
46 operating-points-v2 = <&cluster0_opp>;
51 compatible = "arm,cortex-a53", "arm,armv8";
53 clocks = <&sys_clk 33>;
54 enable-method = "psci";
55 operating-points-v2 = <&cluster0_opp>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 clocks = <&sys_clk 33>;
63 enable-method = "psci";
64 operating-points-v2 = <&cluster0_opp>;
69 compatible = "arm,cortex-a53", "arm,armv8";
71 clocks = <&sys_clk 33>;
72 enable-method = "psci";
73 operating-points-v2 = <&cluster0_opp>;
77 cluster0_opp: opp-table {
78 compatible = "operating-points-v2";
82 opp-hz = /bits/ 64 <250000000>;
83 clock-latency-ns = <300>;
86 opp-hz = /bits/ 64 <325000000>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <500000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <650000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <666667000>;
99 clock-latency-ns = <300>;
102 opp-hz = /bits/ 64 <866667000>;
103 clock-latency-ns = <300>;
106 opp-hz = /bits/ 64 <1000000000>;
107 clock-latency-ns = <300>;
110 opp-hz = /bits/ 64 <1300000000>;
111 clock-latency-ns = <300>;
116 compatible = "arm,psci-1.0";
122 compatible = "fixed-clock";
124 clock-frequency = <25000000>;
128 emmc_pwrseq: emmc-pwrseq {
129 compatible = "mmc-pwrseq-emmc";
130 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
134 compatible = "arm,armv8-timer";
135 interrupts = <1 13 4>,
142 compatible = "simple-bus";
143 #address-cells = <1>;
145 ranges = <0 0 0 0xffffffff>;
148 compatible = "socionext,uniphier-scssi";
150 reg = <0x54006000 0x100>;
151 interrupts = <0 39 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_spi0>;
154 clocks = <&peri_clk 11>;
155 resets = <&peri_rst 11>;
159 compatible = "socionext,uniphier-scssi";
161 reg = <0x54006100 0x100>;
162 interrupts = <0 216 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_spi1>;
165 clocks = <&peri_clk 11>;
166 resets = <&peri_rst 11>;
169 serial0: serial@54006800 {
170 compatible = "socionext,uniphier-uart";
172 reg = <0x54006800 0x40>;
173 interrupts = <0 33 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart0>;
176 clocks = <&peri_clk 0>;
177 resets = <&peri_rst 0>;
180 serial1: serial@54006900 {
181 compatible = "socionext,uniphier-uart";
183 reg = <0x54006900 0x40>;
184 interrupts = <0 35 4>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1>;
187 clocks = <&peri_clk 1>;
188 resets = <&peri_rst 1>;
191 serial2: serial@54006a00 {
192 compatible = "socionext,uniphier-uart";
194 reg = <0x54006a00 0x40>;
195 interrupts = <0 37 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart2>;
198 clocks = <&peri_clk 2>;
199 resets = <&peri_rst 2>;
202 serial3: serial@54006b00 {
203 compatible = "socionext,uniphier-uart";
205 reg = <0x54006b00 0x40>;
206 interrupts = <0 177 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart3>;
209 clocks = <&peri_clk 3>;
210 resets = <&peri_rst 3>;
213 gpio: gpio@55000000 {
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x55000000 0x200>;
216 interrupt-parent = <&aidet>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
221 gpio-ranges = <&pinctrl 0 0 0>,
224 gpio-ranges-group-names = "gpio_range0",
228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
233 compatible = "socionext,uniphier-fi2c";
235 reg = <0x58780000 0x80>;
236 #address-cells = <1>;
238 interrupts = <0 41 4>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_i2c0>;
241 clocks = <&peri_clk 4>;
242 resets = <&peri_rst 4>;
243 clock-frequency = <100000>;
247 compatible = "socionext,uniphier-fi2c";
249 reg = <0x58781000 0x80>;
250 #address-cells = <1>;
252 interrupts = <0 42 4>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_i2c1>;
255 clocks = <&peri_clk 5>;
256 resets = <&peri_rst 5>;
257 clock-frequency = <100000>;
261 compatible = "socionext,uniphier-fi2c";
263 reg = <0x58782000 0x80>;
264 #address-cells = <1>;
266 interrupts = <0 43 4>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_i2c2>;
269 clocks = <&peri_clk 6>;
270 resets = <&peri_rst 6>;
271 clock-frequency = <100000>;
275 compatible = "socionext,uniphier-fi2c";
277 reg = <0x58783000 0x80>;
278 #address-cells = <1>;
280 interrupts = <0 44 4>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c3>;
283 clocks = <&peri_clk 7>;
284 resets = <&peri_rst 7>;
285 clock-frequency = <100000>;
288 /* chip-internal connection for HDMI */
290 compatible = "socionext,uniphier-fi2c";
291 reg = <0x58786000 0x80>;
292 #address-cells = <1>;
294 interrupts = <0 26 4>;
295 clocks = <&peri_clk 10>;
296 resets = <&peri_rst 10>;
297 clock-frequency = <400000>;
300 system_bus: system-bus@58c00000 {
301 compatible = "socionext,uniphier-system-bus";
303 reg = <0x58c00000 0x400>;
304 #address-cells = <2>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_system_bus>;
311 compatible = "socionext,uniphier-smpctrl";
312 reg = <0x59801000 0x400>;
316 compatible = "socionext,uniphier-pxs3-sdctrl",
317 "simple-mfd", "syscon";
318 reg = <0x59810000 0x400>;
321 compatible = "socionext,uniphier-pxs3-sd-clock";
326 compatible = "socionext,uniphier-pxs3-sd-reset";
332 compatible = "socionext,uniphier-pxs3-perictrl",
333 "simple-mfd", "syscon";
334 reg = <0x59820000 0x200>;
337 compatible = "socionext,uniphier-pxs3-peri-clock";
342 compatible = "socionext,uniphier-pxs3-peri-reset";
347 emmc: sdhc@5a000000 {
348 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
349 reg = <0x5a000000 0x400>;
350 interrupts = <0 78 4>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_emmc>;
353 clocks = <&sys_clk 4>;
354 resets = <&sys_rst 4>;
358 mmc-pwrseq = <&emmc_pwrseq>;
359 cdns,phy-input-delay-legacy = <9>;
360 cdns,phy-input-delay-mmc-highspeed = <2>;
361 cdns,phy-input-delay-mmc-ddr = <3>;
362 cdns,phy-dll-delay-sdclk = <21>;
363 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
366 soc_glue: soc-glue@5f800000 {
367 compatible = "socionext,uniphier-pxs3-soc-glue",
368 "simple-mfd", "syscon";
369 reg = <0x5f800000 0x2000>;
372 compatible = "socionext,uniphier-pxs3-pinctrl";
377 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
379 #address-cells = <1>;
381 ranges = <0 0x5f900000 0x2000>;
384 compatible = "socionext,uniphier-efuse";
389 compatible = "socionext,uniphier-efuse";
394 aidet: aidet@5fc20000 {
395 compatible = "socionext,uniphier-pxs3-aidet";
396 reg = <0x5fc20000 0x200>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
401 gic: interrupt-controller@5fe00000 {
402 compatible = "arm,gic-v3";
403 reg = <0x5fe00000 0x10000>, /* GICD */
404 <0x5fe80000 0x80000>; /* GICR */
405 interrupt-controller;
406 #interrupt-cells = <3>;
407 interrupts = <1 9 4>;
411 compatible = "socionext,uniphier-pxs3-sysctrl",
412 "simple-mfd", "syscon";
413 reg = <0x61840000 0x10000>;
416 compatible = "socionext,uniphier-pxs3-clock";
421 compatible = "socionext,uniphier-pxs3-reset";
426 compatible = "socionext,uniphier-wdt";
430 eth0: ethernet@65000000 {
431 compatible = "socionext,uniphier-pxs3-ave4";
433 reg = <0x65000000 0x8500>;
434 interrupts = <0 66 4>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_ether_rgmii>;
437 clock-names = "ether";
438 clocks = <&sys_clk 6>;
439 reset-names = "ether";
440 resets = <&sys_rst 6>;
442 local-mac-address = [00 00 00 00 00 00];
443 socionext,syscon-phy-mode = <&soc_glue 0>;
446 #address-cells = <1>;
451 eth1: ethernet@65200000 {
452 compatible = "socionext,uniphier-pxs3-ave4";
454 reg = <0x65200000 0x8500>;
455 interrupts = <0 67 4>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_ether1_rgmii>;
458 clock-names = "ether";
459 clocks = <&sys_clk 7>;
460 reset-names = "ether";
461 resets = <&sys_rst 7>;
463 local-mac-address = [00 00 00 00 00 00];
464 socionext,syscon-phy-mode = <&soc_glue 1>;
467 #address-cells = <1>;
472 nand: nand@68000000 {
473 compatible = "socionext,uniphier-denali-nand-v5b";
475 reg-names = "nand_data", "denali_reg";
476 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
477 interrupts = <0 65 4>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_nand>;
480 clock-names = "nand", "nand_x", "ecc";
481 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
482 resets = <&sys_rst 2>;
487 #include "uniphier-pinctrl.dtsi"