arch/arm64/include/asm/arch_gicv3.h

   1 /*
   2  * arch/arm64/include/asm/arch_gicv3.h
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #ifndef __ASM_ARCH_GICV3_H
  19 #define __ASM_ARCH_GICV3_H
  20
  21 #include <asm/sysreg.h>
  22
  23 #define ICC_BPR0_EL1                    sys_reg(3, 0, 12, 8, 3)
  24 #define ICC_AP1Rn_EL1(n)                sys_reg(3, 0, 12, 9, n)
  25 #define ICC_EOIR1_EL1                   sys_reg(3, 0, 12, 12, 1)
  26 #define ICC_DIR_EL1                     sys_reg(3, 0, 12, 11, 1)
  27 #define ICC_IAR1_EL1                    sys_reg(3, 0, 12, 12, 0)
  28 #define ICC_SGI1R_EL1                   sys_reg(3, 0, 12, 11, 5)
  29 #define ICC_PMR_EL1                     sys_reg(3, 0, 4, 6, 0)
  30 #define ICC_CTLR_EL1                    sys_reg(3, 0, 12, 12, 4)
  31 #define ICC_SRE_EL1                     sys_reg(3, 0, 12, 12, 5)
  32 #define ICC_GRPEN0_EL1                  sys_reg(3, 0, 12, 12, 6)
  33 #define ICC_GRPEN1_EL1                  sys_reg(3, 0, 12, 12, 7)
  34 #define ICC_BPR1_EL1                    sys_reg(3, 0, 12, 12, 3)
  35 #define ICC_HPPIR1_EL1                  sys_reg(3, 0, 12, 12, 2)
  36 #define ICC_SRE_EL2                     sys_reg(3, 4, 12, 9, 5)
  37
  38 /*
  39  * System register definitions
  40  */
  41 #define ICH_VSEIR_EL2                   sys_reg(3, 4, 12, 9, 4)
  42 #define ICH_HCR_EL2                     sys_reg(3, 4, 12, 11, 0)
  43 #define ICH_VTR_EL2                     sys_reg(3, 4, 12, 11, 1)
  44 #define ICH_MISR_EL2                    sys_reg(3, 4, 12, 11, 2)
  45 #define ICH_EISR_EL2                    sys_reg(3, 4, 12, 11, 3)
  46 #define ICH_ELSR_EL2                    sys_reg(3, 4, 12, 11, 5)
  47 #define ICH_VMCR_EL2                    sys_reg(3, 4, 12, 11, 7)
  48
  49 #define __LR0_EL2(x)                    sys_reg(3, 4, 12, 12, x)
  50 #define __LR8_EL2(x)                    sys_reg(3, 4, 12, 13, x)
  51
  52 #define ICH_LR0_EL2                     __LR0_EL2(0)
  53 #define ICH_LR1_EL2                     __LR0_EL2(1)
  54 #define ICH_LR2_EL2                     __LR0_EL2(2)
  55 #define ICH_LR3_EL2                     __LR0_EL2(3)
  56 #define ICH_LR4_EL2                     __LR0_EL2(4)
  57 #define ICH_LR5_EL2                     __LR0_EL2(5)
  58 #define ICH_LR6_EL2                     __LR0_EL2(6)
  59 #define ICH_LR7_EL2                     __LR0_EL2(7)
  60 #define ICH_LR8_EL2                     __LR8_EL2(0)
  61 #define ICH_LR9_EL2                     __LR8_EL2(1)
  62 #define ICH_LR10_EL2                    __LR8_EL2(2)
  63 #define ICH_LR11_EL2                    __LR8_EL2(3)
  64 #define ICH_LR12_EL2                    __LR8_EL2(4)
  65 #define ICH_LR13_EL2                    __LR8_EL2(5)
  66 #define ICH_LR14_EL2                    __LR8_EL2(6)
  67 #define ICH_LR15_EL2                    __LR8_EL2(7)
  68
  69 #define __AP0Rx_EL2(x)                  sys_reg(3, 4, 12, 8, x)
  70 #define ICH_AP0R0_EL2                   __AP0Rx_EL2(0)
  71 #define ICH_AP0R1_EL2                   __AP0Rx_EL2(1)
  72 #define ICH_AP0R2_EL2                   __AP0Rx_EL2(2)
  73 #define ICH_AP0R3_EL2                   __AP0Rx_EL2(3)
  74
  75 #define __AP1Rx_EL2(x)                  sys_reg(3, 4, 12, 9, x)
  76 #define ICH_AP1R0_EL2                   __AP1Rx_EL2(0)
  77 #define ICH_AP1R1_EL2                   __AP1Rx_EL2(1)
  78 #define ICH_AP1R2_EL2                   __AP1Rx_EL2(2)
  79 #define ICH_AP1R3_EL2                   __AP1Rx_EL2(3)
  80
  81 #ifndef __ASSEMBLY__
  82
  83 #include <linux/stringify.h>
  84 #include <asm/barrier.h>
  85 #include <asm/cacheflush.h>
  86
  87 #define read_gicreg                     read_sysreg_s
  88 #define write_gicreg                    write_sysreg_s
  89
  90 /*
  91  * Low-level accessors
  92  *
  93  * These system registers are 32 bits, but we make sure that the compiler
  94  * sets the GP register's most significant bits to 0 with an explicit cast.
  95  */
  96
  97 static inline void gic_write_eoir(u32 irq)
  98 {
  99         write_sysreg_s(irq, ICC_EOIR1_EL1);
 100         isb();
 101 }
 102
 103 static inline void gic_write_dir(u32 irq)
 104 {
 105         write_sysreg_s(irq, ICC_DIR_EL1);
 106         isb();
 107 }
 108
 109 static inline u64 gic_read_iar_common(void)
 110 {
 111         u64 irqstat;
 112
 113         irqstat = read_sysreg_s(ICC_IAR1_EL1);
 114         dsb(sy);
 115         return irqstat;
 116 }
 117
 118 /*
 119  * Cavium ThunderX erratum 23154
 120  *
 121  * The gicv3 of ThunderX requires a modified version for reading the
 122  * IAR status to ensure data synchronization (access to icc_iar1_el1
 123  * is not sync'ed before and after).
 124  */
 125 static inline u64 gic_read_iar_cavium_thunderx(void)
 126 {
 127         u64 irqstat;
 128
 129         nops(8);
 130         irqstat = read_sysreg_s(ICC_IAR1_EL1);
 131         nops(4);
 132         mb();
 133
 134         return irqstat;
 135 }
 136
 137 static inline void gic_write_pmr(u32 val)
 138 {
 139         write_sysreg_s(val, ICC_PMR_EL1);
 140 }
 141
 142 static inline void gic_write_ctlr(u32 val)
 143 {
 144         write_sysreg_s(val, ICC_CTLR_EL1);
 145         isb();
 146 }
 147
 148 static inline void gic_write_grpen1(u32 val)
 149 {
 150         write_sysreg_s(val, ICC_GRPEN1_EL1);
 151         isb();
 152 }
 153
 154 static inline void gic_write_sgi1r(u64 val)
 155 {
 156         write_sysreg_s(val, ICC_SGI1R_EL1);
 157 }
 158
 159 static inline u32 gic_read_sre(void)
 160 {
 161         return read_sysreg_s(ICC_SRE_EL1);
 162 }
 163
 164 static inline void gic_write_sre(u32 val)
 165 {
 166         write_sysreg_s(val, ICC_SRE_EL1);
 167         isb();
 168 }
 169
 170 static inline void gic_write_bpr1(u32 val)
 171 {
 172         asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
 173 }
 174
 175 #define gic_read_typer(c)               readq_relaxed(c)
 176 #define gic_write_irouter(v, c)         writeq_relaxed(v, c)
 177
 178 #define gic_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
 179
 180 #define gits_read_baser(c)              readq_relaxed(c)
 181 #define gits_write_baser(v, c)          writeq_relaxed(v, c)
 182
 183 #define gits_read_cbaser(c)             readq_relaxed(c)
 184 #define gits_write_cbaser(v, c)         writeq_relaxed(v, c)
 185
 186 #define gits_write_cwriter(v, c)        writeq_relaxed(v, c)
 187
 188 #define gicr_read_propbaser(c)          readq_relaxed(c)
 189 #define gicr_write_propbaser(v, c)      writeq_relaxed(v, c)
 190
 191 #define gicr_write_pendbaser(v, c)      writeq_relaxed(v, c)
 192 #define gicr_read_pendbaser(c)          readq_relaxed(c)
 193
 194 #endif /* __ASSEMBLY__ */
 195 #endif /* __ASM_ARCH_GICV3_H */