arch/arm64/include/asm/assembler.h

   1 /*
   2  * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
   3  *
   4  * Copyright (C) 1996-2000 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASSEMBLY__
  20 #error "Only include this from assembly code"
  21 #endif
  22
  23 #ifndef __ASM_ASSEMBLER_H
  24 #define __ASM_ASSEMBLER_H
  25
  26 #include <asm/asm-offsets.h>
  27 #include <asm/cpufeature.h>
  28 #include <asm/page.h>
  29 #include <asm/pgtable-hwdef.h>
  30 #include <asm/ptrace.h>
  31 #include <asm/thread_info.h>
  32
  33 /*
  34  * Enable and disable interrupts.
  35  */
  36         .macro  disable_irq
  37         msr     daifset, #2
  38         .endm
  39
  40         .macro  enable_irq
  41         msr     daifclr, #2
  42         .endm
  43
  44         .macro  save_and_disable_irq, flags
  45         mrs     \flags, daif
  46         msr     daifset, #2
  47         .endm
  48
  49         .macro  restore_irq, flags
  50         msr     daif, \flags
  51         .endm
  52
  53 /*
  54  * Enable and disable debug exceptions.
  55  */
  56         .macro  disable_dbg
  57         msr     daifset, #8
  58         .endm
  59
  60         .macro  enable_dbg
  61         msr     daifclr, #8
  62         .endm
  63
  64         .macro  disable_step_tsk, flgs, tmp
  65         tbz     \flgs, #TIF_SINGLESTEP, 9990f
  66         mrs     \tmp, mdscr_el1
  67         bic     \tmp, \tmp, #1
  68         msr     mdscr_el1, \tmp
  69         isb     // Synchronise with enable_dbg
  70 9990:
  71         .endm
  72
  73         .macro  enable_step_tsk, flgs, tmp
  74         tbz     \flgs, #TIF_SINGLESTEP, 9990f
  75         disable_dbg
  76         mrs     \tmp, mdscr_el1
  77         orr     \tmp, \tmp, #1
  78         msr     mdscr_el1, \tmp
  79 9990:
  80         .endm
  81
  82 /*
  83  * Enable both debug exceptions and interrupts. This is likely to be
  84  * faster than two daifclr operations, since writes to this register
  85  * are self-synchronising.
  86  */
  87         .macro  enable_dbg_and_irq
  88         msr     daifclr, #(8 | 2)
  89         .endm
  90
  91 /*
  92  * SMP data memory barrier
  93  */
  94         .macro  smp_dmb, opt
  95         dmb     \opt
  96         .endm
  97
  98 /*
  99  * Value prediction barrier
 100  */
 101         .macro  csdb
 102         hint    #20
 103         .endm
 104
 105 /*
 106  * Sanitise a 64-bit bounded index wrt speculation, returning zero if out
 107  * of bounds.
 108  */
 109         .macro  mask_nospec64, idx, limit, tmp
 110         sub     \tmp, \idx, \limit
 111         bic     \tmp, \tmp, \idx
 112         and     \idx, \idx, \tmp, asr #63
 113         csdb
 114         .endm
 115
 116 /*
 117  * NOP sequence
 118  */
 119         .macro  nops, num
 120         .rept   \num
 121         nop
 122         .endr
 123         .endm
 124
 125 /*
 126  * Emit an entry into the exception table
 127  */
 128         .macro          _asm_extable, from, to
 129         .pushsection    __ex_table, "a"
 130         .align          3
 131         .long           (\from - .), (\to - .)
 132         .popsection
 133         .endm
 134
 135 #define USER(l, x...)                           \
 136 9999:   x;                                      \
 137         _asm_extable    9999b, l
 138
 139 /*
 140  * Register aliases.
 141  */
 142 lr      .req    x30             // link register
 143
 144 /*
 145  * Vector entry
 146  */
 147          .macro ventry  label
 148         .align  7
 149         b       \label
 150         .endm
 151
 152 /*
 153  * Select code when configured for BE.
 154  */
 155 #ifdef CONFIG_CPU_BIG_ENDIAN
 156 #define CPU_BE(code...) code
 157 #else
 158 #define CPU_BE(code...)
 159 #endif
 160
 161 /*
 162  * Select code when configured for LE.
 163  */
 164 #ifdef CONFIG_CPU_BIG_ENDIAN
 165 #define CPU_LE(code...)
 166 #else
 167 #define CPU_LE(code...) code
 168 #endif
 169
 170 /*
 171  * Define a macro that constructs a 64-bit value by concatenating two
 172  * 32-bit registers. Note that on big endian systems the order of the
 173  * registers is swapped.
 174  */
 175 #ifndef CONFIG_CPU_BIG_ENDIAN
 176         .macro  regs_to_64, rd, lbits, hbits
 177 #else
 178         .macro  regs_to_64, rd, hbits, lbits
 179 #endif
 180         orr     \rd, \lbits, \hbits, lsl #32
 181         .endm
 182
 183 /*
 184  * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
 185  * <symbol> is within the range +/- 4 GB of the PC when running
 186  * in core kernel context. In module context, a movz/movk sequence
 187  * is used, since modules may be loaded far away from the kernel
 188  * when KASLR is in effect.
 189  */
 190         /*
 191          * @dst: destination register (64 bit wide)
 192          * @sym: name of the symbol
 193          */
 194         .macro  adr_l, dst, sym
 195 #ifndef MODULE
 196         adrp    \dst, \sym
 197         add     \dst, \dst, :lo12:\sym
 198 #else
 199         movz    \dst, #:abs_g3:\sym
 200         movk    \dst, #:abs_g2_nc:\sym
 201         movk    \dst, #:abs_g1_nc:\sym
 202         movk    \dst, #:abs_g0_nc:\sym
 203 #endif
 204         .endm
 205
 206         /*
 207          * @dst: destination register (32 or 64 bit wide)
 208          * @sym: name of the symbol
 209          * @tmp: optional 64-bit scratch register to be used if <dst> is a
 210          *       32-bit wide register, in which case it cannot be used to hold
 211          *       the address
 212          */
 213         .macro  ldr_l, dst, sym, tmp=
 214 #ifndef MODULE
 215         .ifb    \tmp
 216         adrp    \dst, \sym
 217         ldr     \dst, [\dst, :lo12:\sym]
 218         .else
 219         adrp    \tmp, \sym
 220         ldr     \dst, [\tmp, :lo12:\sym]
 221         .endif
 222 #else
 223         .ifb    \tmp
 224         adr_l   \dst, \sym
 225         ldr     \dst, [\dst]
 226         .else
 227         adr_l   \tmp, \sym
 228         ldr     \dst, [\tmp]
 229         .endif
 230 #endif
 231         .endm
 232
 233         /*
 234          * @src: source register (32 or 64 bit wide)
 235          * @sym: name of the symbol
 236          * @tmp: mandatory 64-bit scratch register to calculate the address
 237          *       while <src> needs to be preserved.
 238          */
 239         .macro  str_l, src, sym, tmp
 240 #ifndef MODULE
 241         adrp    \tmp, \sym
 242         str     \src, [\tmp, :lo12:\sym]
 243 #else
 244         adr_l   \tmp, \sym
 245         str     \src, [\tmp]
 246 #endif
 247         .endm
 248
 249         /*
 250          * @dst: Result of per_cpu(sym, smp_processor_id()), can be SP for
 251          *       non-module code
 252          * @sym: The name of the per-cpu variable
 253          * @tmp: scratch register
 254          */
 255         .macro adr_this_cpu, dst, sym, tmp
 256 #ifndef MODULE
 257         adrp    \tmp, \sym
 258         add     \dst, \tmp, #:lo12:\sym
 259 #else
 260         adr_l   \dst, \sym
 261 #endif
 262         mrs     \tmp, tpidr_el1
 263         add     \dst, \dst, \tmp
 264         .endm
 265
 266         /*
 267          * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
 268          * @sym: The name of the per-cpu variable
 269          * @tmp: scratch register
 270          */
 271         .macro ldr_this_cpu dst, sym, tmp
 272         adr_l   \dst, \sym
 273         mrs     \tmp, tpidr_el1
 274         ldr     \dst, [\dst, \tmp]
 275         .endm
 276
 277 /*
 278  * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
 279  */
 280         .macro  vma_vm_mm, rd, rn
 281         ldr     \rd, [\rn, #VMA_VM_MM]
 282         .endm
 283
 284 /*
 285  * mmid - get context id from mm pointer (mm->context.id)
 286  */
 287         .macro  mmid, rd, rn
 288         ldr     \rd, [\rn, #MM_CONTEXT_ID]
 289         .endm
 290 /*
 291  * read_ctr - read CTR_EL0. If the system has mismatched
 292  * cache line sizes, provide the system wide safe value
 293  * from arm64_ftr_reg_ctrel0.sys_val
 294  */
 295         .macro  read_ctr, reg
 296 alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
 297         mrs     \reg, ctr_el0                   // read CTR
 298         nop
 299 alternative_else
 300         ldr_l   \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
 301 alternative_endif
 302         .endm
 303
 304
 305 /*
 306  * raw_dcache_line_size - get the minimum D-cache line size on this CPU
 307  * from the CTR register.
 308  */
 309         .macro  raw_dcache_line_size, reg, tmp
 310         mrs     \tmp, ctr_el0                   // read CTR
 311         ubfm    \tmp, \tmp, #16, #19            // cache line size encoding
 312         mov     \reg, #4                        // bytes per word
 313         lsl     \reg, \reg, \tmp                // actual cache line size
 314         .endm
 315
 316 /*
 317  * dcache_line_size - get the safe D-cache line size across all CPUs
 318  */
 319         .macro  dcache_line_size, reg, tmp
 320         read_ctr        \tmp
 321         ubfm            \tmp, \tmp, #16, #19    // cache line size encoding
 322         mov             \reg, #4                // bytes per word
 323         lsl             \reg, \reg, \tmp        // actual cache line size
 324         .endm
 325
 326 /*
 327  * raw_icache_line_size - get the minimum I-cache line size on this CPU
 328  * from the CTR register.
 329  */
 330         .macro  raw_icache_line_size, reg, tmp
 331         mrs     \tmp, ctr_el0                   // read CTR
 332         and     \tmp, \tmp, #0xf                // cache line size encoding
 333         mov     \reg, #4                        // bytes per word
 334         lsl     \reg, \reg, \tmp                // actual cache line size
 335         .endm
 336
 337 /*
 338  * icache_line_size - get the safe I-cache line size across all CPUs
 339  */
 340         .macro  icache_line_size, reg, tmp
 341         read_ctr        \tmp
 342         and             \tmp, \tmp, #0xf        // cache line size encoding
 343         mov             \reg, #4                // bytes per word
 344         lsl             \reg, \reg, \tmp        // actual cache line size
 345         .endm
 346
 347 /*
 348  * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
 349  */
 350         .macro  tcr_set_idmap_t0sz, valreg, tmpreg
 351 #ifndef CONFIG_ARM64_VA_BITS_48
 352         ldr_l   \tmpreg, idmap_t0sz
 353         bfi     \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
 354 #endif
 355         .endm
 356
 357 /*
 358  * Macro to perform a data cache maintenance for the interval
 359  * [kaddr, kaddr + size)
 360  *
 361  *      op:             operation passed to dc instruction
 362  *      domain:         domain used in dsb instruciton
 363  *      kaddr:          starting virtual address of the region
 364  *      size:           size of the region
 365  *      Corrupts:       kaddr, size, tmp1, tmp2
 366  */
 367         .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
 368         dcache_line_size \tmp1, \tmp2
 369         add     \size, \kaddr, \size
 370         sub     \tmp2, \tmp1, #1
 371         bic     \kaddr, \kaddr, \tmp2
 372 9998:
 373         .if     (\op == cvau || \op == cvac)
 374 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
 375         dc      \op, \kaddr
 376 alternative_else
 377         dc      civac, \kaddr
 378 alternative_endif
 379         .elseif (\op == cvap)
 380 alternative_if ARM64_HAS_DCPOP
 381         sys 3, c7, c12, 1, \kaddr       // dc cvap
 382 alternative_else
 383         dc      cvac, \kaddr
 384 alternative_endif
 385         .else
 386         dc      \op, \kaddr
 387         .endif
 388         add     \kaddr, \kaddr, \tmp1
 389         cmp     \kaddr, \size
 390         b.lo    9998b
 391         dsb     \domain
 392         .endm
 393
 394 /*
 395  * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
 396  */
 397         .macro  reset_pmuserenr_el0, tmpreg
 398         mrs     \tmpreg, id_aa64dfr0_el1        // Check ID_AA64DFR0_EL1 PMUVer
 399         sbfx    \tmpreg, \tmpreg, #8, #4
 400         cmp     \tmpreg, #1                     // Skip if no PMU present
 401         b.lt    9000f
 402         msr     pmuserenr_el0, xzr              // Disable PMU access from EL0
 403 9000:
 404         .endm
 405
 406 /*
 407  * copy_page - copy src to dest using temp registers t1-t8
 408  */
 409         .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
 410 9998:   ldp     \t1, \t2, [\src]
 411         ldp     \t3, \t4, [\src, #16]
 412         ldp     \t5, \t6, [\src, #32]
 413         ldp     \t7, \t8, [\src, #48]
 414         add     \src, \src, #64
 415         stnp    \t1, \t2, [\dest]
 416         stnp    \t3, \t4, [\dest, #16]
 417         stnp    \t5, \t6, [\dest, #32]
 418         stnp    \t7, \t8, [\dest, #48]
 419         add     \dest, \dest, #64
 420         tst     \src, #(PAGE_SIZE - 1)
 421         b.ne    9998b
 422         .endm
 423
 424 /*
 425  * Annotate a function as position independent, i.e., safe to be called before
 426  * the kernel virtual mapping is activated.
 427  */
 428 #define ENDPIPROC(x)                    \
 429         .globl  __pi_##x;               \
 430         .type   __pi_##x, %function;    \
 431         .set    __pi_##x, x;            \
 432         .size   __pi_##x, . - x;        \
 433         ENDPROC(x)
 434
 435 /*
 436  * Annotate a function as being unsuitable for kprobes.
 437  */
 438 #ifdef CONFIG_KPROBES
 439 #define NOKPROBE(x)                             \
 440         .pushsection "_kprobe_blacklist", "aw"; \
 441         .quad   x;                              \
 442         .popsection;
 443 #else
 444 #define NOKPROBE(x)
 445 #endif
 446         /*
 447          * Emit a 64-bit absolute little endian symbol reference in a way that
 448          * ensures that it will be resolved at build time, even when building a
 449          * PIE binary. This requires cooperation from the linker script, which
 450          * must emit the lo32/hi32 halves individually.
 451          */
 452         .macro  le64sym, sym
 453         .long   \sym\()_lo32
 454         .long   \sym\()_hi32
 455         .endm
 456
 457         /*
 458          * mov_q - move an immediate constant into a 64-bit register using
 459          *         between 2 and 4 movz/movk instructions (depending on the
 460          *         magnitude and sign of the operand)
 461          */
 462         .macro  mov_q, reg, val
 463         .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
 464         movz    \reg, :abs_g1_s:\val
 465         .else
 466         .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
 467         movz    \reg, :abs_g2_s:\val
 468         .else
 469         movz    \reg, :abs_g3:\val
 470         movk    \reg, :abs_g2_nc:\val
 471         .endif
 472         movk    \reg, :abs_g1_nc:\val
 473         .endif
 474         movk    \reg, :abs_g0_nc:\val
 475         .endm
 476
 477 /*
 478  * Return the current thread_info.
 479  */
 480         .macro  get_thread_info, rd
 481         mrs     \rd, sp_el0
 482         .endm
 483
 484 /**
 485  * Errata workaround prior to disable MMU. Insert an ISB immediately prior
 486  * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
 487  */
 488         .macro pre_disable_mmu_workaround
 489 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
 490         isb
 491 #endif
 492         .endm
 493
 494         .macro  pte_to_phys, phys, pte
 495         and     \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
 496         .endm
 497
 498 #endif  /* __ASM_ASSEMBLER_H */