arm64: Move post_ttbr_update_workaround to C code

Commit 95e3de3590e3 upstream.

We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit c10e4aa77814063ac459fab673a5a392b7334b42)

CVE-2017-5753
CVE-2017-5715
CVE-2017-5754

Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
Acked-by: Brad Figg <brad.figg@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 48d977685a8407907aa25f4a4c0ac613f45616e5..463619dcadd4a9ac9c4aa2b984764a4aa0817dc8 100644 (file)
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -481,18 +481,6 @@ alternative_endif
        mrs     \rd, sp_el0
        .endm
 
-/*
- * Errata workaround post TTBRx_EL1 update.
- */
-       .macro  post_ttbr_update_workaround
-#ifdef CONFIG_CAVIUM_ERRATUM_27456
-alternative_if ARM64_WORKAROUND_CAVIUM_27456
-       ic      iallu
-       dsb     nsh
-       isb
-alternative_else_nop_endif
-#endif
-       .endm
 /**
  * Errata workaround prior to disable MMU. Insert an ISB immediately prior
  * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index d5e7ef08fac89687b6b50e37d9f0529a9913735e..fd695e860ecb2370952fd5975faf3a0d10bb277a 100644 (file)
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -277,7 +277,7 @@ alternative_else_nop_endif
         * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
         * corruption).
         */
-       post_ttbr_update_workaround
+       bl      post_ttbr_update_workaround
        .endif
 1:
        .if     \el != 0

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index db28958d9e4f7c7942ecbaf8ca2564b4f824052b..23498d032c820821a515f7f483861594b394b447 100644 (file)
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -235,6 +235,15 @@ switch_mm_fastpath:
                cpu_switch_mm(mm->pgd, mm);
 }
 
+/* Errata workaround post TTBRx_EL1 update. */
+asmlinkage void post_ttbr_update_workaround(void)
+{
+       asm(ALTERNATIVE("nop; nop; nop",
+                       "ic iallu; dsb nsh; isb",
+                       ARM64_WORKAROUND_CAVIUM_27456,
+                       CONFIG_CAVIUM_ERRATUM_27456));
+}
+
 static int asids_init(void)
 {
        asid_bits = get_cpu_asid_bits();

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index c25e58bc29100542eb8aac896328a97b5368fc44..27058f3fd1320d9141604e97e46a9d814c604046 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -148,8 +148,7 @@ ENTRY(cpu_do_switch_mm)
        isb
        msr     ttbr0_el1, x0                   // now update TTBR0
        isb
-       post_ttbr_update_workaround
-       ret
+       b       post_ttbr_update_workaround     // Back to C code...
 ENDPROC(cpu_do_switch_mm)
 
        .pushsection ".idmap.text", "awx"