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git.proxmox.com Git - mirror_ubuntu-disco-kernel.git/blob - arch/arm64/kvm/hyp/switch.c
2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/types.h>
19 #include <linux/jump_label.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
24 #include <asm/fpsimd.h>
25 #include <asm/debug-monitors.h>
27 static bool __hyp_text
__fpsimd_enabled_nvhe(void)
29 return !(read_sysreg(cptr_el2
) & CPTR_EL2_TFP
);
32 static bool __hyp_text
__fpsimd_enabled_vhe(void)
34 return !!(read_sysreg(cpacr_el1
) & CPACR_EL1_FPEN
);
37 static hyp_alternate_select(__fpsimd_is_enabled
,
38 __fpsimd_enabled_nvhe
, __fpsimd_enabled_vhe
,
39 ARM64_HAS_VIRT_HOST_EXTN
);
41 bool __hyp_text
__fpsimd_enabled(void)
43 return __fpsimd_is_enabled()();
46 static void __hyp_text
__activate_traps_vhe(void)
50 val
= read_sysreg(cpacr_el1
);
52 val
&= ~(CPACR_EL1_FPEN
| CPACR_EL1_ZEN
);
53 write_sysreg(val
, cpacr_el1
);
55 write_sysreg(__kvm_hyp_vector
, vbar_el1
);
58 static void __hyp_text
__activate_traps_nvhe(void)
62 val
= CPTR_EL2_DEFAULT
;
63 val
|= CPTR_EL2_TTA
| CPTR_EL2_TFP
| CPTR_EL2_TZ
;
64 write_sysreg(val
, cptr_el2
);
67 static hyp_alternate_select(__activate_traps_arch
,
68 __activate_traps_nvhe
, __activate_traps_vhe
,
69 ARM64_HAS_VIRT_HOST_EXTN
);
71 static void __hyp_text
__activate_traps(struct kvm_vcpu
*vcpu
)
76 * We are about to set CPTR_EL2.TFP to trap all floating point
77 * register accesses to EL2, however, the ARM ARM clearly states that
78 * traps are only taken to EL2 if the operation would not otherwise
79 * trap to EL1. Therefore, always make sure that for 32-bit guests,
80 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
81 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
82 * it will cause an exception.
84 val
= vcpu
->arch
.hcr_el2
;
86 if (!(val
& HCR_RW
) && system_supports_fpsimd()) {
87 write_sysreg(1 << 30, fpexc32_el2
);
91 if (val
& HCR_RW
) /* for AArch64 only: */
92 val
|= HCR_TID3
; /* TID3: trap feature register accesses */
94 write_sysreg(val
, hcr_el2
);
96 /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
97 write_sysreg(1 << 15, hstr_el2
);
99 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
100 * PMSELR_EL0 to make sure it never contains the cycle
101 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
102 * EL1 instead of being trapped to EL2.
104 write_sysreg(0, pmselr_el0
);
105 write_sysreg(ARMV8_PMU_USERENR_MASK
, pmuserenr_el0
);
106 write_sysreg(vcpu
->arch
.mdcr_el2
, mdcr_el2
);
107 __activate_traps_arch()();
110 static void __hyp_text
__deactivate_traps_vhe(void)
112 extern char vectors
[]; /* kernel exception vectors */
113 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
115 mdcr_el2
&= MDCR_EL2_HPMN_MASK
|
116 MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
|
119 write_sysreg(mdcr_el2
, mdcr_el2
);
120 write_sysreg(HCR_HOST_VHE_FLAGS
, hcr_el2
);
121 write_sysreg(CPACR_EL1_DEFAULT
, cpacr_el1
);
122 write_sysreg(vectors
, vbar_el1
);
125 static void __hyp_text
__deactivate_traps_nvhe(void)
127 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
129 mdcr_el2
&= MDCR_EL2_HPMN_MASK
;
130 mdcr_el2
|= MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
;
132 write_sysreg(mdcr_el2
, mdcr_el2
);
133 write_sysreg(HCR_RW
, hcr_el2
);
134 write_sysreg(CPTR_EL2_DEFAULT
, cptr_el2
);
137 static hyp_alternate_select(__deactivate_traps_arch
,
138 __deactivate_traps_nvhe
, __deactivate_traps_vhe
,
139 ARM64_HAS_VIRT_HOST_EXTN
);
141 static void __hyp_text
__deactivate_traps(struct kvm_vcpu
*vcpu
)
144 * If we pended a virtual abort, preserve it until it gets
145 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
146 * the crucial bit is "On taking a vSError interrupt,
147 * HCR_EL2.VSE is cleared to 0."
149 if (vcpu
->arch
.hcr_el2
& HCR_VSE
)
150 vcpu
->arch
.hcr_el2
= read_sysreg(hcr_el2
);
152 __deactivate_traps_arch()();
153 write_sysreg(0, hstr_el2
);
154 write_sysreg(0, pmuserenr_el0
);
157 static void __hyp_text
__activate_vm(struct kvm_vcpu
*vcpu
)
159 struct kvm
*kvm
= kern_hyp_va(vcpu
->kvm
);
160 write_sysreg(kvm
->arch
.vttbr
, vttbr_el2
);
163 static void __hyp_text
__deactivate_vm(struct kvm_vcpu
*vcpu
)
165 write_sysreg(0, vttbr_el2
);
168 static void __hyp_text
__vgic_save_state(struct kvm_vcpu
*vcpu
)
170 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
171 __vgic_v3_save_state(vcpu
);
173 __vgic_v2_save_state(vcpu
);
175 write_sysreg(read_sysreg(hcr_el2
) & ~HCR_INT_OVERRIDE
, hcr_el2
);
178 static void __hyp_text
__vgic_restore_state(struct kvm_vcpu
*vcpu
)
182 val
= read_sysreg(hcr_el2
);
183 val
|= HCR_INT_OVERRIDE
;
184 val
|= vcpu
->arch
.irq_lines
;
185 write_sysreg(val
, hcr_el2
);
187 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
188 __vgic_v3_restore_state(vcpu
);
190 __vgic_v2_restore_state(vcpu
);
193 static bool __hyp_text
__true_value(void)
198 static bool __hyp_text
__false_value(void)
203 static hyp_alternate_select(__check_arm_834220
,
204 __false_value
, __true_value
,
205 ARM64_WORKAROUND_834220
);
207 static bool __hyp_text
__translate_far_to_hpfar(u64 far
, u64
*hpfar
)
212 * Resolve the IPA the hard way using the guest VA.
214 * Stage-1 translation already validated the memory access
215 * rights. As such, we can use the EL1 translation regime, and
216 * don't have to distinguish between EL0 and EL1 access.
218 * We do need to save/restore PAR_EL1 though, as we haven't
219 * saved the guest context yet, and we may return early...
221 par
= read_sysreg(par_el1
);
222 asm volatile("at s1e1r, %0" : : "r" (far
));
225 tmp
= read_sysreg(par_el1
);
226 write_sysreg(par
, par_el1
);
228 if (unlikely(tmp
& 1))
229 return false; /* Translation failed, back to guest */
231 /* Convert PAR to HPFAR format */
232 *hpfar
= ((tmp
>> 12) & ((1UL << 36) - 1)) << 4;
236 static bool __hyp_text
__populate_fault_info(struct kvm_vcpu
*vcpu
)
238 u64 esr
= read_sysreg_el2(esr
);
239 u8 ec
= ESR_ELx_EC(esr
);
242 vcpu
->arch
.fault
.esr_el2
= esr
;
244 if (ec
!= ESR_ELx_EC_DABT_LOW
&& ec
!= ESR_ELx_EC_IABT_LOW
)
247 far
= read_sysreg_el2(far
);
250 * The HPFAR can be invalid if the stage 2 fault did not
251 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
252 * bit is clear) and one of the two following cases are true:
253 * 1. The fault was due to a permission fault
254 * 2. The processor carries errata 834220
256 * Therefore, for all non S1PTW faults where we either have a
257 * permission fault or the errata workaround is enabled, we
258 * resolve the IPA using the AT instruction.
260 if (!(esr
& ESR_ELx_S1PTW
) &&
261 (__check_arm_834220()() || (esr
& ESR_ELx_FSC_TYPE
) == FSC_PERM
)) {
262 if (!__translate_far_to_hpfar(far
, &hpfar
))
265 hpfar
= read_sysreg(hpfar_el2
);
268 vcpu
->arch
.fault
.far_el2
= far
;
269 vcpu
->arch
.fault
.hpfar_el2
= hpfar
;
273 /* Skip an instruction which has been emulated. Returns true if
274 * execution can continue or false if we need to exit hyp mode because
275 * single-step was in effect.
277 static bool __hyp_text
__skip_instr(struct kvm_vcpu
*vcpu
)
279 *vcpu_pc(vcpu
) = read_sysreg_el2(elr
);
281 if (vcpu_mode_is_32bit(vcpu
)) {
282 vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
= read_sysreg_el2(spsr
);
283 kvm_skip_instr32(vcpu
, kvm_vcpu_trap_il_is32bit(vcpu
));
284 write_sysreg_el2(vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
, spsr
);
289 write_sysreg_el2(*vcpu_pc(vcpu
), elr
);
291 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
) {
292 vcpu
->arch
.fault
.esr_el2
=
293 (ESR_ELx_EC_SOFTSTP_LOW
<< ESR_ELx_EC_SHIFT
) | 0x22;
300 int __hyp_text
__kvm_vcpu_run(struct kvm_vcpu
*vcpu
)
302 struct kvm_cpu_context
*host_ctxt
;
303 struct kvm_cpu_context
*guest_ctxt
;
307 vcpu
= kern_hyp_va(vcpu
);
308 write_sysreg(vcpu
, tpidr_el2
);
310 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
311 guest_ctxt
= &vcpu
->arch
.ctxt
;
313 __sysreg_save_host_state(host_ctxt
);
314 __debug_cond_save_host_state(vcpu
);
316 __activate_traps(vcpu
);
319 __vgic_restore_state(vcpu
);
320 __timer_enable_traps(vcpu
);
323 * We must restore the 32-bit state before the sysregs, thanks
324 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
326 __sysreg32_restore_state(vcpu
);
327 __sysreg_restore_guest_state(guest_ctxt
);
328 __debug_restore_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
330 /* Jump in the fire! */
332 exit_code
= __guest_enter(vcpu
, host_ctxt
);
333 /* And we're baaack! */
336 * We're using the raw exception code in order to only process
337 * the trap if no SError is pending. We will come back to the
338 * same PC once the SError has been injected, and replay the
339 * trapping instruction.
341 if (exit_code
== ARM_EXCEPTION_TRAP
&& !__populate_fault_info(vcpu
))
344 if (static_branch_unlikely(&vgic_v2_cpuif_trap
) &&
345 exit_code
== ARM_EXCEPTION_TRAP
) {
348 valid
= kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_DABT_LOW
&&
349 kvm_vcpu_trap_get_fault_type(vcpu
) == FSC_FAULT
&&
350 kvm_vcpu_dabt_isvalid(vcpu
) &&
351 !kvm_vcpu_dabt_isextabt(vcpu
) &&
352 !kvm_vcpu_dabt_iss1tw(vcpu
);
355 int ret
= __vgic_v2_perform_cpuif_access(vcpu
);
358 if (__skip_instr(vcpu
))
361 exit_code
= ARM_EXCEPTION_TRAP
;
365 /* Promote an illegal access to an
366 * SError. If we would be returning
367 * due to single-step clear the SS
368 * bit so handle_exit knows what to
369 * do after dealing with the error.
371 if (!__skip_instr(vcpu
))
372 *vcpu_cpsr(vcpu
) &= ~DBG_SPSR_SS
;
373 exit_code
= ARM_EXCEPTION_EL1_SERROR
;
376 /* 0 falls through to be handler out of EL2 */
380 if (static_branch_unlikely(&vgic_v3_cpuif_trap
) &&
381 exit_code
== ARM_EXCEPTION_TRAP
&&
382 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_SYS64
||
383 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_CP15_32
)) {
384 int ret
= __vgic_v3_perform_cpuif_access(vcpu
);
387 if (__skip_instr(vcpu
))
390 exit_code
= ARM_EXCEPTION_TRAP
;
393 /* 0 falls through to be handled out of EL2 */
396 fp_enabled
= __fpsimd_enabled();
398 __sysreg_save_guest_state(guest_ctxt
);
399 __sysreg32_save_state(vcpu
);
400 __timer_disable_traps(vcpu
);
401 __vgic_save_state(vcpu
);
403 __deactivate_traps(vcpu
);
404 __deactivate_vm(vcpu
);
406 __sysreg_restore_host_state(host_ctxt
);
409 __fpsimd_save_state(&guest_ctxt
->gp_regs
.fp_regs
);
410 __fpsimd_restore_state(&host_ctxt
->gp_regs
.fp_regs
);
413 __debug_save_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
415 * This must come after restoring the host sysregs, since a non-VHE
416 * system may enable SPE here and make use of the TTBRs.
418 __debug_cond_restore_host_state(vcpu
);
423 static const char __hyp_panic_string
[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
425 static void __hyp_text
__hyp_call_panic_nvhe(u64 spsr
, u64 elr
, u64 par
)
427 unsigned long str_va
;
430 * Force the panic string to be loaded from the literal pool,
431 * making sure it is a kernel address and not a PC-relative
434 asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va
));
436 __hyp_do_panic(str_va
,
438 read_sysreg(esr_el2
), read_sysreg_el2(far
),
439 read_sysreg(hpfar_el2
), par
,
440 (void *)read_sysreg(tpidr_el2
));
443 static void __hyp_text
__hyp_call_panic_vhe(u64 spsr
, u64 elr
, u64 par
)
445 panic(__hyp_panic_string
,
447 read_sysreg_el2(esr
), read_sysreg_el2(far
),
448 read_sysreg(hpfar_el2
), par
,
449 (void *)read_sysreg(tpidr_el2
));
452 static hyp_alternate_select(__hyp_call_panic
,
453 __hyp_call_panic_nvhe
, __hyp_call_panic_vhe
,
454 ARM64_HAS_VIRT_HOST_EXTN
);
456 void __hyp_text __noreturn
__hyp_panic(void)
458 u64 spsr
= read_sysreg_el2(spsr
);
459 u64 elr
= read_sysreg_el2(elr
);
460 u64 par
= read_sysreg(par_el1
);
462 if (read_sysreg(vttbr_el2
)) {
463 struct kvm_vcpu
*vcpu
;
464 struct kvm_cpu_context
*host_ctxt
;
466 vcpu
= (struct kvm_vcpu
*)read_sysreg(tpidr_el2
);
467 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
468 __timer_disable_traps(vcpu
);
469 __deactivate_traps(vcpu
);
470 __deactivate_vm(vcpu
);
471 __sysreg_restore_host_state(host_ctxt
);
474 /* Call panic for real */
475 __hyp_call_panic()(spsr
, elr
, par
);