arch/unicore32/include/mach/regs-umal.h

   1 /*
   2  * PKUnity Ultra Media Access Layer (UMAL) Ethernet MAC Registers
   3  */
   4
   5 /* MAC module of UMAL */
   6 /* UMAL's MAC module includes G/MII interface, several additional PHY
   7  * interfaces, and MAC control sub-layer, which provides support for control
   8  * frames (e.g. PAUSE frames).
   9  */
  10 /*
  11  * TX/RX reset and control UMAL_CFG1
  12  */
  13 #define UMAL_CFG1               (PKUNITY_UMAL_BASE + 0x0000)
  14 /*
  15  * MAC interface mode control UMAL_CFG2
  16  */
  17 #define UMAL_CFG2               (PKUNITY_UMAL_BASE + 0x0004)
  18 /*
  19  * Inter Packet/Frame Gap UMAL_IPGIFG
  20  */
  21 #define UMAL_IPGIFG             (PKUNITY_UMAL_BASE + 0x0008)
  22 /*
  23  * Collision retry or backoff UMAL_HALFDUPLEX
  24  */
  25 #define UMAL_HALFDUPLEX         (PKUNITY_UMAL_BASE + 0x000c)
  26 /*
  27  * Maximum Frame Length UMAL_MAXFRAME
  28  */
  29 #define UMAL_MAXFRAME           (PKUNITY_UMAL_BASE + 0x0010)
  30 /*
  31  * Test Regsiter UMAL_TESTREG
  32  */
  33 #define UMAL_TESTREG            (PKUNITY_UMAL_BASE + 0x001c)
  34 /*
  35  * MII Management Configure UMAL_MIICFG
  36  */
  37 #define UMAL_MIICFG             (PKUNITY_UMAL_BASE + 0x0020)
  38 /*
  39  * MII Management Command UMAL_MIICMD
  40  */
  41 #define UMAL_MIICMD             (PKUNITY_UMAL_BASE + 0x0024)
  42 /*
  43  * MII Management Address UMAL_MIIADDR
  44  */
  45 #define UMAL_MIIADDR            (PKUNITY_UMAL_BASE + 0x0028)
  46 /*
  47  * MII Management Control UMAL_MIICTRL
  48  */
  49 #define UMAL_MIICTRL            (PKUNITY_UMAL_BASE + 0x002c)
  50 /*
  51  * MII Management Status UMAL_MIISTATUS
  52  */
  53 #define UMAL_MIISTATUS          (PKUNITY_UMAL_BASE + 0x0030)
  54 /*
  55  * MII Management Indicator UMAL_MIIIDCT
  56  */
  57 #define UMAL_MIIIDCT            (PKUNITY_UMAL_BASE + 0x0034)
  58 /*
  59  * Interface Control UMAL_IFCTRL
  60  */
  61 #define UMAL_IFCTRL             (PKUNITY_UMAL_BASE + 0x0038)
  62 /*
  63  * Interface Status UMAL_IFSTATUS
  64  */
  65 #define UMAL_IFSTATUS           (PKUNITY_UMAL_BASE + 0x003c)
  66 /*
  67  * MAC address (high 4 bytes) UMAL_STADDR1
  68  */
  69 #define UMAL_STADDR1            (PKUNITY_UMAL_BASE + 0x0040)
  70 /*
  71  * MAC address (low 2 bytes) UMAL_STADDR2
  72  */
  73 #define UMAL_STADDR2            (PKUNITY_UMAL_BASE + 0x0044)
  74
  75 /* FIFO MODULE OF UMAL */
  76 /* UMAL's FIFO module provides data queuing for increased system level
  77  * throughput
  78  */
  79 #define UMAL_FIFOCFG0           (PKUNITY_UMAL_BASE + 0x0048)
  80 #define UMAL_FIFOCFG1           (PKUNITY_UMAL_BASE + 0x004c)
  81 #define UMAL_FIFOCFG2           (PKUNITY_UMAL_BASE + 0x0050)
  82 #define UMAL_FIFOCFG3           (PKUNITY_UMAL_BASE + 0x0054)
  83 #define UMAL_FIFOCFG4           (PKUNITY_UMAL_BASE + 0x0058)
  84 #define UMAL_FIFOCFG5           (PKUNITY_UMAL_BASE + 0x005c)
  85 #define UMAL_FIFORAM0           (PKUNITY_UMAL_BASE + 0x0060)
  86 #define UMAL_FIFORAM1           (PKUNITY_UMAL_BASE + 0x0064)
  87 #define UMAL_FIFORAM2           (PKUNITY_UMAL_BASE + 0x0068)
  88 #define UMAL_FIFORAM3           (PKUNITY_UMAL_BASE + 0x006c)
  89 #define UMAL_FIFORAM4           (PKUNITY_UMAL_BASE + 0x0070)
  90 #define UMAL_FIFORAM5           (PKUNITY_UMAL_BASE + 0x0074)
  91 #define UMAL_FIFORAM6           (PKUNITY_UMAL_BASE + 0x0078)
  92 #define UMAL_FIFORAM7           (PKUNITY_UMAL_BASE + 0x007c)
  93
  94 /* MAHBE MODULE OF UMAL */
  95 /* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master
  96  * and Slave ports.Registers within the M-AHBE provide Control and Status
  97  * information concerning these transfers.
  98  */
  99 /*
 100  * Transmit Control UMAL_DMATxCtrl
 101  */
 102 #define UMAL_DMATxCtrl          (PKUNITY_UMAL_BASE + 0x0180)
 103 /*
 104  * Pointer to TX Descripter UMAL_DMATxDescriptor
 105  */
 106 #define UMAL_DMATxDescriptor    (PKUNITY_UMAL_BASE + 0x0184)
 107 /*
 108  * Status of Tx Packet Transfers UMAL_DMATxStatus
 109  */
 110 #define UMAL_DMATxStatus        (PKUNITY_UMAL_BASE + 0x0188)
 111 /*
 112  * Receive Control UMAL_DMARxCtrl
 113  */
 114 #define UMAL_DMARxCtrl          (PKUNITY_UMAL_BASE + 0x018c)
 115 /*
 116  * Pointer to Rx Descriptor UMAL_DMARxDescriptor
 117  */
 118 #define UMAL_DMARxDescriptor    (PKUNITY_UMAL_BASE + 0x0190)
 119 /*
 120  * Status of Rx Packet Transfers UMAL_DMARxStatus
 121  */
 122 #define UMAL_DMARxStatus        (PKUNITY_UMAL_BASE + 0x0194)
 123 /*
 124  * Interrupt Mask UMAL_DMAIntrMask
 125  */
 126 #define UMAL_DMAIntrMask        (PKUNITY_UMAL_BASE + 0x0198)
 127 /*
 128  * Interrupts, read only UMAL_DMAInterrupt
 129  */
 130 #define UMAL_DMAInterrupt       (PKUNITY_UMAL_BASE + 0x019c)
 131
 132 /*
 133  * Commands for UMAL_CFG1 register
 134  */
 135 #define UMAL_CFG1_TXENABLE      FIELD(1, 1, 0)
 136 #define UMAL_CFG1_RXENABLE      FIELD(1, 1, 2)
 137 #define UMAL_CFG1_TXFLOWCTL     FIELD(1, 1, 4)
 138 #define UMAL_CFG1_RXFLOWCTL     FIELD(1, 1, 5)
 139 #define UMAL_CFG1_CONFLPBK      FIELD(1, 1, 8)
 140 #define UMAL_CFG1_RESET         FIELD(1, 1, 31)
 141 #define UMAL_CFG1_CONFFLCTL     (MAC_TX_FLOW_CTL | MAC_RX_FLOW_CTL)
 142
 143 /*
 144  * Commands for UMAL_CFG2 register
 145  */
 146 #define UMAL_CFG2_FULLDUPLEX    FIELD(1, 1, 0)
 147 #define UMAL_CFG2_CRCENABLE     FIELD(1, 1, 1)
 148 #define UMAL_CFG2_PADCRC        FIELD(1, 1, 2)
 149 #define UMAL_CFG2_LENGTHCHECK   FIELD(1, 1, 4)
 150 #define UMAL_CFG2_MODEMASK      FMASK(2, 8)
 151 #define UMAL_CFG2_NIBBLEMODE    FIELD(1, 2, 8)
 152 #define UMAL_CFG2_BYTEMODE      FIELD(2, 2, 8)
 153 #define UMAL_CFG2_PREAMBLENMASK FMASK(4, 12)
 154 #define UMAL_CFG2_DEFPREAMBLEN  FIELD(7, 4, 12)
 155 #define UMAL_CFG2_FD100         (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
 156                                 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
 157                                 | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
 158 #define UMAL_CFG2_FD1000        (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_BYTEMODE \
 159                                 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
 160                                 | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
 161 #define UMAL_CFG2_HD100         (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
 162                                 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
 163                                 | UMAL_CFG2_CRCENABLE)
 164
 165 /*
 166  * Command for UMAL_IFCTRL register
 167  */
 168 #define UMAL_IFCTRL_RESET       FIELD(1, 1, 31)
 169
 170 /*
 171  * Command for UMAL_MIICFG register
 172  */
 173 #define UMAL_MIICFG_RESET       FIELD(1, 1, 31)
 174
 175 /*
 176  * Command for UMAL_MIICMD register
 177  */
 178 #define UMAL_MIICMD_READ        FIELD(1, 1, 0)
 179
 180 /*
 181  * Command for UMAL_MIIIDCT register
 182  */
 183 #define UMAL_MIIIDCT_BUSY       FIELD(1, 1, 0)
 184 #define UMAL_MIIIDCT_NOTVALID   FIELD(1, 1, 2)
 185
 186 /*
 187  * Commands for DMATxCtrl regesters
 188  */
 189 #define UMAL_DMA_Enable         FIELD(1, 1, 0)
 190
 191 /*
 192  * Commands for DMARxCtrl regesters
 193  */
 194 #define UMAL_DMAIntrMask_ENABLEHALFWORD FIELD(1, 1, 16)
 195
 196 /*
 197  * Command for DMARxStatus
 198  */
 199 #define CLR_RX_BUS_ERR          FIELD(1, 1, 3)
 200 #define CLR_RX_OVERFLOW         FIELD(1, 1, 2)
 201 #define CLR_RX_PKT              FIELD(1, 1, 0)
 202
 203 /*
 204  * Command for DMATxStatus
 205  */
 206 #define CLR_TX_BUS_ERR          FIELD(1, 1, 3)
 207 #define CLR_TX_UNDERRUN         FIELD(1, 1, 1)
 208 #define CLR_TX_PKT              FIELD(1, 1, 0)
 209
 210 /*
 211  * Commands for DMAIntrMask and DMAInterrupt register
 212  */
 213 #define INT_RX_MASK             FIELD(0xd, 4, 4)
 214 #define INT_TX_MASK             FIELD(0xb, 4, 0)
 215
 216 #define INT_RX_BUS_ERR          FIELD(1, 1, 7)
 217 #define INT_RX_OVERFLOW         FIELD(1, 1, 6)
 218 #define INT_RX_PKT              FIELD(1, 1, 4)
 219 #define INT_TX_BUS_ERR          FIELD(1, 1, 3)
 220 #define INT_TX_UNDERRUN         FIELD(1, 1, 1)
 221 #define INT_TX_PKT              FIELD(1, 1, 0)
 222
 223 /*
 224  * MARCOS of UMAL's descriptors
 225  */
 226 #define UMAL_DESC_PACKETSIZE_EMPTY      FIELD(1, 1, 31)
 227 #define UMAL_DESC_PACKETSIZE_NONEMPTY   FIELD(0, 1, 31)
 228 #define UMAL_DESC_PACKETSIZE_SIZEMASK   FMASK(12, 0)
 229