arch/x86/include/asm/io.h

   1 #ifndef _ASM_X86_IO_H
   2 #define _ASM_X86_IO_H
   3
   4 /*
   5  * This file contains the definitions for the x86 IO instructions
   6  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   7  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   8  * versions of the single-IO instructions (inb_p/inw_p/..).
   9  *
  10  * This file is not meant to be obfuscating: it's just complicated
  11  * to (a) handle it all in a way that makes gcc able to optimize it
  12  * as well as possible and (b) trying to avoid writing the same thing
  13  * over and over again with slight variations and possibly making a
  14  * mistake somewhere.
  15  */
  16
  17 /*
  18  * Thanks to James van Artsdalen for a better timing-fix than
  19  * the two short jumps: using outb's to a nonexistent port seems
  20  * to guarantee better timings even on fast machines.
  21  *
  22  * On the other hand, I'd like to be sure of a non-existent port:
  23  * I feel a bit unsafe about using 0x80 (should be safe, though)
  24  *
  25  *              Linus
  26  */
  27
  28  /*
  29   *  Bit simplified and optimized by Jan Hubicka
  30   *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
  31   *
  32   *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
  33   *  isa_read[wl] and isa_write[wl] fixed
  34   *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  35   */
  36
  37 #define ARCH_HAS_IOREMAP_WC
  38
  39 #include <linux/string.h>
  40 #include <linux/compiler.h>
  41 #include <asm/page.h>
  42 #include <asm/early_ioremap.h>
  43
  44 #define build_mmio_read(name, size, type, reg, barrier) \
  45 static inline type name(const volatile void __iomem *addr) \
  46 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
  47 :"m" (*(volatile type __force *)addr) barrier); return ret; }
  48
  49 #define build_mmio_write(name, size, type, reg, barrier) \
  50 static inline void name(type val, volatile void __iomem *addr) \
  51 { asm volatile("mov" size " %0,%1": :reg (val), \
  52 "m" (*(volatile type __force *)addr) barrier); }
  53
  54 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
  55 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
  56 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
  57
  58 build_mmio_read(__readb, "b", unsigned char, "=q", )
  59 build_mmio_read(__readw, "w", unsigned short, "=r", )
  60 build_mmio_read(__readl, "l", unsigned int, "=r", )
  61
  62 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
  63 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
  64 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
  65
  66 build_mmio_write(__writeb, "b", unsigned char, "q", )
  67 build_mmio_write(__writew, "w", unsigned short, "r", )
  68 build_mmio_write(__writel, "l", unsigned int, "r", )
  69
  70 #define readb_relaxed(a) __readb(a)
  71 #define readw_relaxed(a) __readw(a)
  72 #define readl_relaxed(a) __readl(a)
  73 #define __raw_readb __readb
  74 #define __raw_readw __readw
  75 #define __raw_readl __readl
  76
  77 #define __raw_writeb __writeb
  78 #define __raw_writew __writew
  79 #define __raw_writel __writel
  80
  81 #define mmiowb() barrier()
  82
  83 #ifdef CONFIG_X86_64
  84
  85 build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
  86 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
  87
  88 #define readq_relaxed(a)        readq(a)
  89
  90 #define __raw_readq(a)          readq(a)
  91 #define __raw_writeq(val, addr) writeq(val, addr)
  92
  93 /* Let people know that we have them */
  94 #define readq                   readq
  95 #define writeq                  writeq
  96
  97 #endif
  98
  99 /**
 100  *      virt_to_phys    -       map virtual addresses to physical
 101  *      @address: address to remap
 102  *
 103  *      The returned physical address is the physical (CPU) mapping for
 104  *      the memory address given. It is only valid to use this function on
 105  *      addresses directly mapped or allocated via kmalloc.
 106  *
 107  *      This function does not give bus mappings for DMA transfers. In
 108  *      almost all conceivable cases a device driver should not be using
 109  *      this function
 110  */
 111
 112 static inline phys_addr_t virt_to_phys(volatile void *address)
 113 {
 114         return __pa(address);
 115 }
 116
 117 /**
 118  *      phys_to_virt    -       map physical address to virtual
 119  *      @address: address to remap
 120  *
 121  *      The returned virtual address is a current CPU mapping for
 122  *      the memory address given. It is only valid to use this function on
 123  *      addresses that have a kernel mapping
 124  *
 125  *      This function does not handle bus mappings for DMA transfers. In
 126  *      almost all conceivable cases a device driver should not be using
 127  *      this function
 128  */
 129
 130 static inline void *phys_to_virt(phys_addr_t address)
 131 {
 132         return __va(address);
 133 }
 134
 135 /*
 136  * Change "struct page" to physical address.
 137  */
 138 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 139
 140 /*
 141  * ISA I/O bus memory addresses are 1:1 with the physical address.
 142  * However, we truncate the address to unsigned int to avoid undesirable
 143  * promitions in legacy drivers.
 144  */
 145 static inline unsigned int isa_virt_to_bus(volatile void *address)
 146 {
 147         return (unsigned int)virt_to_phys(address);
 148 }
 149 #define isa_page_to_bus(page)   ((unsigned int)page_to_phys(page))
 150 #define isa_bus_to_virt         phys_to_virt
 151
 152 /*
 153  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 154  * are forbidden in portable PCI drivers.
 155  *
 156  * Allow them on x86 for legacy drivers, though.
 157  */
 158 #define virt_to_bus virt_to_phys
 159 #define bus_to_virt phys_to_virt
 160
 161 /**
 162  * ioremap     -   map bus memory into CPU space
 163  * @offset:    bus address of the memory
 164  * @size:      size of the resource to map
 165  *
 166  * ioremap performs a platform specific sequence of operations to
 167  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 168  * writew/writel functions and the other mmio helpers. The returned
 169  * address is not guaranteed to be usable directly as a virtual
 170  * address.
 171  *
 172  * If the area you are trying to map is a PCI BAR you should have a
 173  * look at pci_iomap().
 174  */
 175 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
 176 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
 177 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
 178                                 unsigned long prot_val);
 179
 180 /*
 181  * The default ioremap() behavior is non-cached:
 182  */
 183 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
 184 {
 185         return ioremap_nocache(offset, size);
 186 }
 187
 188 extern void iounmap(volatile void __iomem *addr);
 189
 190 extern void set_iounmap_nonlazy(void);
 191
 192 #ifdef __KERNEL__
 193
 194 #include <asm-generic/iomap.h>
 195
 196 #include <linux/vmalloc.h>
 197
 198 /*
 199  * Convert a virtual cached pointer to an uncached pointer
 200  */
 201 #define xlate_dev_kmem_ptr(p)   p
 202
 203 static inline void
 204 memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
 205 {
 206         memset((void __force *)addr, val, count);
 207 }
 208
 209 static inline void
 210 memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
 211 {
 212         memcpy(dst, (const void __force *)src, count);
 213 }
 214
 215 static inline void
 216 memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
 217 {
 218         memcpy((void __force *)dst, src, count);
 219 }
 220
 221 /*
 222  * ISA space is 'always mapped' on a typical x86 system, no need to
 223  * explicitly ioremap() it. The fact that the ISA IO space is mapped
 224  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 225  * are physical addresses. The following constant pointer can be
 226  * used as the IO-area pointer (it can be iounmapped as well, so the
 227  * analogy with PCI is quite large):
 228  */
 229 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
 230
 231 /*
 232  *      Cache management
 233  *
 234  *      This needed for two cases
 235  *      1. Out of order aware processors
 236  *      2. Accidentally out of order processors (PPro errata #51)
 237  */
 238
 239 static inline void flush_write_buffers(void)
 240 {
 241 #if defined(CONFIG_X86_PPRO_FENCE)
 242         asm volatile("lock; addl $0,0(%%esp)": : :"memory");
 243 #endif
 244 }
 245
 246 #endif /* __KERNEL__ */
 247
 248 extern void native_io_delay(void);
 249
 250 extern int io_delay_type;
 251 extern void io_delay_init(void);
 252
 253 #if defined(CONFIG_PARAVIRT)
 254 #include <asm/paravirt.h>
 255 #else
 256
 257 static inline void slow_down_io(void)
 258 {
 259         native_io_delay();
 260 #ifdef REALLY_SLOW_IO
 261         native_io_delay();
 262         native_io_delay();
 263         native_io_delay();
 264 #endif
 265 }
 266
 267 #endif
 268
 269 #define BUILDIO(bwl, bw, type)                                          \
 270 static inline void out##bwl(unsigned type value, int port)              \
 271 {                                                                       \
 272         asm volatile("out" #bwl " %" #bw "0, %w1"                       \
 273                      : : "a"(value), "Nd"(port));                       \
 274 }                                                                       \
 275                                                                         \
 276 static inline unsigned type in##bwl(int port)                           \
 277 {                                                                       \
 278         unsigned type value;                                            \
 279         asm volatile("in" #bwl " %w1, %" #bw "0"                        \
 280                      : "=a"(value) : "Nd"(port));                       \
 281         return value;                                                   \
 282 }                                                                       \
 283                                                                         \
 284 static inline void out##bwl##_p(unsigned type value, int port)          \
 285 {                                                                       \
 286         out##bwl(value, port);                                          \
 287         slow_down_io();                                                 \
 288 }                                                                       \
 289                                                                         \
 290 static inline unsigned type in##bwl##_p(int port)                       \
 291 {                                                                       \
 292         unsigned type value = in##bwl(port);                            \
 293         slow_down_io();                                                 \
 294         return value;                                                   \
 295 }                                                                       \
 296                                                                         \
 297 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
 298 {                                                                       \
 299         asm volatile("rep; outs" #bwl                                   \
 300                      : "+S"(addr), "+c"(count) : "d"(port));            \
 301 }                                                                       \
 302                                                                         \
 303 static inline void ins##bwl(int port, void *addr, unsigned long count)  \
 304 {                                                                       \
 305         asm volatile("rep; ins" #bwl                                    \
 306                      : "+D"(addr), "+c"(count) : "d"(port));            \
 307 }
 308
 309 BUILDIO(b, b, char)
 310 BUILDIO(w, w, short)
 311 BUILDIO(l, , int)
 312
 313 extern void *xlate_dev_mem_ptr(unsigned long phys);
 314 extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
 315
 316 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
 317                                 unsigned long prot_val);
 318 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
 319
 320 extern bool is_early_ioremap_ptep(pte_t *ptep);
 321
 322 #ifdef CONFIG_XEN
 323 #include <xen/xen.h>
 324 struct bio_vec;
 325
 326 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 327                                       const struct bio_vec *vec2);
 328
 329 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 330         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 331          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 332 #endif  /* CONFIG_XEN */
 333
 334 #define IO_SPACE_LIMIT 0xffff
 335
 336 #ifdef CONFIG_MTRR
 337 extern int __must_check arch_phys_wc_add(unsigned long base,
 338                                          unsigned long size);
 339 extern void arch_phys_wc_del(int handle);
 340 #define arch_phys_wc_add arch_phys_wc_add
 341 #endif
 342
 343 #endif /* _ASM_X86_IO_H */