1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
34 static void __init
spectre_v2_select_mitigation(void);
35 static void __init
ssb_select_mitigation(void);
36 static void __init
l1tf_select_mitigation(void);
38 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
39 u64 x86_spec_ctrl_base
;
40 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
41 static DEFINE_MUTEX(spec_ctrl_mutex
);
44 * The vendor and possibly platform specific bits which can be modified in
47 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
50 * AMD specific MSR info for Speculative Store Bypass control.
51 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
53 u64 __ro_after_init x86_amd_ls_cfg_base
;
54 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
56 /* Control conditional STIPB in switch_to() */
57 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
58 /* Control conditional IBPB in switch_mm() */
59 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
60 /* Control unconditional IBPB in switch_mm() */
61 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
63 void __init
check_bugs(void)
68 * identify_boot_cpu() initialized SMT support information, let the
71 cpu_smt_check_topology_early();
73 if (!IS_ENABLED(CONFIG_SMP
)) {
75 print_cpu_info(&boot_cpu_data
);
79 * Read the SPEC_CTRL MSR to account for reserved bits which may
80 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
81 * init code as it is not enumerated and depends on the family.
83 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
84 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
86 /* Allow STIBP in MSR_SPEC_CTRL if supported */
87 if (boot_cpu_has(X86_FEATURE_STIBP
))
88 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
90 /* Select the proper spectre mitigation before patching alternatives */
91 spectre_v2_select_mitigation();
94 * Select proper mitigation for any exposure to the Speculative Store
95 * Bypass vulnerability.
97 ssb_select_mitigation();
99 l1tf_select_mitigation();
103 * Check whether we are able to run this kernel safely on SMP.
105 * - i386 is no longer supported.
106 * - In order to run on anything without a TSC, we need to be
107 * compiled for a i486.
109 if (boot_cpu_data
.x86
< 4)
110 panic("Kernel requires i486+ for 'invlpg' and other features");
112 init_utsname()->machine
[1] =
113 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
114 alternative_instructions();
116 fpu__init_check_bugs();
117 #else /* CONFIG_X86_64 */
118 alternative_instructions();
121 * Make sure the first 2MB area is not mapped by huge pages
122 * There are typically fixed size MTRRs in there and overlapping
123 * MTRRs into large pages causes slow downs.
125 * Right now we don't do that with gbpages because there seems
126 * very little benefit for that case.
129 set_memory_4k((unsigned long)__va(0), 1);
134 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
136 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
137 struct thread_info
*ti
= current_thread_info();
139 /* Is MSR_SPEC_CTRL implemented ? */
140 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
142 * Restrict guest_spec_ctrl to supported values. Clear the
143 * modifiable bits in the host base value and or the
144 * modifiable bits from the guest value.
146 guestval
= hostval
& ~x86_spec_ctrl_mask
;
147 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
149 /* SSBD controlled in MSR_SPEC_CTRL */
150 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
151 static_cpu_has(X86_FEATURE_AMD_SSBD
))
152 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
154 /* Conditional STIBP enabled? */
155 if (static_branch_unlikely(&switch_to_cond_stibp
))
156 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
158 if (hostval
!= guestval
) {
159 msrval
= setguest
? guestval
: hostval
;
160 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
165 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
166 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
168 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
169 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
173 * If the host has SSBD mitigation enabled, force it in the host's
174 * virtual MSR value. If its not permanently enabled, evaluate
175 * current's TIF_SSBD thread flag.
177 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
178 hostval
= SPEC_CTRL_SSBD
;
180 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
182 /* Sanitize the guest value */
183 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
185 if (hostval
!= guestval
) {
188 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
189 ssbd_spec_ctrl_to_tif(hostval
);
191 speculation_ctrl_update(tif
);
194 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
196 static void x86_amd_ssb_disable(void)
198 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
200 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
201 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
202 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
203 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
207 #define pr_fmt(fmt) "Spectre V2 : " fmt
209 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
212 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
213 SPECTRE_V2_USER_NONE
;
216 static bool spectre_v2_bad_module
;
218 bool retpoline_module_ok(bool has_retpoline
)
220 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
223 pr_err("System may be vulnerable to spectre v2\n");
224 spectre_v2_bad_module
= true;
228 static inline const char *spectre_v2_module_string(void)
230 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
233 static inline const char *spectre_v2_module_string(void) { return ""; }
236 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
238 int len
= strlen(opt
);
240 return len
== arglen
&& !strncmp(arg
, opt
, len
);
243 /* The kernel command line selection for spectre v2 */
244 enum spectre_v2_mitigation_cmd
{
247 SPECTRE_V2_CMD_FORCE
,
248 SPECTRE_V2_CMD_RETPOLINE
,
249 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
250 SPECTRE_V2_CMD_RETPOLINE_AMD
,
253 enum spectre_v2_user_cmd
{
254 SPECTRE_V2_USER_CMD_NONE
,
255 SPECTRE_V2_USER_CMD_AUTO
,
256 SPECTRE_V2_USER_CMD_FORCE
,
259 static const char * const spectre_v2_user_strings
[] = {
260 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
261 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
264 static const struct {
266 enum spectre_v2_user_cmd cmd
;
268 } v2_user_options
[] __initdata
= {
269 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
270 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
271 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
274 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
276 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
277 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
280 static enum spectre_v2_user_cmd __init
281 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
287 case SPECTRE_V2_CMD_NONE
:
288 return SPECTRE_V2_USER_CMD_NONE
;
289 case SPECTRE_V2_CMD_FORCE
:
290 return SPECTRE_V2_USER_CMD_FORCE
;
295 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
298 return SPECTRE_V2_USER_CMD_AUTO
;
300 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
301 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
302 spec_v2_user_print_cond(v2_user_options
[i
].option
,
303 v2_user_options
[i
].secure
);
304 return v2_user_options
[i
].cmd
;
308 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
309 return SPECTRE_V2_USER_CMD_AUTO
;
313 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
315 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
316 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
318 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
321 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
322 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
323 smt_possible
= false;
325 switch (spectre_v2_parse_user_cmdline(v2_cmd
)) {
326 case SPECTRE_V2_USER_CMD_AUTO
:
327 case SPECTRE_V2_USER_CMD_NONE
:
329 case SPECTRE_V2_USER_CMD_FORCE
:
330 mode
= SPECTRE_V2_USER_STRICT
;
334 /* Initialize Indirect Branch Prediction Barrier */
335 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
336 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
339 case SPECTRE_V2_USER_STRICT
:
340 static_branch_enable(&switch_mm_always_ibpb
);
346 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
347 mode
== SPECTRE_V2_USER_STRICT
? "always-on" : "conditional");
350 /* If enhanced IBRS is enabled no STIPB required */
351 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
355 spectre_v2_user
= mode
;
356 /* Only print the STIBP mode when SMT possible */
358 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
361 static const char * const spectre_v2_strings
[] = {
362 [SPECTRE_V2_NONE
] = "Vulnerable",
363 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
364 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
365 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
368 static const struct {
370 enum spectre_v2_mitigation_cmd cmd
;
372 } mitigation_options
[] __initdata
= {
373 { "off", SPECTRE_V2_CMD_NONE
, false },
374 { "on", SPECTRE_V2_CMD_FORCE
, true },
375 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
376 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
377 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
378 { "auto", SPECTRE_V2_CMD_AUTO
, false },
381 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
383 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
384 pr_info("%s selected on command line.\n", reason
);
387 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
389 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
393 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
394 return SPECTRE_V2_CMD_NONE
;
396 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
398 return SPECTRE_V2_CMD_AUTO
;
400 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
401 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
403 cmd
= mitigation_options
[i
].cmd
;
407 if (i
>= ARRAY_SIZE(mitigation_options
)) {
408 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
409 return SPECTRE_V2_CMD_AUTO
;
412 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
413 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
414 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
415 !IS_ENABLED(CONFIG_RETPOLINE
)) {
416 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
417 return SPECTRE_V2_CMD_AUTO
;
420 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
421 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
422 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
423 return SPECTRE_V2_CMD_AUTO
;
426 spec_v2_print_cond(mitigation_options
[i
].option
,
427 mitigation_options
[i
].secure
);
431 static void __init
spectre_v2_select_mitigation(void)
433 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
434 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
437 * If the CPU is not affected and the command line mode is NONE or AUTO
438 * then nothing to do.
440 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
441 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
445 case SPECTRE_V2_CMD_NONE
:
448 case SPECTRE_V2_CMD_FORCE
:
449 case SPECTRE_V2_CMD_AUTO
:
450 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
451 mode
= SPECTRE_V2_IBRS_ENHANCED
;
452 /* Force it so VMEXIT will restore correctly */
453 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
454 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
455 goto specv2_set_mode
;
457 if (IS_ENABLED(CONFIG_RETPOLINE
))
460 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
461 if (IS_ENABLED(CONFIG_RETPOLINE
))
464 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
465 if (IS_ENABLED(CONFIG_RETPOLINE
))
466 goto retpoline_generic
;
468 case SPECTRE_V2_CMD_RETPOLINE
:
469 if (IS_ENABLED(CONFIG_RETPOLINE
))
473 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
477 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
479 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
480 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
481 goto retpoline_generic
;
483 mode
= SPECTRE_V2_RETPOLINE_AMD
;
484 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
485 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
488 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
489 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
493 spectre_v2_enabled
= mode
;
494 pr_info("%s\n", spectre_v2_strings
[mode
]);
497 * If spectre v2 protection has been enabled, unconditionally fill
498 * RSB during a context switch; this protects against two independent
501 * - RSB underflow (and switch to BTB) on Skylake+
502 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
504 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
505 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
508 * Retpoline means the kernel is safe because it has no indirect
509 * branches. Enhanced IBRS protects firmware too, so, enable restricted
510 * speculation around firmware calls only when Enhanced IBRS isn't
513 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
514 * the user might select retpoline on the kernel command line and if
515 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
516 * enable IBRS around firmware calls.
518 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
519 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
520 pr_info("Enabling Restricted Speculation for firmware calls\n");
523 /* Set up IBPB and STIBP depending on the general spectre V2 command */
524 spectre_v2_user_select_mitigation(cmd
);
526 /* Enable STIBP if appropriate */
530 static bool stibp_needed(void)
532 /* Enhanced IBRS makes using STIBP unnecessary. */
533 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
536 /* Check for strict user mitigation mode */
537 return spectre_v2_user
== SPECTRE_V2_USER_STRICT
;
540 static void update_stibp_msr(void *info
)
542 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
545 void arch_smt_update(void)
552 mutex_lock(&spec_ctrl_mutex
);
554 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
555 if (sched_smt_active())
556 mask
|= SPEC_CTRL_STIBP
;
558 if (mask
!= x86_spec_ctrl_base
) {
559 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
560 mask
& SPEC_CTRL_STIBP
? "Enabling" : "Disabling");
561 x86_spec_ctrl_base
= mask
;
562 on_each_cpu(update_stibp_msr
, NULL
, 1);
564 mutex_unlock(&spec_ctrl_mutex
);
568 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
570 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
572 /* The kernel command line selection */
573 enum ssb_mitigation_cmd
{
574 SPEC_STORE_BYPASS_CMD_NONE
,
575 SPEC_STORE_BYPASS_CMD_AUTO
,
576 SPEC_STORE_BYPASS_CMD_ON
,
577 SPEC_STORE_BYPASS_CMD_PRCTL
,
578 SPEC_STORE_BYPASS_CMD_SECCOMP
,
581 static const char * const ssb_strings
[] = {
582 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
583 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
584 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
585 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
588 static const struct {
590 enum ssb_mitigation_cmd cmd
;
591 } ssb_mitigation_options
[] __initdata
= {
592 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
593 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
594 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
595 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
596 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
599 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
601 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
605 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
606 return SPEC_STORE_BYPASS_CMD_NONE
;
608 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
611 return SPEC_STORE_BYPASS_CMD_AUTO
;
613 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
614 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
617 cmd
= ssb_mitigation_options
[i
].cmd
;
621 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
622 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
623 return SPEC_STORE_BYPASS_CMD_AUTO
;
630 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
632 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
633 enum ssb_mitigation_cmd cmd
;
635 if (!boot_cpu_has(X86_FEATURE_SSBD
))
638 cmd
= ssb_parse_cmdline();
639 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
640 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
641 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
645 case SPEC_STORE_BYPASS_CMD_AUTO
:
646 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
648 * Choose prctl+seccomp as the default mode if seccomp is
651 if (IS_ENABLED(CONFIG_SECCOMP
))
652 mode
= SPEC_STORE_BYPASS_SECCOMP
;
654 mode
= SPEC_STORE_BYPASS_PRCTL
;
656 case SPEC_STORE_BYPASS_CMD_ON
:
657 mode
= SPEC_STORE_BYPASS_DISABLE
;
659 case SPEC_STORE_BYPASS_CMD_PRCTL
:
660 mode
= SPEC_STORE_BYPASS_PRCTL
;
662 case SPEC_STORE_BYPASS_CMD_NONE
:
667 * We have three CPU feature flags that are in play here:
668 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
669 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
670 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
672 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
673 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
675 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
676 * use a completely different MSR and bit dependent on family.
678 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
679 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
680 x86_amd_ssb_disable();
682 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
683 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
684 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
691 static void ssb_select_mitigation(void)
693 ssb_mode
= __ssb_select_mitigation();
695 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
696 pr_info("%s\n", ssb_strings
[ssb_mode
]);
700 #define pr_fmt(fmt) "Speculation prctl: " fmt
702 static void task_update_spec_tif(struct task_struct
*tsk
, int tifbit
, bool on
)
707 update
= !test_and_set_tsk_thread_flag(tsk
, tifbit
);
709 update
= test_and_clear_tsk_thread_flag(tsk
, tifbit
);
712 * Immediately update the speculation control MSRs for the current
713 * task, but for a non-current task delay setting the CPU
714 * mitigation until it is scheduled next.
716 * This can only happen for SECCOMP mitigation. For PRCTL it's
717 * always the current task.
719 if (tsk
== current
&& update
)
720 speculation_ctrl_update_current();
723 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
725 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
726 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
731 /* If speculation is force disabled, enable is not allowed */
732 if (task_spec_ssb_force_disable(task
))
734 task_clear_spec_ssb_disable(task
);
735 task_update_spec_tif(task
, TIF_SSBD
, false);
737 case PR_SPEC_DISABLE
:
738 task_set_spec_ssb_disable(task
);
739 task_update_spec_tif(task
, TIF_SSBD
, true);
741 case PR_SPEC_FORCE_DISABLE
:
742 task_set_spec_ssb_disable(task
);
743 task_set_spec_ssb_force_disable(task
);
744 task_update_spec_tif(task
, TIF_SSBD
, true);
752 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
756 case PR_SPEC_STORE_BYPASS
:
757 return ssb_prctl_set(task
, ctrl
);
763 #ifdef CONFIG_SECCOMP
764 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
766 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
767 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
771 static int ssb_prctl_get(struct task_struct
*task
)
774 case SPEC_STORE_BYPASS_DISABLE
:
775 return PR_SPEC_DISABLE
;
776 case SPEC_STORE_BYPASS_SECCOMP
:
777 case SPEC_STORE_BYPASS_PRCTL
:
778 if (task_spec_ssb_force_disable(task
))
779 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
780 if (task_spec_ssb_disable(task
))
781 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
782 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
784 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
785 return PR_SPEC_ENABLE
;
786 return PR_SPEC_NOT_AFFECTED
;
790 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
793 case PR_SPEC_STORE_BYPASS
:
794 return ssb_prctl_get(task
);
800 void x86_spec_ctrl_setup_ap(void)
802 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
803 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
805 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
806 x86_amd_ssb_disable();
810 #define pr_fmt(fmt) "L1TF: " fmt
812 /* Default mitigation for L1TF-affected CPUs */
813 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
814 #if IS_ENABLED(CONFIG_KVM_INTEL)
815 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
817 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
818 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
822 * These CPUs all support 44bits physical address space internally in the
823 * cache but CPUID can report a smaller number of physical address bits.
825 * The L1TF mitigation uses the top most address bit for the inversion of
826 * non present PTEs. When the installed memory reaches into the top most
827 * address bit due to memory holes, which has been observed on machines
828 * which report 36bits physical address bits and have 32G RAM installed,
829 * then the mitigation range check in l1tf_select_mitigation() triggers.
830 * This is a false positive because the mitigation is still possible due to
831 * the fact that the cache uses 44bit internally. Use the cache bits
832 * instead of the reported physical bits and adjust them on the affected
833 * machines to 44bit if the reported bits are less than 44.
835 static void override_cache_bits(struct cpuinfo_x86
*c
)
840 switch (c
->x86_model
) {
841 case INTEL_FAM6_NEHALEM
:
842 case INTEL_FAM6_WESTMERE
:
843 case INTEL_FAM6_SANDYBRIDGE
:
844 case INTEL_FAM6_IVYBRIDGE
:
845 case INTEL_FAM6_HASWELL_CORE
:
846 case INTEL_FAM6_HASWELL_ULT
:
847 case INTEL_FAM6_HASWELL_GT3E
:
848 case INTEL_FAM6_BROADWELL_CORE
:
849 case INTEL_FAM6_BROADWELL_GT3E
:
850 case INTEL_FAM6_SKYLAKE_MOBILE
:
851 case INTEL_FAM6_SKYLAKE_DESKTOP
:
852 case INTEL_FAM6_KABYLAKE_MOBILE
:
853 case INTEL_FAM6_KABYLAKE_DESKTOP
:
854 if (c
->x86_cache_bits
< 44)
855 c
->x86_cache_bits
= 44;
860 static void __init
l1tf_select_mitigation(void)
864 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
867 override_cache_bits(&boot_cpu_data
);
869 switch (l1tf_mitigation
) {
870 case L1TF_MITIGATION_OFF
:
871 case L1TF_MITIGATION_FLUSH_NOWARN
:
872 case L1TF_MITIGATION_FLUSH
:
874 case L1TF_MITIGATION_FLUSH_NOSMT
:
875 case L1TF_MITIGATION_FULL
:
876 cpu_smt_disable(false);
878 case L1TF_MITIGATION_FULL_FORCE
:
879 cpu_smt_disable(true);
883 #if CONFIG_PGTABLE_LEVELS == 2
884 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
888 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
889 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
890 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
894 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
897 static int __init
l1tf_cmdline(char *str
)
899 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
905 if (!strcmp(str
, "off"))
906 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
907 else if (!strcmp(str
, "flush,nowarn"))
908 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
909 else if (!strcmp(str
, "flush"))
910 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
911 else if (!strcmp(str
, "flush,nosmt"))
912 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
913 else if (!strcmp(str
, "full"))
914 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
915 else if (!strcmp(str
, "full,force"))
916 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
920 early_param("l1tf", l1tf_cmdline
);
926 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
928 #if IS_ENABLED(CONFIG_KVM_INTEL)
929 static const char * const l1tf_vmx_states
[] = {
930 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
931 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
932 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
933 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
934 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
935 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
938 static ssize_t
l1tf_show_state(char *buf
)
940 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
941 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
943 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
944 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
945 sched_smt_active())) {
946 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
947 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
950 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
951 l1tf_vmx_states
[l1tf_vmx_mitigation
],
952 sched_smt_active() ? "vulnerable" : "disabled");
955 static ssize_t
l1tf_show_state(char *buf
)
957 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
961 static char *stibp_state(void)
963 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
966 switch (spectre_v2_user
) {
967 case SPECTRE_V2_USER_NONE
:
968 return ", STIBP: disabled";
969 case SPECTRE_V2_USER_STRICT
:
970 return ", STIBP: forced";
975 static char *ibpb_state(void)
977 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
978 switch (spectre_v2_user
) {
979 case SPECTRE_V2_USER_NONE
:
980 return ", IBPB: disabled";
981 case SPECTRE_V2_USER_STRICT
:
982 return ", IBPB: always-on";
988 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
989 char *buf
, unsigned int bug
)
991 if (!boot_cpu_has_bug(bug
))
992 return sprintf(buf
, "Not affected\n");
995 case X86_BUG_CPU_MELTDOWN
:
996 if (boot_cpu_has(X86_FEATURE_PTI
))
997 return sprintf(buf
, "Mitigation: PTI\n");
1001 case X86_BUG_SPECTRE_V1
:
1002 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
1004 case X86_BUG_SPECTRE_V2
:
1005 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
1007 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1009 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1010 spectre_v2_module_string());
1012 case X86_BUG_SPEC_STORE_BYPASS
:
1013 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1016 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1017 return l1tf_show_state(buf
);
1023 return sprintf(buf
, "Vulnerable\n");
1026 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1028 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1031 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1033 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1036 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1038 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1041 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1043 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1046 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1048 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);