1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
37 static void __init
spectre_v1_select_mitigation(void);
38 static void __init
spectre_v2_select_mitigation(void);
39 static void __init
ssb_select_mitigation(void);
40 static void __init
l1tf_select_mitigation(void);
41 static void __init
mds_select_mitigation(void);
42 static void __init
mds_print_mitigation(void);
43 static void __init
taa_select_mitigation(void);
45 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
46 u64 x86_spec_ctrl_base
;
47 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
48 static DEFINE_MUTEX(spec_ctrl_mutex
);
51 * The vendor and possibly platform specific bits which can be modified in
54 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
57 * AMD specific MSR info for Speculative Store Bypass control.
58 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
60 u64 __ro_after_init x86_amd_ls_cfg_base
;
61 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
63 /* Control conditional STIBP in switch_to() */
64 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
65 /* Control conditional IBPB in switch_mm() */
66 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
67 /* Control unconditional IBPB in switch_mm() */
68 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
70 /* Control MDS CPU buffer clear before returning to user space */
71 DEFINE_STATIC_KEY_FALSE(mds_user_clear
);
72 EXPORT_SYMBOL_GPL(mds_user_clear
);
73 /* Control MDS CPU buffer clear before idling (halt, mwait) */
74 DEFINE_STATIC_KEY_FALSE(mds_idle_clear
);
75 EXPORT_SYMBOL_GPL(mds_idle_clear
);
77 void __init
check_bugs(void)
82 * identify_boot_cpu() initialized SMT support information, let the
85 cpu_smt_check_topology();
87 if (!IS_ENABLED(CONFIG_SMP
)) {
89 print_cpu_info(&boot_cpu_data
);
93 * Read the SPEC_CTRL MSR to account for reserved bits which may
94 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
95 * init code as it is not enumerated and depends on the family.
97 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
98 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
100 /* Allow STIBP in MSR_SPEC_CTRL if supported */
101 if (boot_cpu_has(X86_FEATURE_STIBP
))
102 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
104 /* Select the proper CPU mitigations before patching alternatives: */
105 spectre_v1_select_mitigation();
106 spectre_v2_select_mitigation();
107 ssb_select_mitigation();
108 l1tf_select_mitigation();
109 mds_select_mitigation();
110 taa_select_mitigation();
113 * As MDS and TAA mitigations are inter-related, print MDS
114 * mitigation until after TAA mitigation selection is done.
116 mds_print_mitigation();
122 * Check whether we are able to run this kernel safely on SMP.
124 * - i386 is no longer supported.
125 * - In order to run on anything without a TSC, we need to be
126 * compiled for a i486.
128 if (boot_cpu_data
.x86
< 4)
129 panic("Kernel requires i486+ for 'invlpg' and other features");
131 init_utsname()->machine
[1] =
132 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
133 alternative_instructions();
135 fpu__init_check_bugs();
136 #else /* CONFIG_X86_64 */
137 alternative_instructions();
140 * Make sure the first 2MB area is not mapped by huge pages
141 * There are typically fixed size MTRRs in there and overlapping
142 * MTRRs into large pages causes slow downs.
144 * Right now we don't do that with gbpages because there seems
145 * very little benefit for that case.
148 set_memory_4k((unsigned long)__va(0), 1);
153 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
155 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
156 struct thread_info
*ti
= current_thread_info();
158 /* Is MSR_SPEC_CTRL implemented ? */
159 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
161 * Restrict guest_spec_ctrl to supported values. Clear the
162 * modifiable bits in the host base value and or the
163 * modifiable bits from the guest value.
165 guestval
= hostval
& ~x86_spec_ctrl_mask
;
166 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
168 /* SSBD controlled in MSR_SPEC_CTRL */
169 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
170 static_cpu_has(X86_FEATURE_AMD_SSBD
))
171 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
173 /* Conditional STIBP enabled? */
174 if (static_branch_unlikely(&switch_to_cond_stibp
))
175 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
177 if (hostval
!= guestval
) {
178 msrval
= setguest
? guestval
: hostval
;
179 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
184 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
185 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
187 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
188 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
192 * If the host has SSBD mitigation enabled, force it in the host's
193 * virtual MSR value. If its not permanently enabled, evaluate
194 * current's TIF_SSBD thread flag.
196 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
197 hostval
= SPEC_CTRL_SSBD
;
199 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
201 /* Sanitize the guest value */
202 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
204 if (hostval
!= guestval
) {
207 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
208 ssbd_spec_ctrl_to_tif(hostval
);
210 speculation_ctrl_update(tif
);
213 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
215 static void x86_amd_ssb_disable(void)
217 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
219 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
220 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
221 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
222 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
226 #define pr_fmt(fmt) "MDS: " fmt
228 /* Default mitigation for MDS-affected CPUs */
229 static enum mds_mitigations mds_mitigation __ro_after_init
= MDS_MITIGATION_FULL
;
230 static bool mds_nosmt __ro_after_init
= false;
232 static const char * const mds_strings
[] = {
233 [MDS_MITIGATION_OFF
] = "Vulnerable",
234 [MDS_MITIGATION_FULL
] = "Mitigation: Clear CPU buffers",
235 [MDS_MITIGATION_VMWERV
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
238 static void __init
mds_select_mitigation(void)
240 if (!boot_cpu_has_bug(X86_BUG_MDS
) || cpu_mitigations_off()) {
241 mds_mitigation
= MDS_MITIGATION_OFF
;
245 if (mds_mitigation
== MDS_MITIGATION_FULL
) {
246 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR
))
247 mds_mitigation
= MDS_MITIGATION_VMWERV
;
249 static_branch_enable(&mds_user_clear
);
251 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY
) &&
252 (mds_nosmt
|| cpu_mitigations_auto_nosmt()))
253 cpu_smt_disable(false);
257 static void __init
mds_print_mitigation(void)
259 if (!boot_cpu_has_bug(X86_BUG_MDS
) || cpu_mitigations_off())
262 pr_info("%s\n", mds_strings
[mds_mitigation
]);
265 static int __init
mds_cmdline(char *str
)
267 if (!boot_cpu_has_bug(X86_BUG_MDS
))
273 if (!strcmp(str
, "off"))
274 mds_mitigation
= MDS_MITIGATION_OFF
;
275 else if (!strcmp(str
, "full"))
276 mds_mitigation
= MDS_MITIGATION_FULL
;
277 else if (!strcmp(str
, "full,nosmt")) {
278 mds_mitigation
= MDS_MITIGATION_FULL
;
284 early_param("mds", mds_cmdline
);
287 #define pr_fmt(fmt) "TAA: " fmt
289 /* Default mitigation for TAA-affected CPUs */
290 static enum taa_mitigations taa_mitigation __ro_after_init
= TAA_MITIGATION_VERW
;
291 static bool taa_nosmt __ro_after_init
;
293 static const char * const taa_strings
[] = {
294 [TAA_MITIGATION_OFF
] = "Vulnerable",
295 [TAA_MITIGATION_UCODE_NEEDED
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
296 [TAA_MITIGATION_VERW
] = "Mitigation: Clear CPU buffers",
297 [TAA_MITIGATION_TSX_DISABLED
] = "Mitigation: TSX disabled",
300 static void __init
taa_select_mitigation(void)
304 if (!boot_cpu_has_bug(X86_BUG_TAA
)) {
305 taa_mitigation
= TAA_MITIGATION_OFF
;
309 /* TSX previously disabled by tsx=off */
310 if (!boot_cpu_has(X86_FEATURE_RTM
)) {
311 taa_mitigation
= TAA_MITIGATION_TSX_DISABLED
;
315 if (cpu_mitigations_off()) {
316 taa_mitigation
= TAA_MITIGATION_OFF
;
321 * TAA mitigation via VERW is turned off if both
322 * tsx_async_abort=off and mds=off are specified.
324 if (taa_mitigation
== TAA_MITIGATION_OFF
&&
325 mds_mitigation
== MDS_MITIGATION_OFF
)
328 if (boot_cpu_has(X86_FEATURE_MD_CLEAR
))
329 taa_mitigation
= TAA_MITIGATION_VERW
;
331 taa_mitigation
= TAA_MITIGATION_UCODE_NEEDED
;
334 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
335 * A microcode update fixes this behavior to clear CPU buffers. It also
336 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
337 * ARCH_CAP_TSX_CTRL_MSR bit.
339 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
340 * update is required.
342 ia32_cap
= x86_read_arch_cap_msr();
343 if ( (ia32_cap
& ARCH_CAP_MDS_NO
) &&
344 !(ia32_cap
& ARCH_CAP_TSX_CTRL_MSR
))
345 taa_mitigation
= TAA_MITIGATION_UCODE_NEEDED
;
348 * TSX is enabled, select alternate mitigation for TAA which is
349 * the same as MDS. Enable MDS static branch to clear CPU buffers.
351 * For guests that can't determine whether the correct microcode is
352 * present on host, enable the mitigation for UCODE_NEEDED as well.
354 static_branch_enable(&mds_user_clear
);
356 if (taa_nosmt
|| cpu_mitigations_auto_nosmt())
357 cpu_smt_disable(false);
360 * Update MDS mitigation, if necessary, as the mds_user_clear is
361 * now enabled for TAA mitigation.
363 if (mds_mitigation
== MDS_MITIGATION_OFF
&&
364 boot_cpu_has_bug(X86_BUG_MDS
)) {
365 mds_mitigation
= MDS_MITIGATION_FULL
;
366 mds_select_mitigation();
369 pr_info("%s\n", taa_strings
[taa_mitigation
]);
372 static int __init
tsx_async_abort_parse_cmdline(char *str
)
374 if (!boot_cpu_has_bug(X86_BUG_TAA
))
380 if (!strcmp(str
, "off")) {
381 taa_mitigation
= TAA_MITIGATION_OFF
;
382 } else if (!strcmp(str
, "full")) {
383 taa_mitigation
= TAA_MITIGATION_VERW
;
384 } else if (!strcmp(str
, "full,nosmt")) {
385 taa_mitigation
= TAA_MITIGATION_VERW
;
391 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline
);
394 #define pr_fmt(fmt) "Spectre V1 : " fmt
396 enum spectre_v1_mitigation
{
397 SPECTRE_V1_MITIGATION_NONE
,
398 SPECTRE_V1_MITIGATION_AUTO
,
401 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init
=
402 SPECTRE_V1_MITIGATION_AUTO
;
404 static const char * const spectre_v1_strings
[] = {
405 [SPECTRE_V1_MITIGATION_NONE
] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
406 [SPECTRE_V1_MITIGATION_AUTO
] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
410 * Does SMAP provide full mitigation against speculative kernel access to
413 static bool smap_works_speculatively(void)
415 if (!boot_cpu_has(X86_FEATURE_SMAP
))
419 * On CPUs which are vulnerable to Meltdown, SMAP does not
420 * prevent speculative access to user data in the L1 cache.
421 * Consider SMAP to be non-functional as a mitigation on these
424 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN
))
430 static void __init
spectre_v1_select_mitigation(void)
432 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1
) || cpu_mitigations_off()) {
433 spectre_v1_mitigation
= SPECTRE_V1_MITIGATION_NONE
;
437 if (spectre_v1_mitigation
== SPECTRE_V1_MITIGATION_AUTO
) {
439 * With Spectre v1, a user can speculatively control either
440 * path of a conditional swapgs with a user-controlled GS
441 * value. The mitigation is to add lfences to both code paths.
443 * If FSGSBASE is enabled, the user can put a kernel address in
444 * GS, in which case SMAP provides no protection.
446 * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
447 * FSGSBASE enablement patches have been merged. ]
449 * If FSGSBASE is disabled, the user can only put a user space
450 * address in GS. That makes an attack harder, but still
451 * possible if there's no SMAP protection.
453 if (!smap_works_speculatively()) {
455 * Mitigation can be provided from SWAPGS itself or
456 * PTI as the CR3 write in the Meltdown mitigation
459 * If neither is there, mitigate with an LFENCE to
460 * stop speculation through swapgs.
462 if (boot_cpu_has_bug(X86_BUG_SWAPGS
) &&
463 !boot_cpu_has(X86_FEATURE_PTI
))
464 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER
);
467 * Enable lfences in the kernel entry (non-swapgs)
468 * paths, to prevent user entry from speculatively
471 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL
);
475 pr_info("%s\n", spectre_v1_strings
[spectre_v1_mitigation
]);
478 static int __init
nospectre_v1_cmdline(char *str
)
480 spectre_v1_mitigation
= SPECTRE_V1_MITIGATION_NONE
;
483 early_param("nospectre_v1", nospectre_v1_cmdline
);
486 #define pr_fmt(fmt) "Spectre V2 : " fmt
488 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
491 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
492 SPECTRE_V2_USER_NONE
;
494 #ifdef CONFIG_RETPOLINE
495 static bool spectre_v2_bad_module
;
497 bool retpoline_module_ok(bool has_retpoline
)
499 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
502 pr_err("System may be vulnerable to spectre v2\n");
503 spectre_v2_bad_module
= true;
507 static inline const char *spectre_v2_module_string(void)
509 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
512 static inline const char *spectre_v2_module_string(void) { return ""; }
515 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
517 int len
= strlen(opt
);
519 return len
== arglen
&& !strncmp(arg
, opt
, len
);
522 /* The kernel command line selection for spectre v2 */
523 enum spectre_v2_mitigation_cmd
{
526 SPECTRE_V2_CMD_FORCE
,
527 SPECTRE_V2_CMD_RETPOLINE
,
528 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
529 SPECTRE_V2_CMD_RETPOLINE_AMD
,
532 enum spectre_v2_user_cmd
{
533 SPECTRE_V2_USER_CMD_NONE
,
534 SPECTRE_V2_USER_CMD_AUTO
,
535 SPECTRE_V2_USER_CMD_FORCE
,
536 SPECTRE_V2_USER_CMD_PRCTL
,
537 SPECTRE_V2_USER_CMD_PRCTL_IBPB
,
538 SPECTRE_V2_USER_CMD_SECCOMP
,
539 SPECTRE_V2_USER_CMD_SECCOMP_IBPB
,
542 static const char * const spectre_v2_user_strings
[] = {
543 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
544 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
545 [SPECTRE_V2_USER_STRICT_PREFERRED
] = "User space: Mitigation: STIBP always-on protection",
546 [SPECTRE_V2_USER_PRCTL
] = "User space: Mitigation: STIBP via prctl",
547 [SPECTRE_V2_USER_SECCOMP
] = "User space: Mitigation: STIBP via seccomp and prctl",
550 static const struct {
552 enum spectre_v2_user_cmd cmd
;
554 } v2_user_options
[] __initconst
= {
555 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
556 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
557 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
558 { "prctl", SPECTRE_V2_USER_CMD_PRCTL
, false },
559 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB
, false },
560 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP
, false },
561 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB
, false },
564 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
566 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
567 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
570 static enum spectre_v2_user_cmd __init
571 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
577 case SPECTRE_V2_CMD_NONE
:
578 return SPECTRE_V2_USER_CMD_NONE
;
579 case SPECTRE_V2_CMD_FORCE
:
580 return SPECTRE_V2_USER_CMD_FORCE
;
585 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
588 return SPECTRE_V2_USER_CMD_AUTO
;
590 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
591 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
592 spec_v2_user_print_cond(v2_user_options
[i
].option
,
593 v2_user_options
[i
].secure
);
594 return v2_user_options
[i
].cmd
;
598 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
599 return SPECTRE_V2_USER_CMD_AUTO
;
603 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
605 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
606 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
607 enum spectre_v2_user_cmd cmd
;
609 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
612 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
613 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
614 smt_possible
= false;
616 cmd
= spectre_v2_parse_user_cmdline(v2_cmd
);
618 case SPECTRE_V2_USER_CMD_NONE
:
620 case SPECTRE_V2_USER_CMD_FORCE
:
621 mode
= SPECTRE_V2_USER_STRICT
;
623 case SPECTRE_V2_USER_CMD_PRCTL
:
624 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
625 mode
= SPECTRE_V2_USER_PRCTL
;
627 case SPECTRE_V2_USER_CMD_AUTO
:
628 case SPECTRE_V2_USER_CMD_SECCOMP
:
629 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
630 if (IS_ENABLED(CONFIG_SECCOMP
))
631 mode
= SPECTRE_V2_USER_SECCOMP
;
633 mode
= SPECTRE_V2_USER_PRCTL
;
638 * At this point, an STIBP mode other than "off" has been set.
639 * If STIBP support is not being forced, check if STIBP always-on
642 if (mode
!= SPECTRE_V2_USER_STRICT
&&
643 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON
))
644 mode
= SPECTRE_V2_USER_STRICT_PREFERRED
;
646 /* Initialize Indirect Branch Prediction Barrier */
647 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
648 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
651 case SPECTRE_V2_USER_CMD_FORCE
:
652 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
653 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
654 static_branch_enable(&switch_mm_always_ibpb
);
656 case SPECTRE_V2_USER_CMD_PRCTL
:
657 case SPECTRE_V2_USER_CMD_AUTO
:
658 case SPECTRE_V2_USER_CMD_SECCOMP
:
659 static_branch_enable(&switch_mm_cond_ibpb
);
665 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
666 static_key_enabled(&switch_mm_always_ibpb
) ?
667 "always-on" : "conditional");
670 /* If enhanced IBRS is enabled no STIBP required */
671 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
675 * If SMT is not possible or STIBP is not available clear the STIBP
678 if (!smt_possible
|| !boot_cpu_has(X86_FEATURE_STIBP
))
679 mode
= SPECTRE_V2_USER_NONE
;
681 spectre_v2_user
= mode
;
682 /* Only print the STIBP mode when SMT possible */
684 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
687 static const char * const spectre_v2_strings
[] = {
688 [SPECTRE_V2_NONE
] = "Vulnerable",
689 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
690 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
691 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
694 static const struct {
696 enum spectre_v2_mitigation_cmd cmd
;
698 } mitigation_options
[] __initconst
= {
699 { "off", SPECTRE_V2_CMD_NONE
, false },
700 { "on", SPECTRE_V2_CMD_FORCE
, true },
701 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
702 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
703 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
704 { "auto", SPECTRE_V2_CMD_AUTO
, false },
707 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
709 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
710 pr_info("%s selected on command line.\n", reason
);
713 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
715 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
719 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2") ||
720 cpu_mitigations_off())
721 return SPECTRE_V2_CMD_NONE
;
723 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
725 return SPECTRE_V2_CMD_AUTO
;
727 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
728 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
730 cmd
= mitigation_options
[i
].cmd
;
734 if (i
>= ARRAY_SIZE(mitigation_options
)) {
735 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
736 return SPECTRE_V2_CMD_AUTO
;
739 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
740 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
741 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
742 !IS_ENABLED(CONFIG_RETPOLINE
)) {
743 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
744 return SPECTRE_V2_CMD_AUTO
;
747 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
748 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
749 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
750 return SPECTRE_V2_CMD_AUTO
;
753 spec_v2_print_cond(mitigation_options
[i
].option
,
754 mitigation_options
[i
].secure
);
758 static void __init
spectre_v2_select_mitigation(void)
760 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
761 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
764 * If the CPU is not affected and the command line mode is NONE or AUTO
765 * then nothing to do.
767 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
768 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
772 case SPECTRE_V2_CMD_NONE
:
775 case SPECTRE_V2_CMD_FORCE
:
776 case SPECTRE_V2_CMD_AUTO
:
777 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
778 mode
= SPECTRE_V2_IBRS_ENHANCED
;
779 /* Force it so VMEXIT will restore correctly */
780 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
781 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
782 goto specv2_set_mode
;
784 if (IS_ENABLED(CONFIG_RETPOLINE
))
787 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
788 if (IS_ENABLED(CONFIG_RETPOLINE
))
791 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
792 if (IS_ENABLED(CONFIG_RETPOLINE
))
793 goto retpoline_generic
;
795 case SPECTRE_V2_CMD_RETPOLINE
:
796 if (IS_ENABLED(CONFIG_RETPOLINE
))
800 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
804 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
806 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
807 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
808 goto retpoline_generic
;
810 mode
= SPECTRE_V2_RETPOLINE_AMD
;
811 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
812 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
815 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
816 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
820 spectre_v2_enabled
= mode
;
821 pr_info("%s\n", spectre_v2_strings
[mode
]);
824 * If spectre v2 protection has been enabled, unconditionally fill
825 * RSB during a context switch; this protects against two independent
828 * - RSB underflow (and switch to BTB) on Skylake+
829 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
831 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
832 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
835 * Retpoline means the kernel is safe because it has no indirect
836 * branches. Enhanced IBRS protects firmware too, so, enable restricted
837 * speculation around firmware calls only when Enhanced IBRS isn't
840 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
841 * the user might select retpoline on the kernel command line and if
842 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
843 * enable IBRS around firmware calls.
845 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
846 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
847 pr_info("Enabling Restricted Speculation for firmware calls\n");
850 /* Set up IBPB and STIBP depending on the general spectre V2 command */
851 spectre_v2_user_select_mitigation(cmd
);
854 static void update_stibp_msr(void * __unused
)
856 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
859 /* Update x86_spec_ctrl_base in case SMT state changed. */
860 static void update_stibp_strict(void)
862 u64 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
864 if (sched_smt_active())
865 mask
|= SPEC_CTRL_STIBP
;
867 if (mask
== x86_spec_ctrl_base
)
870 pr_info("Update user space SMT mitigation: STIBP %s\n",
871 mask
& SPEC_CTRL_STIBP
? "always-on" : "off");
872 x86_spec_ctrl_base
= mask
;
873 on_each_cpu(update_stibp_msr
, NULL
, 1);
876 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
877 static void update_indir_branch_cond(void)
879 if (sched_smt_active())
880 static_branch_enable(&switch_to_cond_stibp
);
882 static_branch_disable(&switch_to_cond_stibp
);
886 #define pr_fmt(fmt) fmt
888 /* Update the static key controlling the MDS CPU buffer clear in idle */
889 static void update_mds_branch_idle(void)
892 * Enable the idle clearing if SMT is active on CPUs which are
893 * affected only by MSBDS and not any other MDS variant.
895 * The other variants cannot be mitigated when SMT is enabled, so
896 * clearing the buffers on idle just to prevent the Store Buffer
897 * repartitioning leak would be a window dressing exercise.
899 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY
))
902 if (sched_smt_active())
903 static_branch_enable(&mds_idle_clear
);
905 static_branch_disable(&mds_idle_clear
);
908 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
909 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
911 void arch_smt_update(void)
913 mutex_lock(&spec_ctrl_mutex
);
915 switch (spectre_v2_user
) {
916 case SPECTRE_V2_USER_NONE
:
918 case SPECTRE_V2_USER_STRICT
:
919 case SPECTRE_V2_USER_STRICT_PREFERRED
:
920 update_stibp_strict();
922 case SPECTRE_V2_USER_PRCTL
:
923 case SPECTRE_V2_USER_SECCOMP
:
924 update_indir_branch_cond();
928 switch (mds_mitigation
) {
929 case MDS_MITIGATION_FULL
:
930 case MDS_MITIGATION_VMWERV
:
931 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY
))
932 pr_warn_once(MDS_MSG_SMT
);
933 update_mds_branch_idle();
935 case MDS_MITIGATION_OFF
:
939 switch (taa_mitigation
) {
940 case TAA_MITIGATION_VERW
:
941 case TAA_MITIGATION_UCODE_NEEDED
:
942 if (sched_smt_active())
943 pr_warn_once(TAA_MSG_SMT
);
945 case TAA_MITIGATION_TSX_DISABLED
:
946 case TAA_MITIGATION_OFF
:
950 mutex_unlock(&spec_ctrl_mutex
);
954 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
956 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
958 /* The kernel command line selection */
959 enum ssb_mitigation_cmd
{
960 SPEC_STORE_BYPASS_CMD_NONE
,
961 SPEC_STORE_BYPASS_CMD_AUTO
,
962 SPEC_STORE_BYPASS_CMD_ON
,
963 SPEC_STORE_BYPASS_CMD_PRCTL
,
964 SPEC_STORE_BYPASS_CMD_SECCOMP
,
967 static const char * const ssb_strings
[] = {
968 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
969 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
970 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
971 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
974 static const struct {
976 enum ssb_mitigation_cmd cmd
;
977 } ssb_mitigation_options
[] __initconst
= {
978 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
979 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
980 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
981 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
982 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
985 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
987 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
991 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable") ||
992 cpu_mitigations_off()) {
993 return SPEC_STORE_BYPASS_CMD_NONE
;
995 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
998 return SPEC_STORE_BYPASS_CMD_AUTO
;
1000 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
1001 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
1004 cmd
= ssb_mitigation_options
[i
].cmd
;
1008 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
1009 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
1010 return SPEC_STORE_BYPASS_CMD_AUTO
;
1017 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
1019 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
1020 enum ssb_mitigation_cmd cmd
;
1022 if (!boot_cpu_has(X86_FEATURE_SSBD
))
1025 cmd
= ssb_parse_cmdline();
1026 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
1027 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
1028 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
1032 case SPEC_STORE_BYPASS_CMD_AUTO
:
1033 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
1035 * Choose prctl+seccomp as the default mode if seccomp is
1038 if (IS_ENABLED(CONFIG_SECCOMP
))
1039 mode
= SPEC_STORE_BYPASS_SECCOMP
;
1041 mode
= SPEC_STORE_BYPASS_PRCTL
;
1043 case SPEC_STORE_BYPASS_CMD_ON
:
1044 mode
= SPEC_STORE_BYPASS_DISABLE
;
1046 case SPEC_STORE_BYPASS_CMD_PRCTL
:
1047 mode
= SPEC_STORE_BYPASS_PRCTL
;
1049 case SPEC_STORE_BYPASS_CMD_NONE
:
1054 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1055 * bit in the mask to allow guests to use the mitigation even in the
1056 * case where the host does not enable it.
1058 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
1059 static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
1060 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
1064 * We have three CPU feature flags that are in play here:
1065 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1066 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1067 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1069 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
1070 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
1072 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1073 * use a completely different MSR and bit dependent on family.
1075 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
1076 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
1077 x86_amd_ssb_disable();
1079 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
1080 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1087 static void ssb_select_mitigation(void)
1089 ssb_mode
= __ssb_select_mitigation();
1091 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
1092 pr_info("%s\n", ssb_strings
[ssb_mode
]);
1096 #define pr_fmt(fmt) "Speculation prctl: " fmt
1098 static void task_update_spec_tif(struct task_struct
*tsk
)
1100 /* Force the update of the real TIF bits */
1101 set_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
);
1104 * Immediately update the speculation control MSRs for the current
1105 * task, but for a non-current task delay setting the CPU
1106 * mitigation until it is scheduled next.
1108 * This can only happen for SECCOMP mitigation. For PRCTL it's
1109 * always the current task.
1112 speculation_ctrl_update_current();
1115 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
1117 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
1118 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
1122 case PR_SPEC_ENABLE
:
1123 /* If speculation is force disabled, enable is not allowed */
1124 if (task_spec_ssb_force_disable(task
))
1126 task_clear_spec_ssb_disable(task
);
1127 task_update_spec_tif(task
);
1129 case PR_SPEC_DISABLE
:
1130 task_set_spec_ssb_disable(task
);
1131 task_update_spec_tif(task
);
1133 case PR_SPEC_FORCE_DISABLE
:
1134 task_set_spec_ssb_disable(task
);
1135 task_set_spec_ssb_force_disable(task
);
1136 task_update_spec_tif(task
);
1144 static int ib_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
1147 case PR_SPEC_ENABLE
:
1148 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
1151 * Indirect branch speculation is always disabled in strict
1154 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
1155 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
1157 task_clear_spec_ib_disable(task
);
1158 task_update_spec_tif(task
);
1160 case PR_SPEC_DISABLE
:
1161 case PR_SPEC_FORCE_DISABLE
:
1163 * Indirect branch speculation is always allowed when
1164 * mitigation is force disabled.
1166 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
1168 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
1169 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
1171 task_set_spec_ib_disable(task
);
1172 if (ctrl
== PR_SPEC_FORCE_DISABLE
)
1173 task_set_spec_ib_force_disable(task
);
1174 task_update_spec_tif(task
);
1182 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
1186 case PR_SPEC_STORE_BYPASS
:
1187 return ssb_prctl_set(task
, ctrl
);
1188 case PR_SPEC_INDIRECT_BRANCH
:
1189 return ib_prctl_set(task
, ctrl
);
1195 #ifdef CONFIG_SECCOMP
1196 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
1198 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
1199 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
1200 if (spectre_v2_user
== SPECTRE_V2_USER_SECCOMP
)
1201 ib_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
1205 static int ssb_prctl_get(struct task_struct
*task
)
1208 case SPEC_STORE_BYPASS_DISABLE
:
1209 return PR_SPEC_DISABLE
;
1210 case SPEC_STORE_BYPASS_SECCOMP
:
1211 case SPEC_STORE_BYPASS_PRCTL
:
1212 if (task_spec_ssb_force_disable(task
))
1213 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
1214 if (task_spec_ssb_disable(task
))
1215 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
1216 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
1218 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
1219 return PR_SPEC_ENABLE
;
1220 return PR_SPEC_NOT_AFFECTED
;
1224 static int ib_prctl_get(struct task_struct
*task
)
1226 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
1227 return PR_SPEC_NOT_AFFECTED
;
1229 switch (spectre_v2_user
) {
1230 case SPECTRE_V2_USER_NONE
:
1231 return PR_SPEC_ENABLE
;
1232 case SPECTRE_V2_USER_PRCTL
:
1233 case SPECTRE_V2_USER_SECCOMP
:
1234 if (task_spec_ib_force_disable(task
))
1235 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
1236 if (task_spec_ib_disable(task
))
1237 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
1238 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
1239 case SPECTRE_V2_USER_STRICT
:
1240 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1241 return PR_SPEC_DISABLE
;
1243 return PR_SPEC_NOT_AFFECTED
;
1247 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
1250 case PR_SPEC_STORE_BYPASS
:
1251 return ssb_prctl_get(task
);
1252 case PR_SPEC_INDIRECT_BRANCH
:
1253 return ib_prctl_get(task
);
1259 void x86_spec_ctrl_setup_ap(void)
1261 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
1262 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1264 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
1265 x86_amd_ssb_disable();
1268 bool itlb_multihit_kvm_mitigation
;
1269 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation
);
1272 #define pr_fmt(fmt) "L1TF: " fmt
1274 /* Default mitigation for L1TF-affected CPUs */
1275 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
1276 #if IS_ENABLED(CONFIG_KVM_INTEL)
1277 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
1279 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
1280 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
1283 * These CPUs all support 44bits physical address space internally in the
1284 * cache but CPUID can report a smaller number of physical address bits.
1286 * The L1TF mitigation uses the top most address bit for the inversion of
1287 * non present PTEs. When the installed memory reaches into the top most
1288 * address bit due to memory holes, which has been observed on machines
1289 * which report 36bits physical address bits and have 32G RAM installed,
1290 * then the mitigation range check in l1tf_select_mitigation() triggers.
1291 * This is a false positive because the mitigation is still possible due to
1292 * the fact that the cache uses 44bit internally. Use the cache bits
1293 * instead of the reported physical bits and adjust them on the affected
1294 * machines to 44bit if the reported bits are less than 44.
1296 static void override_cache_bits(struct cpuinfo_x86
*c
)
1301 switch (c
->x86_model
) {
1302 case INTEL_FAM6_NEHALEM
:
1303 case INTEL_FAM6_WESTMERE
:
1304 case INTEL_FAM6_SANDYBRIDGE
:
1305 case INTEL_FAM6_IVYBRIDGE
:
1306 case INTEL_FAM6_HASWELL_CORE
:
1307 case INTEL_FAM6_HASWELL_ULT
:
1308 case INTEL_FAM6_HASWELL_GT3E
:
1309 case INTEL_FAM6_BROADWELL_CORE
:
1310 case INTEL_FAM6_BROADWELL_GT3E
:
1311 case INTEL_FAM6_SKYLAKE_MOBILE
:
1312 case INTEL_FAM6_SKYLAKE_DESKTOP
:
1313 case INTEL_FAM6_KABYLAKE_MOBILE
:
1314 case INTEL_FAM6_KABYLAKE_DESKTOP
:
1315 if (c
->x86_cache_bits
< 44)
1316 c
->x86_cache_bits
= 44;
1321 static void __init
l1tf_select_mitigation(void)
1325 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1328 if (cpu_mitigations_off())
1329 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1330 else if (cpu_mitigations_auto_nosmt())
1331 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1333 override_cache_bits(&boot_cpu_data
);
1335 switch (l1tf_mitigation
) {
1336 case L1TF_MITIGATION_OFF
:
1337 case L1TF_MITIGATION_FLUSH_NOWARN
:
1338 case L1TF_MITIGATION_FLUSH
:
1340 case L1TF_MITIGATION_FLUSH_NOSMT
:
1341 case L1TF_MITIGATION_FULL
:
1342 cpu_smt_disable(false);
1344 case L1TF_MITIGATION_FULL_FORCE
:
1345 cpu_smt_disable(true);
1349 #if CONFIG_PGTABLE_LEVELS == 2
1350 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1354 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
1355 if (l1tf_mitigation
!= L1TF_MITIGATION_OFF
&&
1356 e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
1357 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1358 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1360 pr_info("However, doing so will make a part of your RAM unusable.\n");
1361 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1365 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
1368 static int __init
l1tf_cmdline(char *str
)
1370 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1376 if (!strcmp(str
, "off"))
1377 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1378 else if (!strcmp(str
, "flush,nowarn"))
1379 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
1380 else if (!strcmp(str
, "flush"))
1381 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
1382 else if (!strcmp(str
, "flush,nosmt"))
1383 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1384 else if (!strcmp(str
, "full"))
1385 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
1386 else if (!strcmp(str
, "full,force"))
1387 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
1391 early_param("l1tf", l1tf_cmdline
);
1394 #define pr_fmt(fmt) fmt
1398 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1400 #if IS_ENABLED(CONFIG_KVM_INTEL)
1401 static const char * const l1tf_vmx_states
[] = {
1402 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
1403 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
1404 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
1405 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
1406 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
1407 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
1410 static ssize_t
l1tf_show_state(char *buf
)
1412 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
1413 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1415 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
1416 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
1417 sched_smt_active())) {
1418 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
1419 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
1422 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
1423 l1tf_vmx_states
[l1tf_vmx_mitigation
],
1424 sched_smt_active() ? "vulnerable" : "disabled");
1427 static ssize_t
itlb_multihit_show_state(char *buf
)
1429 if (itlb_multihit_kvm_mitigation
)
1430 return sprintf(buf
, "KVM: Mitigation: Split huge pages\n");
1432 return sprintf(buf
, "KVM: Vulnerable\n");
1435 static ssize_t
l1tf_show_state(char *buf
)
1437 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1440 static ssize_t
itlb_multihit_show_state(char *buf
)
1442 return sprintf(buf
, "Processor vulnerable\n");
1446 static ssize_t
mds_show_state(char *buf
)
1448 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
1449 return sprintf(buf
, "%s; SMT Host state unknown\n",
1450 mds_strings
[mds_mitigation
]);
1453 if (boot_cpu_has(X86_BUG_MSBDS_ONLY
)) {
1454 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1455 (mds_mitigation
== MDS_MITIGATION_OFF
? "vulnerable" :
1456 sched_smt_active() ? "mitigated" : "disabled"));
1459 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1460 sched_smt_active() ? "vulnerable" : "disabled");
1463 static ssize_t
tsx_async_abort_show_state(char *buf
)
1465 if ((taa_mitigation
== TAA_MITIGATION_TSX_DISABLED
) ||
1466 (taa_mitigation
== TAA_MITIGATION_OFF
))
1467 return sprintf(buf
, "%s\n", taa_strings
[taa_mitigation
]);
1469 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
1470 return sprintf(buf
, "%s; SMT Host state unknown\n",
1471 taa_strings
[taa_mitigation
]);
1474 return sprintf(buf
, "%s; SMT %s\n", taa_strings
[taa_mitigation
],
1475 sched_smt_active() ? "vulnerable" : "disabled");
1478 static char *stibp_state(void)
1480 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
1483 switch (spectre_v2_user
) {
1484 case SPECTRE_V2_USER_NONE
:
1485 return ", STIBP: disabled";
1486 case SPECTRE_V2_USER_STRICT
:
1487 return ", STIBP: forced";
1488 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1489 return ", STIBP: always-on";
1490 case SPECTRE_V2_USER_PRCTL
:
1491 case SPECTRE_V2_USER_SECCOMP
:
1492 if (static_key_enabled(&switch_to_cond_stibp
))
1493 return ", STIBP: conditional";
1498 static char *ibpb_state(void)
1500 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
1501 if (static_key_enabled(&switch_mm_always_ibpb
))
1502 return ", IBPB: always-on";
1503 if (static_key_enabled(&switch_mm_cond_ibpb
))
1504 return ", IBPB: conditional";
1505 return ", IBPB: disabled";
1510 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
1511 char *buf
, unsigned int bug
)
1513 if (!boot_cpu_has_bug(bug
))
1514 return sprintf(buf
, "Not affected\n");
1517 case X86_BUG_CPU_MELTDOWN
:
1518 if (boot_cpu_has(X86_FEATURE_PTI
))
1519 return sprintf(buf
, "Mitigation: PTI\n");
1523 case X86_BUG_SPECTRE_V1
:
1524 return sprintf(buf
, "%s\n", spectre_v1_strings
[spectre_v1_mitigation
]);
1526 case X86_BUG_SPECTRE_V2
:
1527 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
1529 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1531 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1532 spectre_v2_module_string());
1534 case X86_BUG_SPEC_STORE_BYPASS
:
1535 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1538 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1539 return l1tf_show_state(buf
);
1543 return mds_show_state(buf
);
1546 return tsx_async_abort_show_state(buf
);
1548 case X86_BUG_ITLB_MULTIHIT
:
1549 return itlb_multihit_show_state(buf
);
1555 return sprintf(buf
, "Vulnerable\n");
1558 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1560 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1563 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1565 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1568 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1570 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1573 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1575 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1578 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1580 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);
1583 ssize_t
cpu_show_mds(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1585 return cpu_show_common(dev
, attr
, buf
, X86_BUG_MDS
);
1588 ssize_t
cpu_show_tsx_async_abort(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1590 return cpu_show_common(dev
, attr
, buf
, X86_BUG_TAA
);
1593 ssize_t
cpu_show_itlb_multihit(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1595 return cpu_show_common(dev
, attr
, buf
, X86_BUG_ITLB_MULTIHIT
);