1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
18 #include <asm/spec-ctrl.h>
19 #include <asm/cmdline.h>
21 #include <asm/processor.h>
22 #include <asm/processor-flags.h>
23 #include <asm/fpu/internal.h>
26 #include <asm/paravirt.h>
27 #include <asm/alternative.h>
28 #include <asm/pgtable.h>
29 #include <asm/set_memory.h>
30 #include <asm/intel-family.h>
31 #include <asm/e820/api.h>
33 static void __init
spectre_v2_select_mitigation(void);
34 static void __init
ssb_select_mitigation(void);
35 static void __init
l1tf_select_mitigation(void);
38 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
39 * writes to SPEC_CTRL contain whatever reserved bits have been set.
41 u64 __ro_after_init x86_spec_ctrl_base
;
42 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
45 * The vendor and possibly platform specific bits which can be modified in
48 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
51 * AMD specific MSR info for Speculative Store Bypass control.
52 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
54 u64 __ro_after_init x86_amd_ls_cfg_base
;
55 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
57 void __init
check_bugs(void)
62 * identify_boot_cpu() initialized SMT support information, let the
65 cpu_smt_check_topology_early();
67 if (!IS_ENABLED(CONFIG_SMP
)) {
69 print_cpu_info(&boot_cpu_data
);
73 * Read the SPEC_CTRL MSR to account for reserved bits which may
74 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
75 * init code as it is not enumerated and depends on the family.
77 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
78 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
80 /* Allow STIBP in MSR_SPEC_CTRL if supported */
81 if (boot_cpu_has(X86_FEATURE_STIBP
))
82 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
84 /* Select the proper spectre mitigation before patching alternatives */
85 spectre_v2_select_mitigation();
88 * Select proper mitigation for any exposure to the Speculative Store
89 * Bypass vulnerability.
91 ssb_select_mitigation();
93 l1tf_select_mitigation();
97 * Check whether we are able to run this kernel safely on SMP.
99 * - i386 is no longer supported.
100 * - In order to run on anything without a TSC, we need to be
101 * compiled for a i486.
103 if (boot_cpu_data
.x86
< 4)
104 panic("Kernel requires i486+ for 'invlpg' and other features");
106 init_utsname()->machine
[1] =
107 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
108 alternative_instructions();
110 fpu__init_check_bugs();
111 #else /* CONFIG_X86_64 */
112 alternative_instructions();
115 * Make sure the first 2MB area is not mapped by huge pages
116 * There are typically fixed size MTRRs in there and overlapping
117 * MTRRs into large pages causes slow downs.
119 * Right now we don't do that with gbpages because there seems
120 * very little benefit for that case.
123 set_memory_4k((unsigned long)__va(0), 1);
127 /* The kernel command line selection */
128 enum spectre_v2_mitigation_cmd
{
131 SPECTRE_V2_CMD_FORCE
,
132 SPECTRE_V2_CMD_RETPOLINE
,
133 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
134 SPECTRE_V2_CMD_RETPOLINE_AMD
,
137 static const char *spectre_v2_strings
[] = {
138 [SPECTRE_V2_NONE
] = "Vulnerable",
139 [SPECTRE_V2_RETPOLINE_MINIMAL
] = "Vulnerable: Minimal generic ASM retpoline",
140 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD
] = "Vulnerable: Minimal AMD ASM retpoline",
141 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
142 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
143 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
147 #define pr_fmt(fmt) "Spectre V2 : " fmt
149 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
153 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
155 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
156 struct thread_info
*ti
= current_thread_info();
158 /* Is MSR_SPEC_CTRL implemented ? */
159 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
161 * Restrict guest_spec_ctrl to supported values. Clear the
162 * modifiable bits in the host base value and or the
163 * modifiable bits from the guest value.
165 guestval
= hostval
& ~x86_spec_ctrl_mask
;
166 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
168 /* SSBD controlled in MSR_SPEC_CTRL */
169 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
))
170 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
172 if (hostval
!= guestval
) {
173 msrval
= setguest
? guestval
: hostval
;
174 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
179 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
180 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
182 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
183 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
187 * If the host has SSBD mitigation enabled, force it in the host's
188 * virtual MSR value. If its not permanently enabled, evaluate
189 * current's TIF_SSBD thread flag.
191 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
192 hostval
= SPEC_CTRL_SSBD
;
194 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
196 /* Sanitize the guest value */
197 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
199 if (hostval
!= guestval
) {
202 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
203 ssbd_spec_ctrl_to_tif(hostval
);
205 speculative_store_bypass_update(tif
);
208 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
210 static void x86_amd_ssb_disable(void)
212 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
214 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
215 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
216 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
217 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
221 static bool spectre_v2_bad_module
;
223 bool retpoline_module_ok(bool has_retpoline
)
225 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
228 pr_err("System may be vulnerable to spectre v2\n");
229 spectre_v2_bad_module
= true;
233 static inline const char *spectre_v2_module_string(void)
235 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
238 static inline const char *spectre_v2_module_string(void) { return ""; }
241 static void __init
spec2_print_if_insecure(const char *reason
)
243 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
244 pr_info("%s selected on command line.\n", reason
);
247 static void __init
spec2_print_if_secure(const char *reason
)
249 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
250 pr_info("%s selected on command line.\n", reason
);
253 static inline bool retp_compiler(void)
255 return __is_defined(RETPOLINE
);
258 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
260 int len
= strlen(opt
);
262 return len
== arglen
&& !strncmp(arg
, opt
, len
);
265 static const struct {
267 enum spectre_v2_mitigation_cmd cmd
;
269 } mitigation_options
[] = {
270 { "off", SPECTRE_V2_CMD_NONE
, false },
271 { "on", SPECTRE_V2_CMD_FORCE
, true },
272 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
273 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
274 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
275 { "auto", SPECTRE_V2_CMD_AUTO
, false },
278 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
282 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
284 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
285 return SPECTRE_V2_CMD_NONE
;
287 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
289 return SPECTRE_V2_CMD_AUTO
;
291 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
292 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
294 cmd
= mitigation_options
[i
].cmd
;
298 if (i
>= ARRAY_SIZE(mitigation_options
)) {
299 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
300 return SPECTRE_V2_CMD_AUTO
;
304 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
305 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
306 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
307 !IS_ENABLED(CONFIG_RETPOLINE
)) {
308 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
309 return SPECTRE_V2_CMD_AUTO
;
312 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
313 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
314 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
315 return SPECTRE_V2_CMD_AUTO
;
318 if (mitigation_options
[i
].secure
)
319 spec2_print_if_secure(mitigation_options
[i
].option
);
321 spec2_print_if_insecure(mitigation_options
[i
].option
);
326 static void __init
spectre_v2_select_mitigation(void)
328 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
329 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
332 * If the CPU is not affected and the command line mode is NONE or AUTO
333 * then nothing to do.
335 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
336 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
340 case SPECTRE_V2_CMD_NONE
:
343 case SPECTRE_V2_CMD_FORCE
:
344 case SPECTRE_V2_CMD_AUTO
:
345 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
346 mode
= SPECTRE_V2_IBRS_ENHANCED
;
347 /* Force it so VMEXIT will restore correctly */
348 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
349 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
350 goto specv2_set_mode
;
352 if (IS_ENABLED(CONFIG_RETPOLINE
))
355 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
356 if (IS_ENABLED(CONFIG_RETPOLINE
))
359 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
360 if (IS_ENABLED(CONFIG_RETPOLINE
))
361 goto retpoline_generic
;
363 case SPECTRE_V2_CMD_RETPOLINE
:
364 if (IS_ENABLED(CONFIG_RETPOLINE
))
368 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
372 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
374 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
375 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
376 goto retpoline_generic
;
378 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD
:
379 SPECTRE_V2_RETPOLINE_MINIMAL_AMD
;
380 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
381 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
384 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC
:
385 SPECTRE_V2_RETPOLINE_MINIMAL
;
386 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
390 spectre_v2_enabled
= mode
;
391 pr_info("%s\n", spectre_v2_strings
[mode
]);
394 * If spectre v2 protection has been enabled, unconditionally fill
395 * RSB during a context switch; this protects against two independent
398 * - RSB underflow (and switch to BTB) on Skylake+
399 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
401 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
402 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
404 /* Initialize Indirect Branch Prediction Barrier if supported */
405 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
406 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
407 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
411 * Retpoline means the kernel is safe because it has no indirect
412 * branches. Enhanced IBRS protects firmware too, so, enable restricted
413 * speculation around firmware calls only when Enhanced IBRS isn't
416 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
417 * the user might select retpoline on the kernel command line and if
418 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
419 * enable IBRS around firmware calls.
421 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
422 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
423 pr_info("Enabling Restricted Speculation for firmware calls\n");
428 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
430 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
432 /* The kernel command line selection */
433 enum ssb_mitigation_cmd
{
434 SPEC_STORE_BYPASS_CMD_NONE
,
435 SPEC_STORE_BYPASS_CMD_AUTO
,
436 SPEC_STORE_BYPASS_CMD_ON
,
437 SPEC_STORE_BYPASS_CMD_PRCTL
,
438 SPEC_STORE_BYPASS_CMD_SECCOMP
,
441 static const char *ssb_strings
[] = {
442 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
443 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
444 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
445 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
448 static const struct {
450 enum ssb_mitigation_cmd cmd
;
451 } ssb_mitigation_options
[] = {
452 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
453 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
454 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
455 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
456 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
459 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
461 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
465 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
466 return SPEC_STORE_BYPASS_CMD_NONE
;
468 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
471 return SPEC_STORE_BYPASS_CMD_AUTO
;
473 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
474 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
477 cmd
= ssb_mitigation_options
[i
].cmd
;
481 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
482 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
483 return SPEC_STORE_BYPASS_CMD_AUTO
;
490 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
492 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
493 enum ssb_mitigation_cmd cmd
;
495 if (!boot_cpu_has(X86_FEATURE_SSBD
))
498 cmd
= ssb_parse_cmdline();
499 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
500 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
501 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
505 case SPEC_STORE_BYPASS_CMD_AUTO
:
506 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
508 * Choose prctl+seccomp as the default mode if seccomp is
511 if (IS_ENABLED(CONFIG_SECCOMP
))
512 mode
= SPEC_STORE_BYPASS_SECCOMP
;
514 mode
= SPEC_STORE_BYPASS_PRCTL
;
516 case SPEC_STORE_BYPASS_CMD_ON
:
517 mode
= SPEC_STORE_BYPASS_DISABLE
;
519 case SPEC_STORE_BYPASS_CMD_PRCTL
:
520 mode
= SPEC_STORE_BYPASS_PRCTL
;
522 case SPEC_STORE_BYPASS_CMD_NONE
:
527 * We have three CPU feature flags that are in play here:
528 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
529 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
530 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
532 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
533 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
535 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
536 * use a completely different MSR and bit dependent on family.
538 switch (boot_cpu_data
.x86_vendor
) {
539 case X86_VENDOR_INTEL
:
541 if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
542 x86_amd_ssb_disable();
545 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
546 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
547 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
555 static void ssb_select_mitigation(void)
557 ssb_mode
= __ssb_select_mitigation();
559 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
560 pr_info("%s\n", ssb_strings
[ssb_mode
]);
564 #define pr_fmt(fmt) "Speculation prctl: " fmt
566 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
570 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
571 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
576 /* If speculation is force disabled, enable is not allowed */
577 if (task_spec_ssb_force_disable(task
))
579 task_clear_spec_ssb_disable(task
);
580 update
= test_and_clear_tsk_thread_flag(task
, TIF_SSBD
);
582 case PR_SPEC_DISABLE
:
583 task_set_spec_ssb_disable(task
);
584 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
586 case PR_SPEC_FORCE_DISABLE
:
587 task_set_spec_ssb_disable(task
);
588 task_set_spec_ssb_force_disable(task
);
589 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
596 * If being set on non-current task, delay setting the CPU
597 * mitigation until it is next scheduled.
599 if (task
== current
&& update
)
600 speculative_store_bypass_update_current();
605 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
609 case PR_SPEC_STORE_BYPASS
:
610 return ssb_prctl_set(task
, ctrl
);
616 #ifdef CONFIG_SECCOMP
617 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
619 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
620 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
624 static int ssb_prctl_get(struct task_struct
*task
)
627 case SPEC_STORE_BYPASS_DISABLE
:
628 return PR_SPEC_DISABLE
;
629 case SPEC_STORE_BYPASS_SECCOMP
:
630 case SPEC_STORE_BYPASS_PRCTL
:
631 if (task_spec_ssb_force_disable(task
))
632 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
633 if (task_spec_ssb_disable(task
))
634 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
635 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
637 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
638 return PR_SPEC_ENABLE
;
639 return PR_SPEC_NOT_AFFECTED
;
643 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
646 case PR_SPEC_STORE_BYPASS
:
647 return ssb_prctl_get(task
);
653 void x86_spec_ctrl_setup_ap(void)
655 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
656 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
658 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
659 x86_amd_ssb_disable();
663 #define pr_fmt(fmt) "L1TF: " fmt
665 /* Default mitigation for L1TF-affected CPUs */
666 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
667 #if IS_ENABLED(CONFIG_KVM_INTEL)
668 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
670 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
671 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
675 * These CPUs all support 44bits physical address space internally in the
676 * cache but CPUID can report a smaller number of physical address bits.
678 * The L1TF mitigation uses the top most address bit for the inversion of
679 * non present PTEs. When the installed memory reaches into the top most
680 * address bit due to memory holes, which has been observed on machines
681 * which report 36bits physical address bits and have 32G RAM installed,
682 * then the mitigation range check in l1tf_select_mitigation() triggers.
683 * This is a false positive because the mitigation is still possible due to
684 * the fact that the cache uses 44bit internally. Use the cache bits
685 * instead of the reported physical bits and adjust them on the affected
686 * machines to 44bit if the reported bits are less than 44.
688 static void override_cache_bits(struct cpuinfo_x86
*c
)
693 switch (c
->x86_model
) {
694 case INTEL_FAM6_NEHALEM
:
695 case INTEL_FAM6_WESTMERE
:
696 case INTEL_FAM6_SANDYBRIDGE
:
697 case INTEL_FAM6_IVYBRIDGE
:
698 case INTEL_FAM6_HASWELL_CORE
:
699 case INTEL_FAM6_HASWELL_ULT
:
700 case INTEL_FAM6_HASWELL_GT3E
:
701 case INTEL_FAM6_BROADWELL_CORE
:
702 case INTEL_FAM6_BROADWELL_GT3E
:
703 case INTEL_FAM6_SKYLAKE_MOBILE
:
704 case INTEL_FAM6_SKYLAKE_DESKTOP
:
705 case INTEL_FAM6_KABYLAKE_MOBILE
:
706 case INTEL_FAM6_KABYLAKE_DESKTOP
:
707 if (c
->x86_cache_bits
< 44)
708 c
->x86_cache_bits
= 44;
713 static void __init
l1tf_select_mitigation(void)
717 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
720 override_cache_bits(&boot_cpu_data
);
722 switch (l1tf_mitigation
) {
723 case L1TF_MITIGATION_OFF
:
724 case L1TF_MITIGATION_FLUSH_NOWARN
:
725 case L1TF_MITIGATION_FLUSH
:
727 case L1TF_MITIGATION_FLUSH_NOSMT
:
728 case L1TF_MITIGATION_FULL
:
729 cpu_smt_disable(false);
731 case L1TF_MITIGATION_FULL_FORCE
:
732 cpu_smt_disable(true);
736 #if CONFIG_PGTABLE_LEVELS == 2
737 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
741 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
742 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
743 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
747 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
750 static int __init
l1tf_cmdline(char *str
)
752 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
758 if (!strcmp(str
, "off"))
759 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
760 else if (!strcmp(str
, "flush,nowarn"))
761 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
762 else if (!strcmp(str
, "flush"))
763 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
764 else if (!strcmp(str
, "flush,nosmt"))
765 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
766 else if (!strcmp(str
, "full"))
767 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
768 else if (!strcmp(str
, "full,force"))
769 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
773 early_param("l1tf", l1tf_cmdline
);
779 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
781 #if IS_ENABLED(CONFIG_KVM_INTEL)
782 static const char *l1tf_vmx_states
[] = {
783 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
784 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
785 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
786 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
787 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
788 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
791 static ssize_t
l1tf_show_state(char *buf
)
793 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
794 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
796 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
797 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
798 cpu_smt_control
== CPU_SMT_ENABLED
))
799 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
800 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
802 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
803 l1tf_vmx_states
[l1tf_vmx_mitigation
],
804 cpu_smt_control
== CPU_SMT_ENABLED
? "vulnerable" : "disabled");
807 static ssize_t
l1tf_show_state(char *buf
)
809 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
813 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
814 char *buf
, unsigned int bug
)
816 if (!boot_cpu_has_bug(bug
))
817 return sprintf(buf
, "Not affected\n");
820 case X86_BUG_CPU_MELTDOWN
:
821 if (boot_cpu_has(X86_FEATURE_PTI
))
822 return sprintf(buf
, "Mitigation: PTI\n");
826 case X86_BUG_SPECTRE_V1
:
827 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
829 case X86_BUG_SPECTRE_V2
:
830 return sprintf(buf
, "%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
831 boot_cpu_has(X86_FEATURE_USE_IBPB
) ? ", IBPB" : "",
832 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
833 spectre_v2_module_string());
835 case X86_BUG_SPEC_STORE_BYPASS
:
836 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
839 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
840 return l1tf_show_state(buf
);
846 return sprintf(buf
, "Vulnerable\n");
849 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
851 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
854 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
856 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
859 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
861 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
864 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
866 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
869 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
871 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);