1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
34 static void __init
spectre_v2_select_mitigation(void);
35 static void __init
ssb_select_mitigation(void);
36 static void __init
l1tf_select_mitigation(void);
38 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
39 u64 x86_spec_ctrl_base
;
40 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
41 static DEFINE_MUTEX(spec_ctrl_mutex
);
44 * The vendor and possibly platform specific bits which can be modified in
47 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
50 * AMD specific MSR info for Speculative Store Bypass control.
51 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
53 u64 __ro_after_init x86_amd_ls_cfg_base
;
54 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
56 /* Control conditional STIPB in switch_to() */
57 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
59 void __init
check_bugs(void)
64 * identify_boot_cpu() initialized SMT support information, let the
67 cpu_smt_check_topology_early();
69 if (!IS_ENABLED(CONFIG_SMP
)) {
71 print_cpu_info(&boot_cpu_data
);
75 * Read the SPEC_CTRL MSR to account for reserved bits which may
76 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
77 * init code as it is not enumerated and depends on the family.
79 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
80 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
82 /* Allow STIBP in MSR_SPEC_CTRL if supported */
83 if (boot_cpu_has(X86_FEATURE_STIBP
))
84 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
86 /* Select the proper spectre mitigation before patching alternatives */
87 spectre_v2_select_mitigation();
90 * Select proper mitigation for any exposure to the Speculative Store
91 * Bypass vulnerability.
93 ssb_select_mitigation();
95 l1tf_select_mitigation();
99 * Check whether we are able to run this kernel safely on SMP.
101 * - i386 is no longer supported.
102 * - In order to run on anything without a TSC, we need to be
103 * compiled for a i486.
105 if (boot_cpu_data
.x86
< 4)
106 panic("Kernel requires i486+ for 'invlpg' and other features");
108 init_utsname()->machine
[1] =
109 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
110 alternative_instructions();
112 fpu__init_check_bugs();
113 #else /* CONFIG_X86_64 */
114 alternative_instructions();
117 * Make sure the first 2MB area is not mapped by huge pages
118 * There are typically fixed size MTRRs in there and overlapping
119 * MTRRs into large pages causes slow downs.
121 * Right now we don't do that with gbpages because there seems
122 * very little benefit for that case.
125 set_memory_4k((unsigned long)__va(0), 1);
130 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
132 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
133 struct thread_info
*ti
= current_thread_info();
135 /* Is MSR_SPEC_CTRL implemented ? */
136 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
138 * Restrict guest_spec_ctrl to supported values. Clear the
139 * modifiable bits in the host base value and or the
140 * modifiable bits from the guest value.
142 guestval
= hostval
& ~x86_spec_ctrl_mask
;
143 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
145 /* SSBD controlled in MSR_SPEC_CTRL */
146 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
147 static_cpu_has(X86_FEATURE_AMD_SSBD
))
148 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
150 /* Conditional STIBP enabled? */
151 if (static_branch_unlikely(&switch_to_cond_stibp
))
152 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
154 if (hostval
!= guestval
) {
155 msrval
= setguest
? guestval
: hostval
;
156 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
161 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
162 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
164 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
165 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
169 * If the host has SSBD mitigation enabled, force it in the host's
170 * virtual MSR value. If its not permanently enabled, evaluate
171 * current's TIF_SSBD thread flag.
173 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
174 hostval
= SPEC_CTRL_SSBD
;
176 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
178 /* Sanitize the guest value */
179 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
181 if (hostval
!= guestval
) {
184 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
185 ssbd_spec_ctrl_to_tif(hostval
);
187 speculation_ctrl_update(tif
);
190 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
192 static void x86_amd_ssb_disable(void)
194 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
196 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
197 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
198 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
199 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
203 #define pr_fmt(fmt) "Spectre V2 : " fmt
205 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
208 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
209 SPECTRE_V2_USER_NONE
;
212 static bool spectre_v2_bad_module
;
214 bool retpoline_module_ok(bool has_retpoline
)
216 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
219 pr_err("System may be vulnerable to spectre v2\n");
220 spectre_v2_bad_module
= true;
224 static inline const char *spectre_v2_module_string(void)
226 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
229 static inline const char *spectre_v2_module_string(void) { return ""; }
232 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
234 int len
= strlen(opt
);
236 return len
== arglen
&& !strncmp(arg
, opt
, len
);
239 /* The kernel command line selection for spectre v2 */
240 enum spectre_v2_mitigation_cmd
{
243 SPECTRE_V2_CMD_FORCE
,
244 SPECTRE_V2_CMD_RETPOLINE
,
245 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
246 SPECTRE_V2_CMD_RETPOLINE_AMD
,
249 enum spectre_v2_user_cmd
{
250 SPECTRE_V2_USER_CMD_NONE
,
251 SPECTRE_V2_USER_CMD_AUTO
,
252 SPECTRE_V2_USER_CMD_FORCE
,
255 static const char * const spectre_v2_user_strings
[] = {
256 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
257 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
260 static const struct {
262 enum spectre_v2_user_cmd cmd
;
264 } v2_user_options
[] __initdata
= {
265 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
266 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
267 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
270 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
272 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
273 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
276 static enum spectre_v2_user_cmd __init
277 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
283 case SPECTRE_V2_CMD_NONE
:
284 return SPECTRE_V2_USER_CMD_NONE
;
285 case SPECTRE_V2_CMD_FORCE
:
286 return SPECTRE_V2_USER_CMD_FORCE
;
291 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
294 return SPECTRE_V2_USER_CMD_AUTO
;
296 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
297 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
298 spec_v2_user_print_cond(v2_user_options
[i
].option
,
299 v2_user_options
[i
].secure
);
300 return v2_user_options
[i
].cmd
;
304 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
305 return SPECTRE_V2_USER_CMD_AUTO
;
309 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
311 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
312 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
314 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
317 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
318 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
319 smt_possible
= false;
321 switch (spectre_v2_parse_user_cmdline(v2_cmd
)) {
322 case SPECTRE_V2_USER_CMD_AUTO
:
323 case SPECTRE_V2_USER_CMD_NONE
:
325 case SPECTRE_V2_USER_CMD_FORCE
:
326 mode
= SPECTRE_V2_USER_STRICT
;
330 /* Initialize Indirect Branch Prediction Barrier */
331 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
332 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
333 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
336 /* If enhanced IBRS is enabled no STIPB required */
337 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
341 spectre_v2_user
= mode
;
342 /* Only print the STIBP mode when SMT possible */
344 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
347 static const char * const spectre_v2_strings
[] = {
348 [SPECTRE_V2_NONE
] = "Vulnerable",
349 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
350 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
351 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
354 static const struct {
356 enum spectre_v2_mitigation_cmd cmd
;
358 } mitigation_options
[] __initdata
= {
359 { "off", SPECTRE_V2_CMD_NONE
, false },
360 { "on", SPECTRE_V2_CMD_FORCE
, true },
361 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
362 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
363 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
364 { "auto", SPECTRE_V2_CMD_AUTO
, false },
367 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
369 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
370 pr_info("%s selected on command line.\n", reason
);
373 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
375 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
379 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
380 return SPECTRE_V2_CMD_NONE
;
382 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
384 return SPECTRE_V2_CMD_AUTO
;
386 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
387 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
389 cmd
= mitigation_options
[i
].cmd
;
393 if (i
>= ARRAY_SIZE(mitigation_options
)) {
394 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
395 return SPECTRE_V2_CMD_AUTO
;
398 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
399 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
400 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
401 !IS_ENABLED(CONFIG_RETPOLINE
)) {
402 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
403 return SPECTRE_V2_CMD_AUTO
;
406 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
407 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
408 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
409 return SPECTRE_V2_CMD_AUTO
;
412 spec_v2_print_cond(mitigation_options
[i
].option
,
413 mitigation_options
[i
].secure
);
417 static void __init
spectre_v2_select_mitigation(void)
419 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
420 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
423 * If the CPU is not affected and the command line mode is NONE or AUTO
424 * then nothing to do.
426 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
427 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
431 case SPECTRE_V2_CMD_NONE
:
434 case SPECTRE_V2_CMD_FORCE
:
435 case SPECTRE_V2_CMD_AUTO
:
436 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
437 mode
= SPECTRE_V2_IBRS_ENHANCED
;
438 /* Force it so VMEXIT will restore correctly */
439 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
440 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
441 goto specv2_set_mode
;
443 if (IS_ENABLED(CONFIG_RETPOLINE
))
446 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
447 if (IS_ENABLED(CONFIG_RETPOLINE
))
450 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
451 if (IS_ENABLED(CONFIG_RETPOLINE
))
452 goto retpoline_generic
;
454 case SPECTRE_V2_CMD_RETPOLINE
:
455 if (IS_ENABLED(CONFIG_RETPOLINE
))
459 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
463 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
465 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
466 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
467 goto retpoline_generic
;
469 mode
= SPECTRE_V2_RETPOLINE_AMD
;
470 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
471 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
474 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
475 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
479 spectre_v2_enabled
= mode
;
480 pr_info("%s\n", spectre_v2_strings
[mode
]);
483 * If spectre v2 protection has been enabled, unconditionally fill
484 * RSB during a context switch; this protects against two independent
487 * - RSB underflow (and switch to BTB) on Skylake+
488 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
490 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
491 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
494 * Retpoline means the kernel is safe because it has no indirect
495 * branches. Enhanced IBRS protects firmware too, so, enable restricted
496 * speculation around firmware calls only when Enhanced IBRS isn't
499 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
500 * the user might select retpoline on the kernel command line and if
501 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
502 * enable IBRS around firmware calls.
504 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
505 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
506 pr_info("Enabling Restricted Speculation for firmware calls\n");
509 /* Set up IBPB and STIBP depending on the general spectre V2 command */
510 spectre_v2_user_select_mitigation(cmd
);
512 /* Enable STIBP if appropriate */
516 static bool stibp_needed(void)
518 /* Enhanced IBRS makes using STIBP unnecessary. */
519 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
522 /* Check for strict user mitigation mode */
523 return spectre_v2_user
== SPECTRE_V2_USER_STRICT
;
526 static void update_stibp_msr(void *info
)
528 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
531 void arch_smt_update(void)
538 mutex_lock(&spec_ctrl_mutex
);
540 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
541 if (sched_smt_active())
542 mask
|= SPEC_CTRL_STIBP
;
544 if (mask
!= x86_spec_ctrl_base
) {
545 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
546 mask
& SPEC_CTRL_STIBP
? "Enabling" : "Disabling");
547 x86_spec_ctrl_base
= mask
;
548 on_each_cpu(update_stibp_msr
, NULL
, 1);
550 mutex_unlock(&spec_ctrl_mutex
);
554 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
556 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
558 /* The kernel command line selection */
559 enum ssb_mitigation_cmd
{
560 SPEC_STORE_BYPASS_CMD_NONE
,
561 SPEC_STORE_BYPASS_CMD_AUTO
,
562 SPEC_STORE_BYPASS_CMD_ON
,
563 SPEC_STORE_BYPASS_CMD_PRCTL
,
564 SPEC_STORE_BYPASS_CMD_SECCOMP
,
567 static const char * const ssb_strings
[] = {
568 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
569 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
570 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
571 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
574 static const struct {
576 enum ssb_mitigation_cmd cmd
;
577 } ssb_mitigation_options
[] __initdata
= {
578 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
579 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
580 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
581 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
582 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
585 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
587 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
591 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
592 return SPEC_STORE_BYPASS_CMD_NONE
;
594 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
597 return SPEC_STORE_BYPASS_CMD_AUTO
;
599 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
600 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
603 cmd
= ssb_mitigation_options
[i
].cmd
;
607 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
608 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
609 return SPEC_STORE_BYPASS_CMD_AUTO
;
616 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
618 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
619 enum ssb_mitigation_cmd cmd
;
621 if (!boot_cpu_has(X86_FEATURE_SSBD
))
624 cmd
= ssb_parse_cmdline();
625 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
626 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
627 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
631 case SPEC_STORE_BYPASS_CMD_AUTO
:
632 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
634 * Choose prctl+seccomp as the default mode if seccomp is
637 if (IS_ENABLED(CONFIG_SECCOMP
))
638 mode
= SPEC_STORE_BYPASS_SECCOMP
;
640 mode
= SPEC_STORE_BYPASS_PRCTL
;
642 case SPEC_STORE_BYPASS_CMD_ON
:
643 mode
= SPEC_STORE_BYPASS_DISABLE
;
645 case SPEC_STORE_BYPASS_CMD_PRCTL
:
646 mode
= SPEC_STORE_BYPASS_PRCTL
;
648 case SPEC_STORE_BYPASS_CMD_NONE
:
653 * We have three CPU feature flags that are in play here:
654 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
655 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
656 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
658 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
659 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
661 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
662 * use a completely different MSR and bit dependent on family.
664 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
665 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
666 x86_amd_ssb_disable();
668 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
669 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
670 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
677 static void ssb_select_mitigation(void)
679 ssb_mode
= __ssb_select_mitigation();
681 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
682 pr_info("%s\n", ssb_strings
[ssb_mode
]);
686 #define pr_fmt(fmt) "Speculation prctl: " fmt
688 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
692 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
693 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
698 /* If speculation is force disabled, enable is not allowed */
699 if (task_spec_ssb_force_disable(task
))
701 task_clear_spec_ssb_disable(task
);
702 update
= test_and_clear_tsk_thread_flag(task
, TIF_SSBD
);
704 case PR_SPEC_DISABLE
:
705 task_set_spec_ssb_disable(task
);
706 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
708 case PR_SPEC_FORCE_DISABLE
:
709 task_set_spec_ssb_disable(task
);
710 task_set_spec_ssb_force_disable(task
);
711 update
= !test_and_set_tsk_thread_flag(task
, TIF_SSBD
);
718 * If being set on non-current task, delay setting the CPU
719 * mitigation until it is next scheduled.
721 if (task
== current
&& update
)
722 speculation_ctrl_update_current();
727 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
731 case PR_SPEC_STORE_BYPASS
:
732 return ssb_prctl_set(task
, ctrl
);
738 #ifdef CONFIG_SECCOMP
739 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
741 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
742 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
746 static int ssb_prctl_get(struct task_struct
*task
)
749 case SPEC_STORE_BYPASS_DISABLE
:
750 return PR_SPEC_DISABLE
;
751 case SPEC_STORE_BYPASS_SECCOMP
:
752 case SPEC_STORE_BYPASS_PRCTL
:
753 if (task_spec_ssb_force_disable(task
))
754 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
755 if (task_spec_ssb_disable(task
))
756 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
757 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
759 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
760 return PR_SPEC_ENABLE
;
761 return PR_SPEC_NOT_AFFECTED
;
765 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
768 case PR_SPEC_STORE_BYPASS
:
769 return ssb_prctl_get(task
);
775 void x86_spec_ctrl_setup_ap(void)
777 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
778 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
780 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
781 x86_amd_ssb_disable();
785 #define pr_fmt(fmt) "L1TF: " fmt
787 /* Default mitigation for L1TF-affected CPUs */
788 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
789 #if IS_ENABLED(CONFIG_KVM_INTEL)
790 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
792 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
793 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
797 * These CPUs all support 44bits physical address space internally in the
798 * cache but CPUID can report a smaller number of physical address bits.
800 * The L1TF mitigation uses the top most address bit for the inversion of
801 * non present PTEs. When the installed memory reaches into the top most
802 * address bit due to memory holes, which has been observed on machines
803 * which report 36bits physical address bits and have 32G RAM installed,
804 * then the mitigation range check in l1tf_select_mitigation() triggers.
805 * This is a false positive because the mitigation is still possible due to
806 * the fact that the cache uses 44bit internally. Use the cache bits
807 * instead of the reported physical bits and adjust them on the affected
808 * machines to 44bit if the reported bits are less than 44.
810 static void override_cache_bits(struct cpuinfo_x86
*c
)
815 switch (c
->x86_model
) {
816 case INTEL_FAM6_NEHALEM
:
817 case INTEL_FAM6_WESTMERE
:
818 case INTEL_FAM6_SANDYBRIDGE
:
819 case INTEL_FAM6_IVYBRIDGE
:
820 case INTEL_FAM6_HASWELL_CORE
:
821 case INTEL_FAM6_HASWELL_ULT
:
822 case INTEL_FAM6_HASWELL_GT3E
:
823 case INTEL_FAM6_BROADWELL_CORE
:
824 case INTEL_FAM6_BROADWELL_GT3E
:
825 case INTEL_FAM6_SKYLAKE_MOBILE
:
826 case INTEL_FAM6_SKYLAKE_DESKTOP
:
827 case INTEL_FAM6_KABYLAKE_MOBILE
:
828 case INTEL_FAM6_KABYLAKE_DESKTOP
:
829 if (c
->x86_cache_bits
< 44)
830 c
->x86_cache_bits
= 44;
835 static void __init
l1tf_select_mitigation(void)
839 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
842 override_cache_bits(&boot_cpu_data
);
844 switch (l1tf_mitigation
) {
845 case L1TF_MITIGATION_OFF
:
846 case L1TF_MITIGATION_FLUSH_NOWARN
:
847 case L1TF_MITIGATION_FLUSH
:
849 case L1TF_MITIGATION_FLUSH_NOSMT
:
850 case L1TF_MITIGATION_FULL
:
851 cpu_smt_disable(false);
853 case L1TF_MITIGATION_FULL_FORCE
:
854 cpu_smt_disable(true);
858 #if CONFIG_PGTABLE_LEVELS == 2
859 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
863 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
864 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
865 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
869 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
872 static int __init
l1tf_cmdline(char *str
)
874 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
880 if (!strcmp(str
, "off"))
881 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
882 else if (!strcmp(str
, "flush,nowarn"))
883 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
884 else if (!strcmp(str
, "flush"))
885 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
886 else if (!strcmp(str
, "flush,nosmt"))
887 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
888 else if (!strcmp(str
, "full"))
889 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
890 else if (!strcmp(str
, "full,force"))
891 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
895 early_param("l1tf", l1tf_cmdline
);
901 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
903 #if IS_ENABLED(CONFIG_KVM_INTEL)
904 static const char * const l1tf_vmx_states
[] = {
905 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
906 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
907 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
908 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
909 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
910 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
913 static ssize_t
l1tf_show_state(char *buf
)
915 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
916 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
918 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
919 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
920 sched_smt_active())) {
921 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
922 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
925 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
926 l1tf_vmx_states
[l1tf_vmx_mitigation
],
927 sched_smt_active() ? "vulnerable" : "disabled");
930 static ssize_t
l1tf_show_state(char *buf
)
932 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
936 static char *stibp_state(void)
938 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
941 switch (spectre_v2_user
) {
942 case SPECTRE_V2_USER_NONE
:
943 return ", STIBP: disabled";
944 case SPECTRE_V2_USER_STRICT
:
945 return ", STIBP: forced";
950 static char *ibpb_state(void)
952 if (boot_cpu_has(X86_FEATURE_USE_IBPB
))
958 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
959 char *buf
, unsigned int bug
)
961 if (!boot_cpu_has_bug(bug
))
962 return sprintf(buf
, "Not affected\n");
965 case X86_BUG_CPU_MELTDOWN
:
966 if (boot_cpu_has(X86_FEATURE_PTI
))
967 return sprintf(buf
, "Mitigation: PTI\n");
971 case X86_BUG_SPECTRE_V1
:
972 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
974 case X86_BUG_SPECTRE_V2
:
975 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
977 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
979 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
980 spectre_v2_module_string());
982 case X86_BUG_SPEC_STORE_BYPASS
:
983 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
986 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
987 return l1tf_show_state(buf
);
993 return sprintf(buf
, "Vulnerable\n");
996 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
998 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1001 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1003 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1006 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1008 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1011 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1013 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1016 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1018 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);