1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
18 #include <asm/spec-ctrl.h>
19 #include <asm/cmdline.h>
21 #include <asm/processor.h>
22 #include <asm/processor-flags.h>
23 #include <asm/fpu/internal.h>
25 #include <asm/paravirt.h>
26 #include <asm/alternative.h>
27 #include <asm/pgtable.h>
28 #include <asm/set_memory.h>
29 #include <asm/intel-family.h>
31 static void __init
spectre_v2_select_mitigation(void);
32 static void __init
ssb_select_mitigation(void);
35 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
36 * writes to SPEC_CTRL contain whatever reserved bits have been set.
38 u64 __ro_after_init x86_spec_ctrl_base
;
41 * The vendor and possibly platform specific bits which can be modified in
44 static u64 __ro_after_init x86_spec_ctrl_mask
= ~SPEC_CTRL_IBRS
;
47 * AMD specific MSR info for Speculative Store Bypass control.
48 * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
50 u64 __ro_after_init x86_amd_ls_cfg_base
;
51 u64 __ro_after_init x86_amd_ls_cfg_rds_mask
;
53 void __init
check_bugs(void)
57 if (!IS_ENABLED(CONFIG_SMP
)) {
59 print_cpu_info(&boot_cpu_data
);
63 * Read the SPEC_CTRL MSR to account for reserved bits which may
64 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
65 * init code as it is not enumerated and depends on the family.
67 if (boot_cpu_has(X86_FEATURE_IBRS
))
68 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
70 /* Select the proper spectre mitigation before patching alternatives */
71 spectre_v2_select_mitigation();
74 * Select proper mitigation for any exposure to the Speculative Store
75 * Bypass vulnerability.
77 ssb_select_mitigation();
81 * Check whether we are able to run this kernel safely on SMP.
83 * - i386 is no longer supported.
84 * - In order to run on anything without a TSC, we need to be
85 * compiled for a i486.
87 if (boot_cpu_data
.x86
< 4)
88 panic("Kernel requires i486+ for 'invlpg' and other features");
90 init_utsname()->machine
[1] =
91 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
92 alternative_instructions();
94 fpu__init_check_bugs();
95 #else /* CONFIG_X86_64 */
96 alternative_instructions();
99 * Make sure the first 2MB area is not mapped by huge pages
100 * There are typically fixed size MTRRs in there and overlapping
101 * MTRRs into large pages causes slow downs.
103 * Right now we don't do that with gbpages because there seems
104 * very little benefit for that case.
107 set_memory_4k((unsigned long)__va(0), 1);
111 /* The kernel command line selection */
112 enum spectre_v2_mitigation_cmd
{
115 SPECTRE_V2_CMD_FORCE
,
116 SPECTRE_V2_CMD_RETPOLINE
,
117 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
118 SPECTRE_V2_CMD_RETPOLINE_AMD
,
121 static const char *spectre_v2_strings
[] = {
122 [SPECTRE_V2_NONE
] = "Vulnerable",
123 [SPECTRE_V2_RETPOLINE_MINIMAL
] = "Vulnerable: Minimal generic ASM retpoline",
124 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD
] = "Vulnerable: Minimal AMD ASM retpoline",
125 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
126 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
130 #define pr_fmt(fmt) "Spectre V2 : " fmt
132 static enum spectre_v2_mitigation spectre_v2_enabled
= SPECTRE_V2_NONE
;
134 void x86_spec_ctrl_set(u64 val
)
136 if (val
& x86_spec_ctrl_mask
)
137 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val
);
139 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
| val
);
141 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set
);
143 u64
x86_spec_ctrl_get_default(void)
145 u64 msrval
= x86_spec_ctrl_base
;
147 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
148 msrval
|= rds_tif_to_spec_ctrl(current_thread_info()->flags
);
151 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default
);
153 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl
)
155 u64 host
= x86_spec_ctrl_base
;
157 if (!boot_cpu_has(X86_FEATURE_IBRS
))
160 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
161 host
|= rds_tif_to_spec_ctrl(current_thread_info()->flags
);
163 if (host
!= guest_spec_ctrl
)
164 wrmsrl(MSR_IA32_SPEC_CTRL
, guest_spec_ctrl
);
166 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest
);
168 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl
)
170 u64 host
= x86_spec_ctrl_base
;
172 if (!boot_cpu_has(X86_FEATURE_IBRS
))
175 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
176 host
|= rds_tif_to_spec_ctrl(current_thread_info()->flags
);
178 if (host
!= guest_spec_ctrl
)
179 wrmsrl(MSR_IA32_SPEC_CTRL
, host
);
181 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host
);
183 static void x86_amd_rds_enable(void)
185 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_rds_mask
;
187 if (boot_cpu_has(X86_FEATURE_AMD_RDS
))
188 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
192 static bool spectre_v2_bad_module
;
194 bool retpoline_module_ok(bool has_retpoline
)
196 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
199 pr_err("System may be vulnerable to spectre v2\n");
200 spectre_v2_bad_module
= true;
204 static inline const char *spectre_v2_module_string(void)
206 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
209 static inline const char *spectre_v2_module_string(void) { return ""; }
212 static void __init
spec2_print_if_insecure(const char *reason
)
214 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
215 pr_info("%s selected on command line.\n", reason
);
218 static void __init
spec2_print_if_secure(const char *reason
)
220 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
221 pr_info("%s selected on command line.\n", reason
);
224 static inline bool retp_compiler(void)
226 return __is_defined(RETPOLINE
);
229 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
231 int len
= strlen(opt
);
233 return len
== arglen
&& !strncmp(arg
, opt
, len
);
236 static const struct {
238 enum spectre_v2_mitigation_cmd cmd
;
240 } mitigation_options
[] = {
241 { "off", SPECTRE_V2_CMD_NONE
, false },
242 { "on", SPECTRE_V2_CMD_FORCE
, true },
243 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
244 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
245 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
246 { "auto", SPECTRE_V2_CMD_AUTO
, false },
249 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
253 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
255 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
256 return SPECTRE_V2_CMD_NONE
;
258 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
260 return SPECTRE_V2_CMD_AUTO
;
262 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
263 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
265 cmd
= mitigation_options
[i
].cmd
;
269 if (i
>= ARRAY_SIZE(mitigation_options
)) {
270 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
271 return SPECTRE_V2_CMD_AUTO
;
275 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
276 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
277 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
278 !IS_ENABLED(CONFIG_RETPOLINE
)) {
279 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
280 return SPECTRE_V2_CMD_AUTO
;
283 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
284 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
285 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
286 return SPECTRE_V2_CMD_AUTO
;
289 if (mitigation_options
[i
].secure
)
290 spec2_print_if_secure(mitigation_options
[i
].option
);
292 spec2_print_if_insecure(mitigation_options
[i
].option
);
297 /* Check for Skylake-like CPUs (for RSB handling) */
298 static bool __init
is_skylake_era(void)
300 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
301 boot_cpu_data
.x86
== 6) {
302 switch (boot_cpu_data
.x86_model
) {
303 case INTEL_FAM6_SKYLAKE_MOBILE
:
304 case INTEL_FAM6_SKYLAKE_DESKTOP
:
305 case INTEL_FAM6_SKYLAKE_X
:
306 case INTEL_FAM6_KABYLAKE_MOBILE
:
307 case INTEL_FAM6_KABYLAKE_DESKTOP
:
314 static void __init
spectre_v2_select_mitigation(void)
316 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
317 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
320 * If the CPU is not affected and the command line mode is NONE or AUTO
321 * then nothing to do.
323 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
324 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
328 case SPECTRE_V2_CMD_NONE
:
331 case SPECTRE_V2_CMD_FORCE
:
332 case SPECTRE_V2_CMD_AUTO
:
333 if (IS_ENABLED(CONFIG_RETPOLINE
))
336 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
337 if (IS_ENABLED(CONFIG_RETPOLINE
))
340 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
341 if (IS_ENABLED(CONFIG_RETPOLINE
))
342 goto retpoline_generic
;
344 case SPECTRE_V2_CMD_RETPOLINE
:
345 if (IS_ENABLED(CONFIG_RETPOLINE
))
349 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
353 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
355 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
356 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
357 goto retpoline_generic
;
359 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD
:
360 SPECTRE_V2_RETPOLINE_MINIMAL_AMD
;
361 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
362 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
365 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC
:
366 SPECTRE_V2_RETPOLINE_MINIMAL
;
367 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
370 spectre_v2_enabled
= mode
;
371 pr_info("%s\n", spectre_v2_strings
[mode
]);
374 * If neither SMEP nor PTI are available, there is a risk of
375 * hitting userspace addresses in the RSB after a context switch
376 * from a shallow call stack to a deeper one. To prevent this fill
377 * the entire RSB, even when using IBRS.
379 * Skylake era CPUs have a separate issue with *underflow* of the
380 * RSB, when they will predict 'ret' targets from the generic BTB.
381 * The proper mitigation for this is IBRS. If IBRS is not supported
382 * or deactivated in favour of retpolines the RSB fill on context
383 * switch is required.
385 if ((!boot_cpu_has(X86_FEATURE_PTI
) &&
386 !boot_cpu_has(X86_FEATURE_SMEP
)) || is_skylake_era()) {
387 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
388 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
391 /* Initialize Indirect Branch Prediction Barrier if supported */
392 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
393 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
394 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
398 * Retpoline means the kernel is safe because it has no indirect
399 * branches. But firmware isn't, so use IBRS to protect that.
401 if (boot_cpu_has(X86_FEATURE_IBRS
)) {
402 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
403 pr_info("Enabling Restricted Speculation for firmware calls\n");
408 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
410 static enum ssb_mitigation ssb_mode
= SPEC_STORE_BYPASS_NONE
;
412 /* The kernel command line selection */
413 enum ssb_mitigation_cmd
{
414 SPEC_STORE_BYPASS_CMD_NONE
,
415 SPEC_STORE_BYPASS_CMD_AUTO
,
416 SPEC_STORE_BYPASS_CMD_ON
,
417 SPEC_STORE_BYPASS_CMD_PRCTL
,
420 static const char *ssb_strings
[] = {
421 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
422 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
423 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl"
426 static const struct {
428 enum ssb_mitigation_cmd cmd
;
429 } ssb_mitigation_options
[] = {
430 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
431 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
432 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
433 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
436 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
438 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
442 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
443 return SPEC_STORE_BYPASS_CMD_NONE
;
445 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
448 return SPEC_STORE_BYPASS_CMD_AUTO
;
450 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
451 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
454 cmd
= ssb_mitigation_options
[i
].cmd
;
458 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
459 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
460 return SPEC_STORE_BYPASS_CMD_AUTO
;
467 static enum ssb_mitigation_cmd __init
__ssb_select_mitigation(void)
469 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
470 enum ssb_mitigation_cmd cmd
;
472 if (!boot_cpu_has(X86_FEATURE_RDS
))
475 cmd
= ssb_parse_cmdline();
476 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
477 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
478 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
482 case SPEC_STORE_BYPASS_CMD_AUTO
:
483 /* Choose prctl as the default mode */
484 mode
= SPEC_STORE_BYPASS_PRCTL
;
486 case SPEC_STORE_BYPASS_CMD_ON
:
487 mode
= SPEC_STORE_BYPASS_DISABLE
;
489 case SPEC_STORE_BYPASS_CMD_PRCTL
:
490 mode
= SPEC_STORE_BYPASS_PRCTL
;
492 case SPEC_STORE_BYPASS_CMD_NONE
:
497 * We have three CPU feature flags that are in play here:
498 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
499 * - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
500 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
502 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
503 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
505 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
506 * a completely different MSR and bit dependent on family.
508 switch (boot_cpu_data
.x86_vendor
) {
509 case X86_VENDOR_INTEL
:
510 x86_spec_ctrl_base
|= SPEC_CTRL_RDS
;
511 x86_spec_ctrl_mask
&= ~SPEC_CTRL_RDS
;
512 x86_spec_ctrl_set(SPEC_CTRL_RDS
);
515 x86_amd_rds_enable();
523 static void ssb_select_mitigation()
525 ssb_mode
= __ssb_select_mitigation();
527 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
528 pr_info("%s\n", ssb_strings
[ssb_mode
]);
533 static int ssb_prctl_set(unsigned long ctrl
)
535 bool rds
= !!test_tsk_thread_flag(current
, TIF_RDS
);
537 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
)
540 if (ctrl
== PR_SPEC_ENABLE
)
541 clear_tsk_thread_flag(current
, TIF_RDS
);
543 set_tsk_thread_flag(current
, TIF_RDS
);
545 if (rds
!= !!test_tsk_thread_flag(current
, TIF_RDS
))
546 speculative_store_bypass_update();
551 static int ssb_prctl_get(void)
554 case SPEC_STORE_BYPASS_DISABLE
:
555 return PR_SPEC_DISABLE
;
556 case SPEC_STORE_BYPASS_PRCTL
:
557 if (test_tsk_thread_flag(current
, TIF_RDS
))
558 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
559 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
561 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
562 return PR_SPEC_ENABLE
;
563 return PR_SPEC_NOT_AFFECTED
;
567 int arch_prctl_spec_ctrl_set(unsigned long which
, unsigned long ctrl
)
569 if (ctrl
!= PR_SPEC_ENABLE
&& ctrl
!= PR_SPEC_DISABLE
)
573 case PR_SPEC_STORE_BYPASS
:
574 return ssb_prctl_set(ctrl
);
580 int arch_prctl_spec_ctrl_get(unsigned long which
)
583 case PR_SPEC_STORE_BYPASS
:
584 return ssb_prctl_get();
590 void x86_spec_ctrl_setup_ap(void)
592 if (boot_cpu_has(X86_FEATURE_IBRS
))
593 x86_spec_ctrl_set(x86_spec_ctrl_base
& ~x86_spec_ctrl_mask
);
595 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
596 x86_amd_rds_enable();
601 ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
602 char *buf
, unsigned int bug
)
604 if (!boot_cpu_has_bug(bug
))
605 return sprintf(buf
, "Not affected\n");
608 case X86_BUG_CPU_MELTDOWN
:
609 if (boot_cpu_has(X86_FEATURE_PTI
))
610 return sprintf(buf
, "Mitigation: PTI\n");
614 case X86_BUG_SPECTRE_V1
:
615 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
617 case X86_BUG_SPECTRE_V2
:
618 return sprintf(buf
, "%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
619 boot_cpu_has(X86_FEATURE_USE_IBPB
) ? ", IBPB" : "",
620 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
621 spectre_v2_module_string());
623 case X86_BUG_SPEC_STORE_BYPASS
:
624 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
630 return sprintf(buf
, "Vulnerable\n");
633 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
635 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
638 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
640 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
643 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
645 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
648 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
650 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);