1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
16 #include <asm/nospec-branch.h>
17 #include <asm/cmdline.h>
19 #include <asm/processor.h>
20 #include <asm/processor-flags.h>
21 #include <asm/fpu/internal.h>
23 #include <asm/paravirt.h>
24 #include <asm/alternative.h>
25 #include <asm/pgtable.h>
26 #include <asm/set_memory.h>
27 #include <asm/intel-family.h>
29 static void __init
spectre_v2_select_mitigation(void);
30 static void __init
ssb_select_mitigation(void);
33 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
34 * writes to SPEC_CTRL contain whatever reserved bits have been set.
36 static u64 __ro_after_init x86_spec_ctrl_base
;
39 * The vendor and possibly platform specific bits which can be modified in
42 static u64 __ro_after_init x86_spec_ctrl_mask
= ~SPEC_CTRL_IBRS
;
45 * AMD specific MSR info for Speculative Store Bypass control.
46 * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
48 u64 __ro_after_init x86_amd_ls_cfg_base
;
49 u64 __ro_after_init x86_amd_ls_cfg_rds_mask
;
51 void __init
check_bugs(void)
55 if (!IS_ENABLED(CONFIG_SMP
)) {
57 print_cpu_info(&boot_cpu_data
);
61 * Read the SPEC_CTRL MSR to account for reserved bits which may
62 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
63 * init code as it is not enumerated and depends on the family.
65 if (boot_cpu_has(X86_FEATURE_IBRS
))
66 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
68 /* Select the proper spectre mitigation before patching alternatives */
69 spectre_v2_select_mitigation();
72 * Select proper mitigation for any exposure to the Speculative Store
73 * Bypass vulnerability.
75 ssb_select_mitigation();
79 * Check whether we are able to run this kernel safely on SMP.
81 * - i386 is no longer supported.
82 * - In order to run on anything without a TSC, we need to be
83 * compiled for a i486.
85 if (boot_cpu_data
.x86
< 4)
86 panic("Kernel requires i486+ for 'invlpg' and other features");
88 init_utsname()->machine
[1] =
89 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
90 alternative_instructions();
92 fpu__init_check_bugs();
93 #else /* CONFIG_X86_64 */
94 alternative_instructions();
97 * Make sure the first 2MB area is not mapped by huge pages
98 * There are typically fixed size MTRRs in there and overlapping
99 * MTRRs into large pages causes slow downs.
101 * Right now we don't do that with gbpages because there seems
102 * very little benefit for that case.
105 set_memory_4k((unsigned long)__va(0), 1);
109 /* The kernel command line selection */
110 enum spectre_v2_mitigation_cmd
{
113 SPECTRE_V2_CMD_FORCE
,
114 SPECTRE_V2_CMD_RETPOLINE
,
115 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
116 SPECTRE_V2_CMD_RETPOLINE_AMD
,
119 static const char *spectre_v2_strings
[] = {
120 [SPECTRE_V2_NONE
] = "Vulnerable",
121 [SPECTRE_V2_RETPOLINE_MINIMAL
] = "Vulnerable: Minimal generic ASM retpoline",
122 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD
] = "Vulnerable: Minimal AMD ASM retpoline",
123 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
124 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
128 #define pr_fmt(fmt) "Spectre V2 : " fmt
130 static enum spectre_v2_mitigation spectre_v2_enabled
= SPECTRE_V2_NONE
;
132 void x86_spec_ctrl_set(u64 val
)
134 if (val
& x86_spec_ctrl_mask
)
135 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val
);
137 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
| val
);
139 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set
);
141 u64
x86_spec_ctrl_get_default(void)
143 return x86_spec_ctrl_base
;
145 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default
);
147 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl
)
149 if (!boot_cpu_has(X86_FEATURE_IBRS
))
151 if (x86_spec_ctrl_base
!= guest_spec_ctrl
)
152 wrmsrl(MSR_IA32_SPEC_CTRL
, guest_spec_ctrl
);
154 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest
);
156 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl
)
158 if (!boot_cpu_has(X86_FEATURE_IBRS
))
160 if (x86_spec_ctrl_base
!= guest_spec_ctrl
)
161 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
163 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host
);
165 static void x86_amd_rds_enable(void)
167 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_rds_mask
;
169 if (boot_cpu_has(X86_FEATURE_AMD_RDS
))
170 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
174 static bool spectre_v2_bad_module
;
176 bool retpoline_module_ok(bool has_retpoline
)
178 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
181 pr_err("System may be vulnerable to spectre v2\n");
182 spectre_v2_bad_module
= true;
186 static inline const char *spectre_v2_module_string(void)
188 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
191 static inline const char *spectre_v2_module_string(void) { return ""; }
194 static void __init
spec2_print_if_insecure(const char *reason
)
196 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
197 pr_info("%s selected on command line.\n", reason
);
200 static void __init
spec2_print_if_secure(const char *reason
)
202 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
203 pr_info("%s selected on command line.\n", reason
);
206 static inline bool retp_compiler(void)
208 return __is_defined(RETPOLINE
);
211 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
213 int len
= strlen(opt
);
215 return len
== arglen
&& !strncmp(arg
, opt
, len
);
218 static const struct {
220 enum spectre_v2_mitigation_cmd cmd
;
222 } mitigation_options
[] = {
223 { "off", SPECTRE_V2_CMD_NONE
, false },
224 { "on", SPECTRE_V2_CMD_FORCE
, true },
225 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
226 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
227 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
228 { "auto", SPECTRE_V2_CMD_AUTO
, false },
231 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
235 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
237 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
238 return SPECTRE_V2_CMD_NONE
;
240 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
242 return SPECTRE_V2_CMD_AUTO
;
244 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
245 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
247 cmd
= mitigation_options
[i
].cmd
;
251 if (i
>= ARRAY_SIZE(mitigation_options
)) {
252 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
253 return SPECTRE_V2_CMD_AUTO
;
257 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
258 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
259 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
260 !IS_ENABLED(CONFIG_RETPOLINE
)) {
261 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
262 return SPECTRE_V2_CMD_AUTO
;
265 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
266 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
267 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
268 return SPECTRE_V2_CMD_AUTO
;
271 if (mitigation_options
[i
].secure
)
272 spec2_print_if_secure(mitigation_options
[i
].option
);
274 spec2_print_if_insecure(mitigation_options
[i
].option
);
279 /* Check for Skylake-like CPUs (for RSB handling) */
280 static bool __init
is_skylake_era(void)
282 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
283 boot_cpu_data
.x86
== 6) {
284 switch (boot_cpu_data
.x86_model
) {
285 case INTEL_FAM6_SKYLAKE_MOBILE
:
286 case INTEL_FAM6_SKYLAKE_DESKTOP
:
287 case INTEL_FAM6_SKYLAKE_X
:
288 case INTEL_FAM6_KABYLAKE_MOBILE
:
289 case INTEL_FAM6_KABYLAKE_DESKTOP
:
296 static void __init
spectre_v2_select_mitigation(void)
298 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
299 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
302 * If the CPU is not affected and the command line mode is NONE or AUTO
303 * then nothing to do.
305 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
306 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
310 case SPECTRE_V2_CMD_NONE
:
313 case SPECTRE_V2_CMD_FORCE
:
314 case SPECTRE_V2_CMD_AUTO
:
315 if (IS_ENABLED(CONFIG_RETPOLINE
))
318 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
319 if (IS_ENABLED(CONFIG_RETPOLINE
))
322 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
323 if (IS_ENABLED(CONFIG_RETPOLINE
))
324 goto retpoline_generic
;
326 case SPECTRE_V2_CMD_RETPOLINE
:
327 if (IS_ENABLED(CONFIG_RETPOLINE
))
331 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
335 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
337 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
338 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
339 goto retpoline_generic
;
341 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD
:
342 SPECTRE_V2_RETPOLINE_MINIMAL_AMD
;
343 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
344 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
347 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC
:
348 SPECTRE_V2_RETPOLINE_MINIMAL
;
349 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
352 spectre_v2_enabled
= mode
;
353 pr_info("%s\n", spectre_v2_strings
[mode
]);
356 * If neither SMEP nor PTI are available, there is a risk of
357 * hitting userspace addresses in the RSB after a context switch
358 * from a shallow call stack to a deeper one. To prevent this fill
359 * the entire RSB, even when using IBRS.
361 * Skylake era CPUs have a separate issue with *underflow* of the
362 * RSB, when they will predict 'ret' targets from the generic BTB.
363 * The proper mitigation for this is IBRS. If IBRS is not supported
364 * or deactivated in favour of retpolines the RSB fill on context
365 * switch is required.
367 if ((!boot_cpu_has(X86_FEATURE_PTI
) &&
368 !boot_cpu_has(X86_FEATURE_SMEP
)) || is_skylake_era()) {
369 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
370 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
373 /* Initialize Indirect Branch Prediction Barrier if supported */
374 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
375 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
376 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
380 * Retpoline means the kernel is safe because it has no indirect
381 * branches. But firmware isn't, so use IBRS to protect that.
383 if (boot_cpu_has(X86_FEATURE_IBRS
)) {
384 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
385 pr_info("Enabling Restricted Speculation for firmware calls\n");
390 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
392 static enum ssb_mitigation ssb_mode
= SPEC_STORE_BYPASS_NONE
;
394 /* The kernel command line selection */
395 enum ssb_mitigation_cmd
{
396 SPEC_STORE_BYPASS_CMD_NONE
,
397 SPEC_STORE_BYPASS_CMD_AUTO
,
398 SPEC_STORE_BYPASS_CMD_ON
,
401 static const char *ssb_strings
[] = {
402 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
403 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled"
406 static const struct {
408 enum ssb_mitigation_cmd cmd
;
409 } ssb_mitigation_options
[] = {
410 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
411 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
412 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
415 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
417 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
421 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
422 return SPEC_STORE_BYPASS_CMD_NONE
;
424 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
427 return SPEC_STORE_BYPASS_CMD_AUTO
;
429 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
430 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
433 cmd
= ssb_mitigation_options
[i
].cmd
;
437 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
438 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
439 return SPEC_STORE_BYPASS_CMD_AUTO
;
446 static enum ssb_mitigation_cmd __init
__ssb_select_mitigation(void)
448 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
449 enum ssb_mitigation_cmd cmd
;
451 if (!boot_cpu_has(X86_FEATURE_RDS
))
454 cmd
= ssb_parse_cmdline();
455 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
456 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
457 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
461 case SPEC_STORE_BYPASS_CMD_AUTO
:
463 * AMD platforms by default don't need SSB mitigation.
465 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
467 case SPEC_STORE_BYPASS_CMD_ON
:
468 mode
= SPEC_STORE_BYPASS_DISABLE
;
470 case SPEC_STORE_BYPASS_CMD_NONE
:
475 * We have three CPU feature flags that are in play here:
476 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
477 * - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
478 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
480 if (mode
!= SPEC_STORE_BYPASS_NONE
) {
481 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
483 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
484 * a completely different MSR and bit dependent on family.
486 switch (boot_cpu_data
.x86_vendor
) {
487 case X86_VENDOR_INTEL
:
488 x86_spec_ctrl_base
|= SPEC_CTRL_RDS
;
489 x86_spec_ctrl_mask
&= ~SPEC_CTRL_RDS
;
490 x86_spec_ctrl_set(SPEC_CTRL_RDS
);
493 x86_amd_rds_enable();
501 static void ssb_select_mitigation()
503 ssb_mode
= __ssb_select_mitigation();
505 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
506 pr_info("%s\n", ssb_strings
[ssb_mode
]);
511 void x86_spec_ctrl_setup_ap(void)
513 if (boot_cpu_has(X86_FEATURE_IBRS
))
514 x86_spec_ctrl_set(x86_spec_ctrl_base
& ~x86_spec_ctrl_mask
);
516 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
517 x86_amd_rds_enable();
522 ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
523 char *buf
, unsigned int bug
)
525 if (!boot_cpu_has_bug(bug
))
526 return sprintf(buf
, "Not affected\n");
529 case X86_BUG_CPU_MELTDOWN
:
530 if (boot_cpu_has(X86_FEATURE_PTI
))
531 return sprintf(buf
, "Mitigation: PTI\n");
535 case X86_BUG_SPECTRE_V1
:
536 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
538 case X86_BUG_SPECTRE_V2
:
539 return sprintf(buf
, "%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
540 boot_cpu_has(X86_FEATURE_USE_IBPB
) ? ", IBPB" : "",
541 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
542 spectre_v2_module_string());
544 case X86_BUG_SPEC_STORE_BYPASS
:
545 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
551 return sprintf(buf
, "Vulnerable\n");
554 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
556 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
559 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
561 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
564 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
566 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
569 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
571 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);