1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
35 static void __init
spectre_v2_select_mitigation(void);
36 static void __init
ssb_select_mitigation(void);
37 static void __init
l1tf_select_mitigation(void);
38 static void __init
mds_select_mitigation(void);
40 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
41 u64 x86_spec_ctrl_base
;
42 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
43 static DEFINE_MUTEX(spec_ctrl_mutex
);
46 * The vendor and possibly platform specific bits which can be modified in
49 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
52 * AMD specific MSR info for Speculative Store Bypass control.
53 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
55 u64 __ro_after_init x86_amd_ls_cfg_base
;
56 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
58 /* Control conditional STIBP in switch_to() */
59 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
60 /* Control conditional IBPB in switch_mm() */
61 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
62 /* Control unconditional IBPB in switch_mm() */
63 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
65 /* Control MDS CPU buffer clear before returning to user space */
66 DEFINE_STATIC_KEY_FALSE(mds_user_clear
);
67 EXPORT_SYMBOL_GPL(mds_user_clear
);
68 /* Control MDS CPU buffer clear before idling (halt, mwait) */
69 DEFINE_STATIC_KEY_FALSE(mds_idle_clear
);
70 EXPORT_SYMBOL_GPL(mds_idle_clear
);
72 void __init
check_bugs(void)
77 * identify_boot_cpu() initialized SMT support information, let the
80 cpu_smt_check_topology_early();
82 if (!IS_ENABLED(CONFIG_SMP
)) {
84 print_cpu_info(&boot_cpu_data
);
88 * Read the SPEC_CTRL MSR to account for reserved bits which may
89 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
90 * init code as it is not enumerated and depends on the family.
92 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
93 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
95 /* Allow STIBP in MSR_SPEC_CTRL if supported */
96 if (boot_cpu_has(X86_FEATURE_STIBP
))
97 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
99 /* Select the proper spectre mitigation before patching alternatives */
100 spectre_v2_select_mitigation();
103 * Select proper mitigation for any exposure to the Speculative Store
104 * Bypass vulnerability.
106 ssb_select_mitigation();
108 l1tf_select_mitigation();
110 mds_select_mitigation();
114 * Check whether we are able to run this kernel safely on SMP.
116 * - i386 is no longer supported.
117 * - In order to run on anything without a TSC, we need to be
118 * compiled for a i486.
120 if (boot_cpu_data
.x86
< 4)
121 panic("Kernel requires i486+ for 'invlpg' and other features");
123 init_utsname()->machine
[1] =
124 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
125 alternative_instructions();
127 fpu__init_check_bugs();
128 #else /* CONFIG_X86_64 */
129 alternative_instructions();
132 * Make sure the first 2MB area is not mapped by huge pages
133 * There are typically fixed size MTRRs in there and overlapping
134 * MTRRs into large pages causes slow downs.
136 * Right now we don't do that with gbpages because there seems
137 * very little benefit for that case.
140 set_memory_4k((unsigned long)__va(0), 1);
145 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
147 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
148 struct thread_info
*ti
= current_thread_info();
150 /* Is MSR_SPEC_CTRL implemented ? */
151 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
153 * Restrict guest_spec_ctrl to supported values. Clear the
154 * modifiable bits in the host base value and or the
155 * modifiable bits from the guest value.
157 guestval
= hostval
& ~x86_spec_ctrl_mask
;
158 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
160 /* SSBD controlled in MSR_SPEC_CTRL */
161 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
162 static_cpu_has(X86_FEATURE_AMD_SSBD
))
163 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
165 /* Conditional STIBP enabled? */
166 if (static_branch_unlikely(&switch_to_cond_stibp
))
167 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
169 if (hostval
!= guestval
) {
170 msrval
= setguest
? guestval
: hostval
;
171 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
176 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
177 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
179 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
180 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
184 * If the host has SSBD mitigation enabled, force it in the host's
185 * virtual MSR value. If its not permanently enabled, evaluate
186 * current's TIF_SSBD thread flag.
188 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
189 hostval
= SPEC_CTRL_SSBD
;
191 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
193 /* Sanitize the guest value */
194 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
196 if (hostval
!= guestval
) {
199 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
200 ssbd_spec_ctrl_to_tif(hostval
);
202 speculation_ctrl_update(tif
);
205 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
207 static void x86_amd_ssb_disable(void)
209 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
211 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
212 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
213 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
214 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
218 #define pr_fmt(fmt) "MDS: " fmt
220 /* Default mitigation for L1TF-affected CPUs */
221 static enum mds_mitigations mds_mitigation __ro_after_init
= MDS_MITIGATION_FULL
;
223 static const char * const mds_strings
[] = {
224 [MDS_MITIGATION_OFF
] = "Vulnerable",
225 [MDS_MITIGATION_FULL
] = "Mitigation: Clear CPU buffers",
226 [MDS_MITIGATION_VMWERV
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
229 static void mds_select_mitigation(void)
231 if (!boot_cpu_has_bug(X86_BUG_MDS
)) {
232 mds_mitigation
= MDS_MITIGATION_OFF
;
236 if (mds_mitigation
== MDS_MITIGATION_FULL
) {
237 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR
))
238 mds_mitigation
= MDS_MITIGATION_VMWERV
;
239 static_branch_enable(&mds_user_clear
);
241 pr_info("%s\n", mds_strings
[mds_mitigation
]);
244 static int __init
mds_cmdline(char *str
)
246 if (!boot_cpu_has_bug(X86_BUG_MDS
))
252 if (!strcmp(str
, "off"))
253 mds_mitigation
= MDS_MITIGATION_OFF
;
254 else if (!strcmp(str
, "full"))
255 mds_mitigation
= MDS_MITIGATION_FULL
;
259 early_param("mds", mds_cmdline
);
262 #define pr_fmt(fmt) "Spectre V2 : " fmt
264 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
267 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
268 SPECTRE_V2_USER_NONE
;
270 #ifdef CONFIG_RETPOLINE
271 static bool spectre_v2_bad_module
;
273 bool retpoline_module_ok(bool has_retpoline
)
275 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
278 pr_err("System may be vulnerable to spectre v2\n");
279 spectre_v2_bad_module
= true;
283 static inline const char *spectre_v2_module_string(void)
285 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
288 static inline const char *spectre_v2_module_string(void) { return ""; }
291 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
293 int len
= strlen(opt
);
295 return len
== arglen
&& !strncmp(arg
, opt
, len
);
298 /* The kernel command line selection for spectre v2 */
299 enum spectre_v2_mitigation_cmd
{
302 SPECTRE_V2_CMD_FORCE
,
303 SPECTRE_V2_CMD_RETPOLINE
,
304 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
305 SPECTRE_V2_CMD_RETPOLINE_AMD
,
308 enum spectre_v2_user_cmd
{
309 SPECTRE_V2_USER_CMD_NONE
,
310 SPECTRE_V2_USER_CMD_AUTO
,
311 SPECTRE_V2_USER_CMD_FORCE
,
312 SPECTRE_V2_USER_CMD_PRCTL
,
313 SPECTRE_V2_USER_CMD_PRCTL_IBPB
,
314 SPECTRE_V2_USER_CMD_SECCOMP
,
315 SPECTRE_V2_USER_CMD_SECCOMP_IBPB
,
318 static const char * const spectre_v2_user_strings
[] = {
319 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
320 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
321 [SPECTRE_V2_USER_STRICT_PREFERRED
] = "User space: Mitigation: STIBP always-on protection",
322 [SPECTRE_V2_USER_PRCTL
] = "User space: Mitigation: STIBP via prctl",
323 [SPECTRE_V2_USER_SECCOMP
] = "User space: Mitigation: STIBP via seccomp and prctl",
326 static const struct {
328 enum spectre_v2_user_cmd cmd
;
330 } v2_user_options
[] __initdata
= {
331 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
332 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
333 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
334 { "prctl", SPECTRE_V2_USER_CMD_PRCTL
, false },
335 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB
, false },
336 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP
, false },
337 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB
, false },
340 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
342 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
343 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
346 static enum spectre_v2_user_cmd __init
347 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
353 case SPECTRE_V2_CMD_NONE
:
354 return SPECTRE_V2_USER_CMD_NONE
;
355 case SPECTRE_V2_CMD_FORCE
:
356 return SPECTRE_V2_USER_CMD_FORCE
;
361 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
364 return SPECTRE_V2_USER_CMD_AUTO
;
366 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
367 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
368 spec_v2_user_print_cond(v2_user_options
[i
].option
,
369 v2_user_options
[i
].secure
);
370 return v2_user_options
[i
].cmd
;
374 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
375 return SPECTRE_V2_USER_CMD_AUTO
;
379 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
381 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
382 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
383 enum spectre_v2_user_cmd cmd
;
385 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
388 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
389 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
390 smt_possible
= false;
392 cmd
= spectre_v2_parse_user_cmdline(v2_cmd
);
394 case SPECTRE_V2_USER_CMD_NONE
:
396 case SPECTRE_V2_USER_CMD_FORCE
:
397 mode
= SPECTRE_V2_USER_STRICT
;
399 case SPECTRE_V2_USER_CMD_PRCTL
:
400 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
401 mode
= SPECTRE_V2_USER_PRCTL
;
403 case SPECTRE_V2_USER_CMD_AUTO
:
404 case SPECTRE_V2_USER_CMD_SECCOMP
:
405 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
406 if (IS_ENABLED(CONFIG_SECCOMP
))
407 mode
= SPECTRE_V2_USER_SECCOMP
;
409 mode
= SPECTRE_V2_USER_PRCTL
;
414 * At this point, an STIBP mode other than "off" has been set.
415 * If STIBP support is not being forced, check if STIBP always-on
418 if (mode
!= SPECTRE_V2_USER_STRICT
&&
419 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON
))
420 mode
= SPECTRE_V2_USER_STRICT_PREFERRED
;
422 /* Initialize Indirect Branch Prediction Barrier */
423 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
424 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
427 case SPECTRE_V2_USER_CMD_FORCE
:
428 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
429 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
430 static_branch_enable(&switch_mm_always_ibpb
);
432 case SPECTRE_V2_USER_CMD_PRCTL
:
433 case SPECTRE_V2_USER_CMD_AUTO
:
434 case SPECTRE_V2_USER_CMD_SECCOMP
:
435 static_branch_enable(&switch_mm_cond_ibpb
);
441 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
442 static_key_enabled(&switch_mm_always_ibpb
) ?
443 "always-on" : "conditional");
446 /* If enhanced IBRS is enabled no STIBP required */
447 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
451 * If SMT is not possible or STIBP is not available clear the STIBP
454 if (!smt_possible
|| !boot_cpu_has(X86_FEATURE_STIBP
))
455 mode
= SPECTRE_V2_USER_NONE
;
457 spectre_v2_user
= mode
;
458 /* Only print the STIBP mode when SMT possible */
460 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
463 static const char * const spectre_v2_strings
[] = {
464 [SPECTRE_V2_NONE
] = "Vulnerable",
465 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
466 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
467 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
470 static const struct {
472 enum spectre_v2_mitigation_cmd cmd
;
474 } mitigation_options
[] __initdata
= {
475 { "off", SPECTRE_V2_CMD_NONE
, false },
476 { "on", SPECTRE_V2_CMD_FORCE
, true },
477 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
478 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
479 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
480 { "auto", SPECTRE_V2_CMD_AUTO
, false },
483 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
485 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
486 pr_info("%s selected on command line.\n", reason
);
489 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
491 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
495 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
496 return SPECTRE_V2_CMD_NONE
;
498 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
500 return SPECTRE_V2_CMD_AUTO
;
502 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
503 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
505 cmd
= mitigation_options
[i
].cmd
;
509 if (i
>= ARRAY_SIZE(mitigation_options
)) {
510 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
511 return SPECTRE_V2_CMD_AUTO
;
514 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
515 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
516 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
517 !IS_ENABLED(CONFIG_RETPOLINE
)) {
518 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
519 return SPECTRE_V2_CMD_AUTO
;
522 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
523 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
524 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
525 return SPECTRE_V2_CMD_AUTO
;
528 spec_v2_print_cond(mitigation_options
[i
].option
,
529 mitigation_options
[i
].secure
);
533 static void __init
spectre_v2_select_mitigation(void)
535 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
536 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
539 * If the CPU is not affected and the command line mode is NONE or AUTO
540 * then nothing to do.
542 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
543 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
547 case SPECTRE_V2_CMD_NONE
:
550 case SPECTRE_V2_CMD_FORCE
:
551 case SPECTRE_V2_CMD_AUTO
:
552 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
553 mode
= SPECTRE_V2_IBRS_ENHANCED
;
554 /* Force it so VMEXIT will restore correctly */
555 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
556 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
557 goto specv2_set_mode
;
559 if (IS_ENABLED(CONFIG_RETPOLINE
))
562 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
563 if (IS_ENABLED(CONFIG_RETPOLINE
))
566 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
567 if (IS_ENABLED(CONFIG_RETPOLINE
))
568 goto retpoline_generic
;
570 case SPECTRE_V2_CMD_RETPOLINE
:
571 if (IS_ENABLED(CONFIG_RETPOLINE
))
575 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
579 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
581 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
582 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
583 goto retpoline_generic
;
585 mode
= SPECTRE_V2_RETPOLINE_AMD
;
586 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
587 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
590 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
591 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
595 spectre_v2_enabled
= mode
;
596 pr_info("%s\n", spectre_v2_strings
[mode
]);
599 * If spectre v2 protection has been enabled, unconditionally fill
600 * RSB during a context switch; this protects against two independent
603 * - RSB underflow (and switch to BTB) on Skylake+
604 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
606 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
607 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
610 * Retpoline means the kernel is safe because it has no indirect
611 * branches. Enhanced IBRS protects firmware too, so, enable restricted
612 * speculation around firmware calls only when Enhanced IBRS isn't
615 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
616 * the user might select retpoline on the kernel command line and if
617 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
618 * enable IBRS around firmware calls.
620 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
621 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
622 pr_info("Enabling Restricted Speculation for firmware calls\n");
625 /* Set up IBPB and STIBP depending on the general spectre V2 command */
626 spectre_v2_user_select_mitigation(cmd
);
628 /* Enable STIBP if appropriate */
632 static void update_stibp_msr(void * __unused
)
634 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
637 /* Update x86_spec_ctrl_base in case SMT state changed. */
638 static void update_stibp_strict(void)
640 u64 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
642 if (sched_smt_active())
643 mask
|= SPEC_CTRL_STIBP
;
645 if (mask
== x86_spec_ctrl_base
)
648 pr_info("Update user space SMT mitigation: STIBP %s\n",
649 mask
& SPEC_CTRL_STIBP
? "always-on" : "off");
650 x86_spec_ctrl_base
= mask
;
651 on_each_cpu(update_stibp_msr
, NULL
, 1);
654 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
655 static void update_indir_branch_cond(void)
657 if (sched_smt_active())
658 static_branch_enable(&switch_to_cond_stibp
);
660 static_branch_disable(&switch_to_cond_stibp
);
663 /* Update the static key controlling the MDS CPU buffer clear in idle */
664 static void update_mds_branch_idle(void)
667 * Enable the idle clearing on CPUs which are affected only by
668 * MDBDS and not any other MDS variant. The other variants cannot
669 * be mitigated when SMT is enabled, so clearing the buffers on
670 * idle would be a window dressing exercise.
672 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY
))
675 if (sched_smt_active())
676 static_branch_enable(&mds_idle_clear
);
678 static_branch_disable(&mds_idle_clear
);
681 void arch_smt_update(void)
683 /* Enhanced IBRS implies STIBP. No update required. */
684 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
687 mutex_lock(&spec_ctrl_mutex
);
689 switch (spectre_v2_user
) {
690 case SPECTRE_V2_USER_NONE
:
692 case SPECTRE_V2_USER_STRICT
:
693 case SPECTRE_V2_USER_STRICT_PREFERRED
:
694 update_stibp_strict();
696 case SPECTRE_V2_USER_PRCTL
:
697 case SPECTRE_V2_USER_SECCOMP
:
698 update_indir_branch_cond();
702 switch(mds_mitigation
) {
703 case MDS_MITIGATION_FULL
:
704 case MDS_MITIGATION_VMWERV
:
705 update_mds_branch_idle();
707 case MDS_MITIGATION_OFF
:
711 mutex_unlock(&spec_ctrl_mutex
);
715 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
717 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
719 /* The kernel command line selection */
720 enum ssb_mitigation_cmd
{
721 SPEC_STORE_BYPASS_CMD_NONE
,
722 SPEC_STORE_BYPASS_CMD_AUTO
,
723 SPEC_STORE_BYPASS_CMD_ON
,
724 SPEC_STORE_BYPASS_CMD_PRCTL
,
725 SPEC_STORE_BYPASS_CMD_SECCOMP
,
728 static const char * const ssb_strings
[] = {
729 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
730 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
731 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
732 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
735 static const struct {
737 enum ssb_mitigation_cmd cmd
;
738 } ssb_mitigation_options
[] __initdata
= {
739 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
740 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
741 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
742 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
743 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
746 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
748 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
752 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
753 return SPEC_STORE_BYPASS_CMD_NONE
;
755 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
758 return SPEC_STORE_BYPASS_CMD_AUTO
;
760 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
761 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
764 cmd
= ssb_mitigation_options
[i
].cmd
;
768 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
769 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
770 return SPEC_STORE_BYPASS_CMD_AUTO
;
777 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
779 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
780 enum ssb_mitigation_cmd cmd
;
782 if (!boot_cpu_has(X86_FEATURE_SSBD
))
785 cmd
= ssb_parse_cmdline();
786 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
787 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
788 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
792 case SPEC_STORE_BYPASS_CMD_AUTO
:
793 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
795 * Choose prctl+seccomp as the default mode if seccomp is
798 if (IS_ENABLED(CONFIG_SECCOMP
))
799 mode
= SPEC_STORE_BYPASS_SECCOMP
;
801 mode
= SPEC_STORE_BYPASS_PRCTL
;
803 case SPEC_STORE_BYPASS_CMD_ON
:
804 mode
= SPEC_STORE_BYPASS_DISABLE
;
806 case SPEC_STORE_BYPASS_CMD_PRCTL
:
807 mode
= SPEC_STORE_BYPASS_PRCTL
;
809 case SPEC_STORE_BYPASS_CMD_NONE
:
814 * We have three CPU feature flags that are in play here:
815 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
816 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
817 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
819 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
820 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
822 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
823 * use a completely different MSR and bit dependent on family.
825 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
826 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
827 x86_amd_ssb_disable();
829 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
830 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
831 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
838 static void ssb_select_mitigation(void)
840 ssb_mode
= __ssb_select_mitigation();
842 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
843 pr_info("%s\n", ssb_strings
[ssb_mode
]);
847 #define pr_fmt(fmt) "Speculation prctl: " fmt
849 static void task_update_spec_tif(struct task_struct
*tsk
)
851 /* Force the update of the real TIF bits */
852 set_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
);
855 * Immediately update the speculation control MSRs for the current
856 * task, but for a non-current task delay setting the CPU
857 * mitigation until it is scheduled next.
859 * This can only happen for SECCOMP mitigation. For PRCTL it's
860 * always the current task.
863 speculation_ctrl_update_current();
866 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
868 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
869 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
874 /* If speculation is force disabled, enable is not allowed */
875 if (task_spec_ssb_force_disable(task
))
877 task_clear_spec_ssb_disable(task
);
878 task_update_spec_tif(task
);
880 case PR_SPEC_DISABLE
:
881 task_set_spec_ssb_disable(task
);
882 task_update_spec_tif(task
);
884 case PR_SPEC_FORCE_DISABLE
:
885 task_set_spec_ssb_disable(task
);
886 task_set_spec_ssb_force_disable(task
);
887 task_update_spec_tif(task
);
895 static int ib_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
899 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
902 * Indirect branch speculation is always disabled in strict
905 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
906 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
908 task_clear_spec_ib_disable(task
);
909 task_update_spec_tif(task
);
911 case PR_SPEC_DISABLE
:
912 case PR_SPEC_FORCE_DISABLE
:
914 * Indirect branch speculation is always allowed when
915 * mitigation is force disabled.
917 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
919 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
920 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
922 task_set_spec_ib_disable(task
);
923 if (ctrl
== PR_SPEC_FORCE_DISABLE
)
924 task_set_spec_ib_force_disable(task
);
925 task_update_spec_tif(task
);
933 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
937 case PR_SPEC_STORE_BYPASS
:
938 return ssb_prctl_set(task
, ctrl
);
939 case PR_SPEC_INDIRECT_BRANCH
:
940 return ib_prctl_set(task
, ctrl
);
946 #ifdef CONFIG_SECCOMP
947 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
949 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
950 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
951 if (spectre_v2_user
== SPECTRE_V2_USER_SECCOMP
)
952 ib_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
956 static int ssb_prctl_get(struct task_struct
*task
)
959 case SPEC_STORE_BYPASS_DISABLE
:
960 return PR_SPEC_DISABLE
;
961 case SPEC_STORE_BYPASS_SECCOMP
:
962 case SPEC_STORE_BYPASS_PRCTL
:
963 if (task_spec_ssb_force_disable(task
))
964 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
965 if (task_spec_ssb_disable(task
))
966 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
967 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
969 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
970 return PR_SPEC_ENABLE
;
971 return PR_SPEC_NOT_AFFECTED
;
975 static int ib_prctl_get(struct task_struct
*task
)
977 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
978 return PR_SPEC_NOT_AFFECTED
;
980 switch (spectre_v2_user
) {
981 case SPECTRE_V2_USER_NONE
:
982 return PR_SPEC_ENABLE
;
983 case SPECTRE_V2_USER_PRCTL
:
984 case SPECTRE_V2_USER_SECCOMP
:
985 if (task_spec_ib_force_disable(task
))
986 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
987 if (task_spec_ib_disable(task
))
988 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
989 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
990 case SPECTRE_V2_USER_STRICT
:
991 case SPECTRE_V2_USER_STRICT_PREFERRED
:
992 return PR_SPEC_DISABLE
;
994 return PR_SPEC_NOT_AFFECTED
;
998 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
1001 case PR_SPEC_STORE_BYPASS
:
1002 return ssb_prctl_get(task
);
1003 case PR_SPEC_INDIRECT_BRANCH
:
1004 return ib_prctl_get(task
);
1010 void x86_spec_ctrl_setup_ap(void)
1012 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
1013 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1015 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
1016 x86_amd_ssb_disable();
1020 #define pr_fmt(fmt) "L1TF: " fmt
1022 /* Default mitigation for L1TF-affected CPUs */
1023 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
1024 #if IS_ENABLED(CONFIG_KVM_INTEL)
1025 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
1027 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
1028 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
1032 * These CPUs all support 44bits physical address space internally in the
1033 * cache but CPUID can report a smaller number of physical address bits.
1035 * The L1TF mitigation uses the top most address bit for the inversion of
1036 * non present PTEs. When the installed memory reaches into the top most
1037 * address bit due to memory holes, which has been observed on machines
1038 * which report 36bits physical address bits and have 32G RAM installed,
1039 * then the mitigation range check in l1tf_select_mitigation() triggers.
1040 * This is a false positive because the mitigation is still possible due to
1041 * the fact that the cache uses 44bit internally. Use the cache bits
1042 * instead of the reported physical bits and adjust them on the affected
1043 * machines to 44bit if the reported bits are less than 44.
1045 static void override_cache_bits(struct cpuinfo_x86
*c
)
1050 switch (c
->x86_model
) {
1051 case INTEL_FAM6_NEHALEM
:
1052 case INTEL_FAM6_WESTMERE
:
1053 case INTEL_FAM6_SANDYBRIDGE
:
1054 case INTEL_FAM6_IVYBRIDGE
:
1055 case INTEL_FAM6_HASWELL_CORE
:
1056 case INTEL_FAM6_HASWELL_ULT
:
1057 case INTEL_FAM6_HASWELL_GT3E
:
1058 case INTEL_FAM6_BROADWELL_CORE
:
1059 case INTEL_FAM6_BROADWELL_GT3E
:
1060 case INTEL_FAM6_SKYLAKE_MOBILE
:
1061 case INTEL_FAM6_SKYLAKE_DESKTOP
:
1062 case INTEL_FAM6_KABYLAKE_MOBILE
:
1063 case INTEL_FAM6_KABYLAKE_DESKTOP
:
1064 if (c
->x86_cache_bits
< 44)
1065 c
->x86_cache_bits
= 44;
1070 static void __init
l1tf_select_mitigation(void)
1074 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1077 override_cache_bits(&boot_cpu_data
);
1079 switch (l1tf_mitigation
) {
1080 case L1TF_MITIGATION_OFF
:
1081 case L1TF_MITIGATION_FLUSH_NOWARN
:
1082 case L1TF_MITIGATION_FLUSH
:
1084 case L1TF_MITIGATION_FLUSH_NOSMT
:
1085 case L1TF_MITIGATION_FULL
:
1086 cpu_smt_disable(false);
1088 case L1TF_MITIGATION_FULL_FORCE
:
1089 cpu_smt_disable(true);
1093 #if CONFIG_PGTABLE_LEVELS == 2
1094 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1098 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
1099 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
1100 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1101 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1103 pr_info("However, doing so will make a part of your RAM unusable.\n");
1104 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
1108 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
1111 static int __init
l1tf_cmdline(char *str
)
1113 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1119 if (!strcmp(str
, "off"))
1120 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1121 else if (!strcmp(str
, "flush,nowarn"))
1122 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
1123 else if (!strcmp(str
, "flush"))
1124 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
1125 else if (!strcmp(str
, "flush,nosmt"))
1126 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1127 else if (!strcmp(str
, "full"))
1128 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
1129 else if (!strcmp(str
, "full,force"))
1130 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
1134 early_param("l1tf", l1tf_cmdline
);
1140 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1142 #if IS_ENABLED(CONFIG_KVM_INTEL)
1143 static const char * const l1tf_vmx_states
[] = {
1144 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
1145 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
1146 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
1147 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
1148 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
1149 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
1152 static ssize_t
l1tf_show_state(char *buf
)
1154 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
1155 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1157 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
1158 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
1159 sched_smt_active())) {
1160 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
1161 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
1164 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
1165 l1tf_vmx_states
[l1tf_vmx_mitigation
],
1166 sched_smt_active() ? "vulnerable" : "disabled");
1169 static ssize_t
l1tf_show_state(char *buf
)
1171 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1175 static ssize_t
mds_show_state(char *buf
)
1177 if (!hypervisor_is_type(X86_HYPER_NATIVE
)) {
1178 return sprintf(buf
, "%s; SMT Host state unknown\n",
1179 mds_strings
[mds_mitigation
]);
1182 if (boot_cpu_has(X86_BUG_MSBDS_ONLY
)) {
1183 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1184 sched_smt_active() ? "mitigated" : "disabled");
1187 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1188 sched_smt_active() ? "vulnerable" : "disabled");
1191 static char *stibp_state(void)
1193 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
1196 switch (spectre_v2_user
) {
1197 case SPECTRE_V2_USER_NONE
:
1198 return ", STIBP: disabled";
1199 case SPECTRE_V2_USER_STRICT
:
1200 return ", STIBP: forced";
1201 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1202 return ", STIBP: always-on";
1203 case SPECTRE_V2_USER_PRCTL
:
1204 case SPECTRE_V2_USER_SECCOMP
:
1205 if (static_key_enabled(&switch_to_cond_stibp
))
1206 return ", STIBP: conditional";
1211 static char *ibpb_state(void)
1213 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
1214 if (static_key_enabled(&switch_mm_always_ibpb
))
1215 return ", IBPB: always-on";
1216 if (static_key_enabled(&switch_mm_cond_ibpb
))
1217 return ", IBPB: conditional";
1218 return ", IBPB: disabled";
1223 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
1224 char *buf
, unsigned int bug
)
1226 if (!boot_cpu_has_bug(bug
))
1227 return sprintf(buf
, "Not affected\n");
1230 case X86_BUG_CPU_MELTDOWN
:
1231 if (boot_cpu_has(X86_FEATURE_PTI
))
1232 return sprintf(buf
, "Mitigation: PTI\n");
1236 case X86_BUG_SPECTRE_V1
:
1237 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
1239 case X86_BUG_SPECTRE_V2
:
1240 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
1242 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1244 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1245 spectre_v2_module_string());
1247 case X86_BUG_SPEC_STORE_BYPASS
:
1248 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1251 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1252 return l1tf_show_state(buf
);
1256 return mds_show_state(buf
);
1262 return sprintf(buf
, "Vulnerable\n");
1265 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1267 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1270 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1272 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1275 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1277 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1280 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1282 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1285 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1287 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);
1290 ssize_t
cpu_show_mds(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1292 return cpu_show_common(dev
, attr
, buf
, X86_BUG_MDS
);