arch/x86/kernel/cpu/mcheck/p5.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * P5 specific Machine Check Exception Reporting
   4  * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
   5  */
   6 #include <linux/interrupt.h>
   7 #include <linux/kernel.h>
   8 #include <linux/types.h>
   9 #include <linux/smp.h>
  10
  11 #include <asm/processor.h>
  12 #include <asm/traps.h>
  13 #include <asm/tlbflush.h>
  14 #include <asm/mce.h>
  15 #include <asm/msr.h>
  16
  17 /* By default disabled */
  18 int mce_p5_enabled __read_mostly;
  19
  20 /* Machine check handler for Pentium class Intel CPUs: */
  21 static void pentium_machine_check(struct pt_regs *regs, long error_code)
  22 {
  23         u32 loaddr, hi, lotype;
  24
  25         ist_enter(regs);
  26
  27         rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
  28         rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
  29
  30         pr_emerg("CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n",
  31                  smp_processor_id(), loaddr, lotype);
  32
  33         if (lotype & (1<<5)) {
  34                 pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
  35                          smp_processor_id());
  36         }
  37
  38         add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
  39
  40         ist_exit(regs);
  41 }
  42
  43 /* Set up machine check reporting for processors with Intel style MCE: */
  44 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
  45 {
  46         u32 l, h;
  47
  48         /* Default P5 to off as its often misconnected: */
  49         if (!mce_p5_enabled)
  50                 return;
  51
  52         /* Check for MCE support: */
  53         if (!cpu_has(c, X86_FEATURE_MCE))
  54                 return;
  55
  56         machine_check_vector = pentium_machine_check;
  57         /* Make sure the vector pointer is visible before we enable MCEs: */
  58         wmb();
  59
  60         /* Read registers before enabling: */
  61         rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
  62         rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
  63         pr_info("Intel old style machine check architecture supported.\n");
  64
  65         /* Enable MCE: */
  66         cr4_set_bits(X86_CR4_MCE);
  67         pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
  68                 smp_processor_id());
  69 }