2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
35 #include <asm/virtext.h>
38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40 MODULE_AUTHOR("Qumranet");
41 MODULE_LICENSE("GPL");
43 #define IOPM_ALLOC_ORDER 2
44 #define MSRPM_ALLOC_ORDER 1
46 #define SEG_TYPE_LDT 2
47 #define SEG_TYPE_BUSY_TSS16 3
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_FEATURE_SVML (1 << 2)
52 #define SVM_FEATURE_NRIP (1 << 3)
53 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61 static bool erratum_383_found __read_mostly
;
63 static const u32 host_save_user_msrs
[] = {
65 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
68 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
81 /* These are the merged vectors */
84 /* gpa pointers to the real vectors */
88 /* A VMEXIT is required but not yet emulated */
92 * If we vmexit during an instruction emulation we need this to restore
93 * the l1 guest rip after the emulation
95 unsigned long vmexit_rip
;
96 unsigned long vmexit_rsp
;
97 unsigned long vmexit_rax
;
99 /* cache for intercepts of the guest */
100 u16 intercept_cr_read
;
101 u16 intercept_cr_write
;
102 u16 intercept_dr_read
;
103 u16 intercept_dr_write
;
104 u32 intercept_exceptions
;
109 #define MSRPM_OFFSETS 16
110 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
113 struct kvm_vcpu vcpu
;
115 unsigned long vmcb_pa
;
116 struct svm_cpu_data
*svm_data
;
117 uint64_t asid_generation
;
118 uint64_t sysenter_esp
;
119 uint64_t sysenter_eip
;
123 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
128 struct nested_state nested
;
132 unsigned int3_injected
;
133 unsigned long int3_rip
;
136 #define MSR_INVALID 0xffffffffU
138 static struct svm_direct_access_msrs
{
139 u32 index
; /* Index of the MSR */
140 bool always
; /* True if intercept is always on */
141 } direct_access_msrs
[] = {
142 { .index
= MSR_STAR
, .always
= true },
143 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
145 { .index
= MSR_GS_BASE
, .always
= true },
146 { .index
= MSR_FS_BASE
, .always
= true },
147 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
148 { .index
= MSR_LSTAR
, .always
= true },
149 { .index
= MSR_CSTAR
, .always
= true },
150 { .index
= MSR_SYSCALL_MASK
, .always
= true },
152 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
153 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
154 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
155 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
156 { .index
= MSR_INVALID
, .always
= false },
159 /* enable NPT for AMD64 and X86 with PAE */
160 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
161 static bool npt_enabled
= true;
163 static bool npt_enabled
;
167 module_param(npt
, int, S_IRUGO
);
169 static int nested
= 1;
170 module_param(nested
, int, S_IRUGO
);
172 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
173 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
175 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
176 static int nested_svm_intercept(struct vcpu_svm
*svm
);
177 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
178 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
179 bool has_error_code
, u32 error_code
);
181 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
183 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
186 static inline bool is_nested(struct vcpu_svm
*svm
)
188 return svm
->nested
.vmcb
;
191 static inline void enable_gif(struct vcpu_svm
*svm
)
193 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
196 static inline void disable_gif(struct vcpu_svm
*svm
)
198 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
201 static inline bool gif_set(struct vcpu_svm
*svm
)
203 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
206 static unsigned long iopm_base
;
208 struct kvm_ldttss_desc
{
211 unsigned base1
:8, type
:5, dpl
:2, p
:1;
212 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
215 } __attribute__((packed
));
217 struct svm_cpu_data
{
223 struct kvm_ldttss_desc
*tss_desc
;
225 struct page
*save_area
;
228 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
229 static uint32_t svm_features
;
231 struct svm_init_data
{
236 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
238 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
239 #define MSRS_RANGE_SIZE 2048
240 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
242 static u32
svm_msrpm_offset(u32 msr
)
247 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
248 if (msr
< msrpm_ranges
[i
] ||
249 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
252 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
253 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
255 /* Now we have the u8 offset - but need the u32 offset */
259 /* MSR not in any range */
263 #define MAX_INST_SIZE 15
265 static inline u32
svm_has(u32 feat
)
267 return svm_features
& feat
;
270 static inline void clgi(void)
272 asm volatile (__ex(SVM_CLGI
));
275 static inline void stgi(void)
277 asm volatile (__ex(SVM_STGI
));
280 static inline void invlpga(unsigned long addr
, u32 asid
)
282 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
285 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
287 to_svm(vcpu
)->asid_generation
--;
290 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
292 force_new_asid(vcpu
);
295 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
297 vcpu
->arch
.efer
= efer
;
298 if (!npt_enabled
&& !(efer
& EFER_LMA
))
301 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
304 static int is_external_interrupt(u32 info
)
306 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
307 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
310 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
312 struct vcpu_svm
*svm
= to_svm(vcpu
);
315 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
316 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
320 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
322 struct vcpu_svm
*svm
= to_svm(vcpu
);
325 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
327 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
331 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
333 struct vcpu_svm
*svm
= to_svm(vcpu
);
335 if (svm
->vmcb
->control
.next_rip
!= 0)
336 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
338 if (!svm
->next_rip
) {
339 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
341 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
344 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
345 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
346 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
348 kvm_rip_write(vcpu
, svm
->next_rip
);
349 svm_set_interrupt_shadow(vcpu
, 0);
352 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
353 bool has_error_code
, u32 error_code
,
356 struct vcpu_svm
*svm
= to_svm(vcpu
);
359 * If we are within a nested VM we'd better #VMEXIT and let the guest
360 * handle the exception
363 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
366 if (nr
== BP_VECTOR
&& !svm_has(SVM_FEATURE_NRIP
)) {
367 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
370 * For guest debugging where we have to reinject #BP if some
371 * INT3 is guest-owned:
372 * Emulate nRIP by moving RIP forward. Will fail if injection
373 * raises a fault that is not intercepted. Still better than
374 * failing in all cases.
376 skip_emulated_instruction(&svm
->vcpu
);
377 rip
= kvm_rip_read(&svm
->vcpu
);
378 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
379 svm
->int3_injected
= rip
- old_rip
;
382 svm
->vmcb
->control
.event_inj
= nr
384 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
385 | SVM_EVTINJ_TYPE_EXEPT
;
386 svm
->vmcb
->control
.event_inj_err
= error_code
;
389 static void svm_init_erratum_383(void)
395 if (!cpu_has_amd_erratum(amd_erratum_383
))
398 /* Use _safe variants to not break nested virtualization */
399 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
405 low
= lower_32_bits(val
);
406 high
= upper_32_bits(val
);
408 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
410 erratum_383_found
= true;
413 static int has_svm(void)
417 if (!cpu_has_svm(&msg
)) {
418 printk(KERN_INFO
"has_svm: %s\n", msg
);
425 static void svm_hardware_disable(void *garbage
)
430 static int svm_hardware_enable(void *garbage
)
433 struct svm_cpu_data
*sd
;
435 struct desc_ptr gdt_descr
;
436 struct desc_struct
*gdt
;
437 int me
= raw_smp_processor_id();
439 rdmsrl(MSR_EFER
, efer
);
440 if (efer
& EFER_SVME
)
444 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
448 sd
= per_cpu(svm_data
, me
);
451 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
456 sd
->asid_generation
= 1;
457 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
458 sd
->next_asid
= sd
->max_asid
+ 1;
460 native_store_gdt(&gdt_descr
);
461 gdt
= (struct desc_struct
*)gdt_descr
.address
;
462 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
464 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
466 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
468 svm_init_erratum_383();
473 static void svm_cpu_uninit(int cpu
)
475 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
480 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
481 __free_page(sd
->save_area
);
485 static int svm_cpu_init(int cpu
)
487 struct svm_cpu_data
*sd
;
490 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
494 sd
->save_area
= alloc_page(GFP_KERNEL
);
499 per_cpu(svm_data
, cpu
) = sd
;
509 static bool valid_msr_intercept(u32 index
)
513 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
514 if (direct_access_msrs
[i
].index
== index
)
520 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
523 u8 bit_read
, bit_write
;
528 * If this warning triggers extend the direct_access_msrs list at the
529 * beginning of the file
531 WARN_ON(!valid_msr_intercept(msr
));
533 offset
= svm_msrpm_offset(msr
);
534 bit_read
= 2 * (msr
& 0x0f);
535 bit_write
= 2 * (msr
& 0x0f) + 1;
538 BUG_ON(offset
== MSR_INVALID
);
540 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
541 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
546 static void svm_vcpu_init_msrpm(u32
*msrpm
)
550 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
552 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
553 if (!direct_access_msrs
[i
].always
)
556 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
560 static void add_msr_offset(u32 offset
)
564 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
566 /* Offset already in list? */
567 if (msrpm_offsets
[i
] == offset
)
570 /* Slot used by another offset? */
571 if (msrpm_offsets
[i
] != MSR_INVALID
)
574 /* Add offset to list */
575 msrpm_offsets
[i
] = offset
;
581 * If this BUG triggers the msrpm_offsets table has an overflow. Just
582 * increase MSRPM_OFFSETS in this case.
587 static void init_msrpm_offsets(void)
591 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
593 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
596 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
597 BUG_ON(offset
== MSR_INVALID
);
599 add_msr_offset(offset
);
603 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
605 u32
*msrpm
= svm
->msrpm
;
607 svm
->vmcb
->control
.lbr_ctl
= 1;
608 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
609 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
610 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
611 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
614 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
616 u32
*msrpm
= svm
->msrpm
;
618 svm
->vmcb
->control
.lbr_ctl
= 0;
619 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
620 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
621 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
622 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
625 static __init
int svm_hardware_setup(void)
628 struct page
*iopm_pages
;
632 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
637 iopm_va
= page_address(iopm_pages
);
638 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
639 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
641 init_msrpm_offsets();
643 if (boot_cpu_has(X86_FEATURE_NX
))
644 kvm_enable_efer_bits(EFER_NX
);
646 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
647 kvm_enable_efer_bits(EFER_FFXSR
);
650 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
651 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
654 for_each_possible_cpu(cpu
) {
655 r
= svm_cpu_init(cpu
);
660 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
662 if (!svm_has(SVM_FEATURE_NPT
))
665 if (npt_enabled
&& !npt
) {
666 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
671 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
679 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
684 static __exit
void svm_hardware_unsetup(void)
688 for_each_possible_cpu(cpu
)
691 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
695 static void init_seg(struct vmcb_seg
*seg
)
698 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
699 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
704 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
707 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
712 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
714 struct vcpu_svm
*svm
= to_svm(vcpu
);
715 u64 g_tsc_offset
= 0;
717 if (is_nested(svm
)) {
718 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
719 svm
->nested
.hsave
->control
.tsc_offset
;
720 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
723 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
726 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
728 struct vcpu_svm
*svm
= to_svm(vcpu
);
730 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
732 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
735 static void init_vmcb(struct vcpu_svm
*svm
)
737 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
738 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
740 svm
->vcpu
.fpu_active
= 1;
742 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
746 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
751 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
760 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
769 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
774 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
775 (1ULL << INTERCEPT_NMI
) |
776 (1ULL << INTERCEPT_SMI
) |
777 (1ULL << INTERCEPT_SELECTIVE_CR0
) |
778 (1ULL << INTERCEPT_CPUID
) |
779 (1ULL << INTERCEPT_INVD
) |
780 (1ULL << INTERCEPT_HLT
) |
781 (1ULL << INTERCEPT_INVLPG
) |
782 (1ULL << INTERCEPT_INVLPGA
) |
783 (1ULL << INTERCEPT_IOIO_PROT
) |
784 (1ULL << INTERCEPT_MSR_PROT
) |
785 (1ULL << INTERCEPT_TASK_SWITCH
) |
786 (1ULL << INTERCEPT_SHUTDOWN
) |
787 (1ULL << INTERCEPT_VMRUN
) |
788 (1ULL << INTERCEPT_VMMCALL
) |
789 (1ULL << INTERCEPT_VMLOAD
) |
790 (1ULL << INTERCEPT_VMSAVE
) |
791 (1ULL << INTERCEPT_STGI
) |
792 (1ULL << INTERCEPT_CLGI
) |
793 (1ULL << INTERCEPT_SKINIT
) |
794 (1ULL << INTERCEPT_WBINVD
) |
795 (1ULL << INTERCEPT_MONITOR
) |
796 (1ULL << INTERCEPT_MWAIT
);
798 control
->iopm_base_pa
= iopm_base
;
799 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
800 control
->int_ctl
= V_INTR_MASKING_MASK
;
808 save
->cs
.selector
= 0xf000;
809 /* Executable/Readable Code Segment */
810 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
811 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
812 save
->cs
.limit
= 0xffff;
814 * cs.base should really be 0xffff0000, but vmx can't handle that, so
815 * be consistent with it.
817 * Replace when we have real mode working for vmx.
819 save
->cs
.base
= 0xf0000;
821 save
->gdtr
.limit
= 0xffff;
822 save
->idtr
.limit
= 0xffff;
824 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
825 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
827 svm_set_efer(&svm
->vcpu
, 0);
828 save
->dr6
= 0xffff0ff0;
831 save
->rip
= 0x0000fff0;
832 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
835 * This is the guest-visible cr0 value.
836 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
838 svm
->vcpu
.arch
.cr0
= 0;
839 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
841 save
->cr4
= X86_CR4_PAE
;
845 /* Setup VMCB for Nested Paging */
846 control
->nested_ctl
= 1;
847 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
848 (1ULL << INTERCEPT_INVLPG
));
849 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
850 control
->intercept_cr_read
&= ~INTERCEPT_CR3_MASK
;
851 control
->intercept_cr_write
&= ~INTERCEPT_CR3_MASK
;
852 save
->g_pat
= 0x0007040600070406ULL
;
856 force_new_asid(&svm
->vcpu
);
858 svm
->nested
.vmcb
= 0;
859 svm
->vcpu
.arch
.hflags
= 0;
861 if (svm_has(SVM_FEATURE_PAUSE_FILTER
)) {
862 control
->pause_filter_count
= 3000;
863 control
->intercept
|= (1ULL << INTERCEPT_PAUSE
);
869 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
871 struct vcpu_svm
*svm
= to_svm(vcpu
);
875 if (!kvm_vcpu_is_bsp(vcpu
)) {
876 kvm_rip_write(vcpu
, 0);
877 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
878 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
880 vcpu
->arch
.regs_avail
= ~0;
881 vcpu
->arch
.regs_dirty
= ~0;
886 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
888 struct vcpu_svm
*svm
;
890 struct page
*msrpm_pages
;
891 struct page
*hsave_page
;
892 struct page
*nested_msrpm_pages
;
895 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
901 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
906 page
= alloc_page(GFP_KERNEL
);
910 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
914 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
915 if (!nested_msrpm_pages
)
918 hsave_page
= alloc_page(GFP_KERNEL
);
922 svm
->nested
.hsave
= page_address(hsave_page
);
924 svm
->msrpm
= page_address(msrpm_pages
);
925 svm_vcpu_init_msrpm(svm
->msrpm
);
927 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
928 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
930 svm
->vmcb
= page_address(page
);
931 clear_page(svm
->vmcb
);
932 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
933 svm
->asid_generation
= 0;
935 kvm_write_tsc(&svm
->vcpu
, 0);
937 err
= fx_init(&svm
->vcpu
);
941 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
942 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
943 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
948 __free_page(hsave_page
);
950 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
952 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
956 kvm_vcpu_uninit(&svm
->vcpu
);
958 kmem_cache_free(kvm_vcpu_cache
, svm
);
963 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
965 struct vcpu_svm
*svm
= to_svm(vcpu
);
967 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
968 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
969 __free_page(virt_to_page(svm
->nested
.hsave
));
970 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
971 kvm_vcpu_uninit(vcpu
);
972 kmem_cache_free(kvm_vcpu_cache
, svm
);
975 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
977 struct vcpu_svm
*svm
= to_svm(vcpu
);
980 if (unlikely(cpu
!= vcpu
->cpu
)) {
981 svm
->asid_generation
= 0;
984 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
985 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
988 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
990 struct vcpu_svm
*svm
= to_svm(vcpu
);
993 ++vcpu
->stat
.host_state_reload
;
994 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
995 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
998 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1000 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1003 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1005 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1008 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1011 case VCPU_EXREG_PDPTR
:
1012 BUG_ON(!npt_enabled
);
1013 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, vcpu
->arch
.cr3
);
1020 static void svm_set_vintr(struct vcpu_svm
*svm
)
1022 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
1025 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1027 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
1030 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1032 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1035 case VCPU_SREG_CS
: return &save
->cs
;
1036 case VCPU_SREG_DS
: return &save
->ds
;
1037 case VCPU_SREG_ES
: return &save
->es
;
1038 case VCPU_SREG_FS
: return &save
->fs
;
1039 case VCPU_SREG_GS
: return &save
->gs
;
1040 case VCPU_SREG_SS
: return &save
->ss
;
1041 case VCPU_SREG_TR
: return &save
->tr
;
1042 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1048 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1050 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1055 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1056 struct kvm_segment
*var
, int seg
)
1058 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1060 var
->base
= s
->base
;
1061 var
->limit
= s
->limit
;
1062 var
->selector
= s
->selector
;
1063 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1064 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1065 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1066 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1067 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1068 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1069 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1070 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1073 * AMD's VMCB does not have an explicit unusable field, so emulate it
1074 * for cross vendor migration purposes by "not present"
1076 var
->unusable
= !var
->present
|| (var
->type
== 0);
1081 * SVM always stores 0 for the 'G' bit in the CS selector in
1082 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1083 * Intel's VMENTRY has a check on the 'G' bit.
1085 var
->g
= s
->limit
> 0xfffff;
1089 * Work around a bug where the busy flag in the tr selector
1099 * The accessed bit must always be set in the segment
1100 * descriptor cache, although it can be cleared in the
1101 * descriptor, the cached bit always remains at 1. Since
1102 * Intel has a check on this, set it here to support
1103 * cross-vendor migration.
1110 * On AMD CPUs sometimes the DB bit in the segment
1111 * descriptor is left as 1, although the whole segment has
1112 * been made unusable. Clear it here to pass an Intel VMX
1113 * entry check when cross vendor migrating.
1121 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1123 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1128 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1130 struct vcpu_svm
*svm
= to_svm(vcpu
);
1132 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1133 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1136 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1138 struct vcpu_svm
*svm
= to_svm(vcpu
);
1140 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1141 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1144 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1146 struct vcpu_svm
*svm
= to_svm(vcpu
);
1148 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1149 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1152 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1154 struct vcpu_svm
*svm
= to_svm(vcpu
);
1156 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1157 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1160 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1164 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1168 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1170 struct vmcb
*vmcb
= svm
->vmcb
;
1171 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1172 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1174 if (!svm
->vcpu
.fpu_active
)
1175 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1177 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1178 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1181 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1182 vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1183 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1184 if (is_nested(svm
)) {
1185 struct vmcb
*hsave
= svm
->nested
.hsave
;
1187 hsave
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1188 hsave
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1189 vmcb
->control
.intercept_cr_read
|= svm
->nested
.intercept_cr_read
;
1190 vmcb
->control
.intercept_cr_write
|= svm
->nested
.intercept_cr_write
;
1193 svm
->vmcb
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1194 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1195 if (is_nested(svm
)) {
1196 struct vmcb
*hsave
= svm
->nested
.hsave
;
1198 hsave
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1199 hsave
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1204 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1206 struct vcpu_svm
*svm
= to_svm(vcpu
);
1208 if (is_nested(svm
)) {
1210 * We are here because we run in nested mode, the host kvm
1211 * intercepts cr0 writes but the l1 hypervisor does not.
1212 * But the L1 hypervisor may intercept selective cr0 writes.
1213 * This needs to be checked here.
1215 unsigned long old
, new;
1217 /* Remove bits that would trigger a real cr0 write intercept */
1218 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1219 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1222 /* cr0 write with ts and mp unchanged */
1223 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1224 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
) {
1225 svm
->nested
.vmexit_rip
= kvm_rip_read(vcpu
);
1226 svm
->nested
.vmexit_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
1227 svm
->nested
.vmexit_rax
= kvm_register_read(vcpu
, VCPU_REGS_RAX
);
1233 #ifdef CONFIG_X86_64
1234 if (vcpu
->arch
.efer
& EFER_LME
) {
1235 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1236 vcpu
->arch
.efer
|= EFER_LMA
;
1237 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1240 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1241 vcpu
->arch
.efer
&= ~EFER_LMA
;
1242 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1246 vcpu
->arch
.cr0
= cr0
;
1249 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1251 if (!vcpu
->fpu_active
)
1254 * re-enable caching here because the QEMU bios
1255 * does not do it - this results in some delay at
1258 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1259 svm
->vmcb
->save
.cr0
= cr0
;
1260 update_cr0_intercept(svm
);
1263 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1265 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1266 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1268 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1269 force_new_asid(vcpu
);
1271 vcpu
->arch
.cr4
= cr4
;
1274 cr4
|= host_cr4_mce
;
1275 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1278 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1279 struct kvm_segment
*var
, int seg
)
1281 struct vcpu_svm
*svm
= to_svm(vcpu
);
1282 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1284 s
->base
= var
->base
;
1285 s
->limit
= var
->limit
;
1286 s
->selector
= var
->selector
;
1290 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1291 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1292 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1293 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1294 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1295 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1296 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1297 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1299 if (seg
== VCPU_SREG_CS
)
1301 = (svm
->vmcb
->save
.cs
.attrib
1302 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1306 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1308 struct vcpu_svm
*svm
= to_svm(vcpu
);
1310 svm
->vmcb
->control
.intercept_exceptions
&=
1311 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1313 if (svm
->nmi_singlestep
)
1314 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1316 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1317 if (vcpu
->guest_debug
&
1318 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1319 svm
->vmcb
->control
.intercept_exceptions
|=
1321 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1322 svm
->vmcb
->control
.intercept_exceptions
|=
1325 vcpu
->guest_debug
= 0;
1328 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1330 struct vcpu_svm
*svm
= to_svm(vcpu
);
1332 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1333 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1335 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1337 update_db_intercept(vcpu
);
1340 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1342 #ifdef CONFIG_X86_64
1343 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1347 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1349 #ifdef CONFIG_X86_64
1350 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1354 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1356 if (sd
->next_asid
> sd
->max_asid
) {
1357 ++sd
->asid_generation
;
1359 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1362 svm
->asid_generation
= sd
->asid_generation
;
1363 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1366 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1368 struct vcpu_svm
*svm
= to_svm(vcpu
);
1370 svm
->vmcb
->save
.dr7
= value
;
1373 static int pf_interception(struct vcpu_svm
*svm
)
1378 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1379 error_code
= svm
->vmcb
->control
.exit_info_1
;
1381 trace_kvm_page_fault(fault_address
, error_code
);
1382 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1383 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1384 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1387 static int db_interception(struct vcpu_svm
*svm
)
1389 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1391 if (!(svm
->vcpu
.guest_debug
&
1392 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1393 !svm
->nmi_singlestep
) {
1394 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1398 if (svm
->nmi_singlestep
) {
1399 svm
->nmi_singlestep
= false;
1400 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1401 svm
->vmcb
->save
.rflags
&=
1402 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1403 update_db_intercept(&svm
->vcpu
);
1406 if (svm
->vcpu
.guest_debug
&
1407 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1408 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1409 kvm_run
->debug
.arch
.pc
=
1410 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1411 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1418 static int bp_interception(struct vcpu_svm
*svm
)
1420 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1422 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1423 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1424 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1428 static int ud_interception(struct vcpu_svm
*svm
)
1432 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1433 if (er
!= EMULATE_DONE
)
1434 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1438 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1440 struct vcpu_svm
*svm
= to_svm(vcpu
);
1443 if (is_nested(svm
)) {
1446 h_excp
= svm
->nested
.hsave
->control
.intercept_exceptions
;
1447 n_excp
= svm
->nested
.intercept_exceptions
;
1448 h_excp
&= ~(1 << NM_VECTOR
);
1449 excp
= h_excp
| n_excp
;
1451 excp
= svm
->vmcb
->control
.intercept_exceptions
;
1452 excp
&= ~(1 << NM_VECTOR
);
1455 svm
->vmcb
->control
.intercept_exceptions
= excp
;
1457 svm
->vcpu
.fpu_active
= 1;
1458 update_cr0_intercept(svm
);
1461 static int nm_interception(struct vcpu_svm
*svm
)
1463 svm_fpu_activate(&svm
->vcpu
);
1467 static bool is_erratum_383(void)
1472 if (!erratum_383_found
)
1475 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1479 /* Bit 62 may or may not be set for this mce */
1480 value
&= ~(1ULL << 62);
1482 if (value
!= 0xb600000000010015ULL
)
1485 /* Clear MCi_STATUS registers */
1486 for (i
= 0; i
< 6; ++i
)
1487 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1489 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1493 value
&= ~(1ULL << 2);
1494 low
= lower_32_bits(value
);
1495 high
= upper_32_bits(value
);
1497 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1500 /* Flush tlb to evict multi-match entries */
1506 static void svm_handle_mce(struct vcpu_svm
*svm
)
1508 if (is_erratum_383()) {
1510 * Erratum 383 triggered. Guest state is corrupt so kill the
1513 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1515 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1521 * On an #MC intercept the MCE handler is not called automatically in
1522 * the host. So do it by hand here.
1526 /* not sure if we ever come back to this point */
1531 static int mc_interception(struct vcpu_svm
*svm
)
1536 static int shutdown_interception(struct vcpu_svm
*svm
)
1538 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1541 * VMCB is undefined after a SHUTDOWN intercept
1542 * so reinitialize it.
1544 clear_page(svm
->vmcb
);
1547 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1551 static int io_interception(struct vcpu_svm
*svm
)
1553 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1554 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1555 int size
, in
, string
;
1558 ++svm
->vcpu
.stat
.io_exits
;
1559 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1560 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1562 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
1564 port
= io_info
>> 16;
1565 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1566 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1567 skip_emulated_instruction(&svm
->vcpu
);
1569 return kvm_fast_pio_out(vcpu
, size
, port
);
1572 static int nmi_interception(struct vcpu_svm
*svm
)
1577 static int intr_interception(struct vcpu_svm
*svm
)
1579 ++svm
->vcpu
.stat
.irq_exits
;
1583 static int nop_on_interception(struct vcpu_svm
*svm
)
1588 static int halt_interception(struct vcpu_svm
*svm
)
1590 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1591 skip_emulated_instruction(&svm
->vcpu
);
1592 return kvm_emulate_halt(&svm
->vcpu
);
1595 static int vmmcall_interception(struct vcpu_svm
*svm
)
1597 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1598 skip_emulated_instruction(&svm
->vcpu
);
1599 kvm_emulate_hypercall(&svm
->vcpu
);
1603 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1605 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1606 || !is_paging(&svm
->vcpu
)) {
1607 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1611 if (svm
->vmcb
->save
.cpl
) {
1612 kvm_inject_gp(&svm
->vcpu
, 0);
1619 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1620 bool has_error_code
, u32 error_code
)
1624 if (!is_nested(svm
))
1627 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1628 svm
->vmcb
->control
.exit_code_hi
= 0;
1629 svm
->vmcb
->control
.exit_info_1
= error_code
;
1630 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1632 vmexit
= nested_svm_intercept(svm
);
1633 if (vmexit
== NESTED_EXIT_DONE
)
1634 svm
->nested
.exit_required
= true;
1639 /* This function returns true if it is save to enable the irq window */
1640 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1642 if (!is_nested(svm
))
1645 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1648 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1651 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1652 svm
->vmcb
->control
.exit_info_1
= 0;
1653 svm
->vmcb
->control
.exit_info_2
= 0;
1655 if (svm
->nested
.intercept
& 1ULL) {
1657 * The #vmexit can't be emulated here directly because this
1658 * code path runs with irqs and preemtion disabled. A
1659 * #vmexit emulation might sleep. Only signal request for
1662 svm
->nested
.exit_required
= true;
1663 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1670 /* This function returns true if it is save to enable the nmi window */
1671 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1673 if (!is_nested(svm
))
1676 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1679 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1680 svm
->nested
.exit_required
= true;
1685 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1691 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1692 if (is_error_page(page
))
1700 kvm_release_page_clean(page
);
1701 kvm_inject_gp(&svm
->vcpu
, 0);
1706 static void nested_svm_unmap(struct page
*page
)
1709 kvm_release_page_dirty(page
);
1712 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1718 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1719 return NESTED_EXIT_HOST
;
1721 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1722 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1726 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1729 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1732 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1734 u32 offset
, msr
, value
;
1737 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1738 return NESTED_EXIT_HOST
;
1740 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1741 offset
= svm_msrpm_offset(msr
);
1742 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1743 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1745 if (offset
== MSR_INVALID
)
1746 return NESTED_EXIT_DONE
;
1748 /* Offset is in 32 bit units but need in 8 bit units */
1751 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1752 return NESTED_EXIT_DONE
;
1754 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1757 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1759 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1761 switch (exit_code
) {
1764 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1765 return NESTED_EXIT_HOST
;
1767 /* For now we are always handling NPFs when using them */
1769 return NESTED_EXIT_HOST
;
1771 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1772 /* When we're shadowing, trap PFs */
1774 return NESTED_EXIT_HOST
;
1776 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1777 nm_interception(svm
);
1783 return NESTED_EXIT_CONTINUE
;
1787 * If this function returns true, this #vmexit was already handled
1789 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1791 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1792 int vmexit
= NESTED_EXIT_HOST
;
1794 switch (exit_code
) {
1796 vmexit
= nested_svm_exit_handled_msr(svm
);
1799 vmexit
= nested_svm_intercept_ioio(svm
);
1801 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1802 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1803 if (svm
->nested
.intercept_cr_read
& cr_bits
)
1804 vmexit
= NESTED_EXIT_DONE
;
1807 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1808 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1809 if (svm
->nested
.intercept_cr_write
& cr_bits
)
1810 vmexit
= NESTED_EXIT_DONE
;
1813 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1814 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1815 if (svm
->nested
.intercept_dr_read
& dr_bits
)
1816 vmexit
= NESTED_EXIT_DONE
;
1819 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1820 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1821 if (svm
->nested
.intercept_dr_write
& dr_bits
)
1822 vmexit
= NESTED_EXIT_DONE
;
1825 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1826 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1827 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1828 vmexit
= NESTED_EXIT_DONE
;
1831 case SVM_EXIT_ERR
: {
1832 vmexit
= NESTED_EXIT_DONE
;
1836 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1837 if (svm
->nested
.intercept
& exit_bits
)
1838 vmexit
= NESTED_EXIT_DONE
;
1845 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
1849 vmexit
= nested_svm_intercept(svm
);
1851 if (vmexit
== NESTED_EXIT_DONE
)
1852 nested_svm_vmexit(svm
);
1857 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
1859 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
1860 struct vmcb_control_area
*from
= &from_vmcb
->control
;
1862 dst
->intercept_cr_read
= from
->intercept_cr_read
;
1863 dst
->intercept_cr_write
= from
->intercept_cr_write
;
1864 dst
->intercept_dr_read
= from
->intercept_dr_read
;
1865 dst
->intercept_dr_write
= from
->intercept_dr_write
;
1866 dst
->intercept_exceptions
= from
->intercept_exceptions
;
1867 dst
->intercept
= from
->intercept
;
1868 dst
->iopm_base_pa
= from
->iopm_base_pa
;
1869 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
1870 dst
->tsc_offset
= from
->tsc_offset
;
1871 dst
->asid
= from
->asid
;
1872 dst
->tlb_ctl
= from
->tlb_ctl
;
1873 dst
->int_ctl
= from
->int_ctl
;
1874 dst
->int_vector
= from
->int_vector
;
1875 dst
->int_state
= from
->int_state
;
1876 dst
->exit_code
= from
->exit_code
;
1877 dst
->exit_code_hi
= from
->exit_code_hi
;
1878 dst
->exit_info_1
= from
->exit_info_1
;
1879 dst
->exit_info_2
= from
->exit_info_2
;
1880 dst
->exit_int_info
= from
->exit_int_info
;
1881 dst
->exit_int_info_err
= from
->exit_int_info_err
;
1882 dst
->nested_ctl
= from
->nested_ctl
;
1883 dst
->event_inj
= from
->event_inj
;
1884 dst
->event_inj_err
= from
->event_inj_err
;
1885 dst
->nested_cr3
= from
->nested_cr3
;
1886 dst
->lbr_ctl
= from
->lbr_ctl
;
1889 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1891 struct vmcb
*nested_vmcb
;
1892 struct vmcb
*hsave
= svm
->nested
.hsave
;
1893 struct vmcb
*vmcb
= svm
->vmcb
;
1896 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
1897 vmcb
->control
.exit_info_1
,
1898 vmcb
->control
.exit_info_2
,
1899 vmcb
->control
.exit_int_info
,
1900 vmcb
->control
.exit_int_info_err
);
1902 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
1906 /* Exit nested SVM mode */
1907 svm
->nested
.vmcb
= 0;
1909 /* Give the current vmcb to the guest */
1912 nested_vmcb
->save
.es
= vmcb
->save
.es
;
1913 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
1914 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
1915 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
1916 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
1917 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
1918 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
1919 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1920 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1921 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
1922 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1923 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
1924 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
1925 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
1926 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
1927 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
1928 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
1929 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
1931 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
1932 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
1933 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
1934 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
1935 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
1936 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
1937 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
1938 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
1939 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
1940 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
1943 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1944 * to make sure that we do not lose injected events. So check event_inj
1945 * here and copy it to exit_int_info if it is valid.
1946 * Exit_int_info and event_inj can't be both valid because the case
1947 * below only happens on a VMRUN instruction intercept which has
1948 * no valid exit_int_info set.
1950 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
1951 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
1953 nc
->exit_int_info
= vmcb
->control
.event_inj
;
1954 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
1957 nested_vmcb
->control
.tlb_ctl
= 0;
1958 nested_vmcb
->control
.event_inj
= 0;
1959 nested_vmcb
->control
.event_inj_err
= 0;
1961 /* We always set V_INTR_MASKING and remember the old value in hflags */
1962 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1963 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1965 /* Restore the original control entries */
1966 copy_vmcb_control_area(vmcb
, hsave
);
1968 kvm_clear_exception_queue(&svm
->vcpu
);
1969 kvm_clear_interrupt_queue(&svm
->vcpu
);
1971 /* Restore selected save entries */
1972 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1973 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1974 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1975 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1976 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1977 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1978 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1979 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1980 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1981 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1983 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1984 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1986 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1988 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1989 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1990 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1991 svm
->vmcb
->save
.dr7
= 0;
1992 svm
->vmcb
->save
.cpl
= 0;
1993 svm
->vmcb
->control
.exit_int_info
= 0;
1995 nested_svm_unmap(page
);
1997 kvm_mmu_reset_context(&svm
->vcpu
);
1998 kvm_mmu_load(&svm
->vcpu
);
2003 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2006 * This function merges the msr permission bitmaps of kvm and the
2007 * nested vmcb. It is omptimized in that it only merges the parts where
2008 * the kvm msr permission bitmap may contain zero bits
2012 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2015 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2019 if (msrpm_offsets
[i
] == 0xffffffff)
2022 p
= msrpm_offsets
[i
];
2023 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2025 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2028 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2031 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2036 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2038 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2041 if (vmcb
->control
.asid
== 0)
2047 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2049 struct vmcb
*nested_vmcb
;
2050 struct vmcb
*hsave
= svm
->nested
.hsave
;
2051 struct vmcb
*vmcb
= svm
->vmcb
;
2055 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2057 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2061 if (!nested_vmcb_checks(nested_vmcb
)) {
2062 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2063 nested_vmcb
->control
.exit_code_hi
= 0;
2064 nested_vmcb
->control
.exit_info_1
= 0;
2065 nested_vmcb
->control
.exit_info_2
= 0;
2067 nested_svm_unmap(page
);
2072 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2073 nested_vmcb
->save
.rip
,
2074 nested_vmcb
->control
.int_ctl
,
2075 nested_vmcb
->control
.event_inj
,
2076 nested_vmcb
->control
.nested_ctl
);
2078 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr_read
,
2079 nested_vmcb
->control
.intercept_cr_write
,
2080 nested_vmcb
->control
.intercept_exceptions
,
2081 nested_vmcb
->control
.intercept
);
2083 /* Clear internal status */
2084 kvm_clear_exception_queue(&svm
->vcpu
);
2085 kvm_clear_interrupt_queue(&svm
->vcpu
);
2088 * Save the old vmcb, so we don't need to pick what we save, but can
2089 * restore everything when a VMEXIT occurs
2091 hsave
->save
.es
= vmcb
->save
.es
;
2092 hsave
->save
.cs
= vmcb
->save
.cs
;
2093 hsave
->save
.ss
= vmcb
->save
.ss
;
2094 hsave
->save
.ds
= vmcb
->save
.ds
;
2095 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2096 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2097 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2098 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2099 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2100 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2101 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2102 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2103 hsave
->save
.rax
= vmcb
->save
.rax
;
2105 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2107 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2109 copy_vmcb_control_area(hsave
, vmcb
);
2111 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2112 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2114 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2116 /* Load the nested guest state */
2117 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2118 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2119 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2120 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2121 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2122 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2123 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2124 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2125 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2126 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2128 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2129 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2131 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2133 /* Guest paging mode is active - reset mmu */
2134 kvm_mmu_reset_context(&svm
->vcpu
);
2136 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2137 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2138 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2139 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2141 /* In case we don't even reach vcpu_run, the fields are not updated */
2142 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2143 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2144 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2145 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2146 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2147 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2149 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2150 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2152 /* cache intercepts */
2153 svm
->nested
.intercept_cr_read
= nested_vmcb
->control
.intercept_cr_read
;
2154 svm
->nested
.intercept_cr_write
= nested_vmcb
->control
.intercept_cr_write
;
2155 svm
->nested
.intercept_dr_read
= nested_vmcb
->control
.intercept_dr_read
;
2156 svm
->nested
.intercept_dr_write
= nested_vmcb
->control
.intercept_dr_write
;
2157 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2158 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2160 force_new_asid(&svm
->vcpu
);
2161 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2162 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2163 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2165 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2167 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2168 /* We only want the cr8 intercept bits of the guest */
2169 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR8_MASK
;
2170 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2173 /* We don't want to see VMMCALLs from a nested guest */
2174 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VMMCALL
);
2177 * We don't want a nested guest to be more powerful than the guest, so
2178 * all intercepts are ORed
2180 svm
->vmcb
->control
.intercept_cr_read
|=
2181 nested_vmcb
->control
.intercept_cr_read
;
2182 svm
->vmcb
->control
.intercept_cr_write
|=
2183 nested_vmcb
->control
.intercept_cr_write
;
2184 svm
->vmcb
->control
.intercept_dr_read
|=
2185 nested_vmcb
->control
.intercept_dr_read
;
2186 svm
->vmcb
->control
.intercept_dr_write
|=
2187 nested_vmcb
->control
.intercept_dr_write
;
2188 svm
->vmcb
->control
.intercept_exceptions
|=
2189 nested_vmcb
->control
.intercept_exceptions
;
2191 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
2193 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2194 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2195 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2196 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2197 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2198 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2200 nested_svm_unmap(page
);
2202 /* nested_vmcb is our indicator if nested SVM is activated */
2203 svm
->nested
.vmcb
= vmcb_gpa
;
2210 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2212 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2213 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2214 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2215 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2216 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2217 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2218 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2219 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2220 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2221 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2222 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2223 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2226 static int vmload_interception(struct vcpu_svm
*svm
)
2228 struct vmcb
*nested_vmcb
;
2231 if (nested_svm_check_permissions(svm
))
2234 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2235 skip_emulated_instruction(&svm
->vcpu
);
2237 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2241 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2242 nested_svm_unmap(page
);
2247 static int vmsave_interception(struct vcpu_svm
*svm
)
2249 struct vmcb
*nested_vmcb
;
2252 if (nested_svm_check_permissions(svm
))
2255 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2256 skip_emulated_instruction(&svm
->vcpu
);
2258 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2262 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2263 nested_svm_unmap(page
);
2268 static int vmrun_interception(struct vcpu_svm
*svm
)
2270 if (nested_svm_check_permissions(svm
))
2273 /* Save rip after vmrun instruction */
2274 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2276 if (!nested_svm_vmrun(svm
))
2279 if (!nested_svm_vmrun_msrpm(svm
))
2286 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2287 svm
->vmcb
->control
.exit_code_hi
= 0;
2288 svm
->vmcb
->control
.exit_info_1
= 0;
2289 svm
->vmcb
->control
.exit_info_2
= 0;
2291 nested_svm_vmexit(svm
);
2296 static int stgi_interception(struct vcpu_svm
*svm
)
2298 if (nested_svm_check_permissions(svm
))
2301 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2302 skip_emulated_instruction(&svm
->vcpu
);
2309 static int clgi_interception(struct vcpu_svm
*svm
)
2311 if (nested_svm_check_permissions(svm
))
2314 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2315 skip_emulated_instruction(&svm
->vcpu
);
2319 /* After a CLGI no interrupts should come */
2320 svm_clear_vintr(svm
);
2321 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2326 static int invlpga_interception(struct vcpu_svm
*svm
)
2328 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2330 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2331 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2333 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2334 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2336 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2337 skip_emulated_instruction(&svm
->vcpu
);
2341 static int skinit_interception(struct vcpu_svm
*svm
)
2343 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2345 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2349 static int invalid_op_interception(struct vcpu_svm
*svm
)
2351 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2355 static int task_switch_interception(struct vcpu_svm
*svm
)
2359 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2360 SVM_EXITINTINFO_TYPE_MASK
;
2361 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2363 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2365 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2366 bool has_error_code
= false;
2369 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2371 if (svm
->vmcb
->control
.exit_info_2
&
2372 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2373 reason
= TASK_SWITCH_IRET
;
2374 else if (svm
->vmcb
->control
.exit_info_2
&
2375 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2376 reason
= TASK_SWITCH_JMP
;
2378 reason
= TASK_SWITCH_GATE
;
2380 reason
= TASK_SWITCH_CALL
;
2382 if (reason
== TASK_SWITCH_GATE
) {
2384 case SVM_EXITINTINFO_TYPE_NMI
:
2385 svm
->vcpu
.arch
.nmi_injected
= false;
2387 case SVM_EXITINTINFO_TYPE_EXEPT
:
2388 if (svm
->vmcb
->control
.exit_info_2
&
2389 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2390 has_error_code
= true;
2392 (u32
)svm
->vmcb
->control
.exit_info_2
;
2394 kvm_clear_exception_queue(&svm
->vcpu
);
2396 case SVM_EXITINTINFO_TYPE_INTR
:
2397 kvm_clear_interrupt_queue(&svm
->vcpu
);
2404 if (reason
!= TASK_SWITCH_GATE
||
2405 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2406 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2407 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2408 skip_emulated_instruction(&svm
->vcpu
);
2410 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2411 has_error_code
, error_code
) == EMULATE_FAIL
) {
2412 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2413 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2414 svm
->vcpu
.run
->internal
.ndata
= 0;
2420 static int cpuid_interception(struct vcpu_svm
*svm
)
2422 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2423 kvm_emulate_cpuid(&svm
->vcpu
);
2427 static int iret_interception(struct vcpu_svm
*svm
)
2429 ++svm
->vcpu
.stat
.nmi_window_exits
;
2430 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_IRET
);
2431 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2435 static int invlpg_interception(struct vcpu_svm
*svm
)
2437 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2440 static int emulate_on_interception(struct vcpu_svm
*svm
)
2442 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2445 static int cr0_write_interception(struct vcpu_svm
*svm
)
2447 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2450 r
= emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2452 if (svm
->nested
.vmexit_rip
) {
2453 kvm_register_write(vcpu
, VCPU_REGS_RIP
, svm
->nested
.vmexit_rip
);
2454 kvm_register_write(vcpu
, VCPU_REGS_RSP
, svm
->nested
.vmexit_rsp
);
2455 kvm_register_write(vcpu
, VCPU_REGS_RAX
, svm
->nested
.vmexit_rax
);
2456 svm
->nested
.vmexit_rip
= 0;
2459 return r
== EMULATE_DONE
;
2462 static int cr8_write_interception(struct vcpu_svm
*svm
)
2464 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2466 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2467 /* instruction emulation calls kvm_set_cr8() */
2468 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2469 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2470 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2473 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2475 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2479 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2481 struct vcpu_svm
*svm
= to_svm(vcpu
);
2484 case MSR_IA32_TSC
: {
2488 tsc_offset
= svm
->nested
.hsave
->control
.tsc_offset
;
2490 tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2492 *data
= tsc_offset
+ native_read_tsc();
2496 *data
= svm
->vmcb
->save
.star
;
2498 #ifdef CONFIG_X86_64
2500 *data
= svm
->vmcb
->save
.lstar
;
2503 *data
= svm
->vmcb
->save
.cstar
;
2505 case MSR_KERNEL_GS_BASE
:
2506 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2508 case MSR_SYSCALL_MASK
:
2509 *data
= svm
->vmcb
->save
.sfmask
;
2512 case MSR_IA32_SYSENTER_CS
:
2513 *data
= svm
->vmcb
->save
.sysenter_cs
;
2515 case MSR_IA32_SYSENTER_EIP
:
2516 *data
= svm
->sysenter_eip
;
2518 case MSR_IA32_SYSENTER_ESP
:
2519 *data
= svm
->sysenter_esp
;
2522 * Nobody will change the following 5 values in the VMCB so we can
2523 * safely return them on rdmsr. They will always be 0 until LBRV is
2526 case MSR_IA32_DEBUGCTLMSR
:
2527 *data
= svm
->vmcb
->save
.dbgctl
;
2529 case MSR_IA32_LASTBRANCHFROMIP
:
2530 *data
= svm
->vmcb
->save
.br_from
;
2532 case MSR_IA32_LASTBRANCHTOIP
:
2533 *data
= svm
->vmcb
->save
.br_to
;
2535 case MSR_IA32_LASTINTFROMIP
:
2536 *data
= svm
->vmcb
->save
.last_excp_from
;
2538 case MSR_IA32_LASTINTTOIP
:
2539 *data
= svm
->vmcb
->save
.last_excp_to
;
2541 case MSR_VM_HSAVE_PA
:
2542 *data
= svm
->nested
.hsave_msr
;
2545 *data
= svm
->nested
.vm_cr_msr
;
2547 case MSR_IA32_UCODE_REV
:
2551 return kvm_get_msr_common(vcpu
, ecx
, data
);
2556 static int rdmsr_interception(struct vcpu_svm
*svm
)
2558 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2561 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2562 trace_kvm_msr_read_ex(ecx
);
2563 kvm_inject_gp(&svm
->vcpu
, 0);
2565 trace_kvm_msr_read(ecx
, data
);
2567 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2568 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2569 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2570 skip_emulated_instruction(&svm
->vcpu
);
2575 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2577 struct vcpu_svm
*svm
= to_svm(vcpu
);
2578 int svm_dis
, chg_mask
;
2580 if (data
& ~SVM_VM_CR_VALID_MASK
)
2583 chg_mask
= SVM_VM_CR_VALID_MASK
;
2585 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2586 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2588 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2589 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2591 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2593 /* check for svm_disable while efer.svme is set */
2594 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2600 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2602 struct vcpu_svm
*svm
= to_svm(vcpu
);
2606 kvm_write_tsc(vcpu
, data
);
2609 svm
->vmcb
->save
.star
= data
;
2611 #ifdef CONFIG_X86_64
2613 svm
->vmcb
->save
.lstar
= data
;
2616 svm
->vmcb
->save
.cstar
= data
;
2618 case MSR_KERNEL_GS_BASE
:
2619 svm
->vmcb
->save
.kernel_gs_base
= data
;
2621 case MSR_SYSCALL_MASK
:
2622 svm
->vmcb
->save
.sfmask
= data
;
2625 case MSR_IA32_SYSENTER_CS
:
2626 svm
->vmcb
->save
.sysenter_cs
= data
;
2628 case MSR_IA32_SYSENTER_EIP
:
2629 svm
->sysenter_eip
= data
;
2630 svm
->vmcb
->save
.sysenter_eip
= data
;
2632 case MSR_IA32_SYSENTER_ESP
:
2633 svm
->sysenter_esp
= data
;
2634 svm
->vmcb
->save
.sysenter_esp
= data
;
2636 case MSR_IA32_DEBUGCTLMSR
:
2637 if (!svm_has(SVM_FEATURE_LBRV
)) {
2638 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2642 if (data
& DEBUGCTL_RESERVED_BITS
)
2645 svm
->vmcb
->save
.dbgctl
= data
;
2646 if (data
& (1ULL<<0))
2647 svm_enable_lbrv(svm
);
2649 svm_disable_lbrv(svm
);
2651 case MSR_VM_HSAVE_PA
:
2652 svm
->nested
.hsave_msr
= data
;
2655 return svm_set_vm_cr(vcpu
, data
);
2657 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2660 return kvm_set_msr_common(vcpu
, ecx
, data
);
2665 static int wrmsr_interception(struct vcpu_svm
*svm
)
2667 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2668 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2669 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2672 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2673 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2674 trace_kvm_msr_write_ex(ecx
, data
);
2675 kvm_inject_gp(&svm
->vcpu
, 0);
2677 trace_kvm_msr_write(ecx
, data
);
2678 skip_emulated_instruction(&svm
->vcpu
);
2683 static int msr_interception(struct vcpu_svm
*svm
)
2685 if (svm
->vmcb
->control
.exit_info_1
)
2686 return wrmsr_interception(svm
);
2688 return rdmsr_interception(svm
);
2691 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2693 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2695 svm_clear_vintr(svm
);
2696 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2698 * If the user space waits to inject interrupts, exit as soon as
2701 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2702 kvm_run
->request_interrupt_window
&&
2703 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2704 ++svm
->vcpu
.stat
.irq_window_exits
;
2705 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2712 static int pause_interception(struct vcpu_svm
*svm
)
2714 kvm_vcpu_on_spin(&(svm
->vcpu
));
2718 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2719 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2720 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2721 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2722 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2723 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2724 [SVM_EXIT_WRITE_CR0
] = cr0_write_interception
,
2725 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2726 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2727 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2728 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2729 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2730 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2731 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2732 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2733 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2734 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2735 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2736 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2737 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2738 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2739 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2740 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2741 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2742 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2743 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2744 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2745 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2746 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2747 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2748 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2749 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2750 [SVM_EXIT_INTR
] = intr_interception
,
2751 [SVM_EXIT_NMI
] = nmi_interception
,
2752 [SVM_EXIT_SMI
] = nop_on_interception
,
2753 [SVM_EXIT_INIT
] = nop_on_interception
,
2754 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2755 [SVM_EXIT_CPUID
] = cpuid_interception
,
2756 [SVM_EXIT_IRET
] = iret_interception
,
2757 [SVM_EXIT_INVD
] = emulate_on_interception
,
2758 [SVM_EXIT_PAUSE
] = pause_interception
,
2759 [SVM_EXIT_HLT
] = halt_interception
,
2760 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2761 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2762 [SVM_EXIT_IOIO
] = io_interception
,
2763 [SVM_EXIT_MSR
] = msr_interception
,
2764 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2765 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2766 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2767 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2768 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2769 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2770 [SVM_EXIT_STGI
] = stgi_interception
,
2771 [SVM_EXIT_CLGI
] = clgi_interception
,
2772 [SVM_EXIT_SKINIT
] = skinit_interception
,
2773 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2774 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2775 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2776 [SVM_EXIT_NPF
] = pf_interception
,
2779 void dump_vmcb(struct kvm_vcpu
*vcpu
)
2781 struct vcpu_svm
*svm
= to_svm(vcpu
);
2782 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2783 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
2785 pr_err("VMCB Control Area:\n");
2786 pr_err("cr_read: %04x\n", control
->intercept_cr_read
);
2787 pr_err("cr_write: %04x\n", control
->intercept_cr_write
);
2788 pr_err("dr_read: %04x\n", control
->intercept_dr_read
);
2789 pr_err("dr_write: %04x\n", control
->intercept_dr_write
);
2790 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
2791 pr_err("intercepts: %016llx\n", control
->intercept
);
2792 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
2793 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
2794 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
2795 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
2796 pr_err("asid: %d\n", control
->asid
);
2797 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
2798 pr_err("int_ctl: %08x\n", control
->int_ctl
);
2799 pr_err("int_vector: %08x\n", control
->int_vector
);
2800 pr_err("int_state: %08x\n", control
->int_state
);
2801 pr_err("exit_code: %08x\n", control
->exit_code
);
2802 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
2803 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
2804 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
2805 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
2806 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
2807 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
2808 pr_err("event_inj: %08x\n", control
->event_inj
);
2809 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
2810 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
2811 pr_err("next_rip: %016llx\n", control
->next_rip
);
2812 pr_err("VMCB State Save Area:\n");
2813 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2814 save
->es
.selector
, save
->es
.attrib
,
2815 save
->es
.limit
, save
->es
.base
);
2816 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2817 save
->cs
.selector
, save
->cs
.attrib
,
2818 save
->cs
.limit
, save
->cs
.base
);
2819 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2820 save
->ss
.selector
, save
->ss
.attrib
,
2821 save
->ss
.limit
, save
->ss
.base
);
2822 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2823 save
->ds
.selector
, save
->ds
.attrib
,
2824 save
->ds
.limit
, save
->ds
.base
);
2825 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2826 save
->fs
.selector
, save
->fs
.attrib
,
2827 save
->fs
.limit
, save
->fs
.base
);
2828 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2829 save
->gs
.selector
, save
->gs
.attrib
,
2830 save
->gs
.limit
, save
->gs
.base
);
2831 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2832 save
->gdtr
.selector
, save
->gdtr
.attrib
,
2833 save
->gdtr
.limit
, save
->gdtr
.base
);
2834 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2835 save
->ldtr
.selector
, save
->ldtr
.attrib
,
2836 save
->ldtr
.limit
, save
->ldtr
.base
);
2837 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2838 save
->idtr
.selector
, save
->idtr
.attrib
,
2839 save
->idtr
.limit
, save
->idtr
.base
);
2840 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2841 save
->tr
.selector
, save
->tr
.attrib
,
2842 save
->tr
.limit
, save
->tr
.base
);
2843 pr_err("cpl: %d efer: %016llx\n",
2844 save
->cpl
, save
->efer
);
2845 pr_err("cr0: %016llx cr2: %016llx\n",
2846 save
->cr0
, save
->cr2
);
2847 pr_err("cr3: %016llx cr4: %016llx\n",
2848 save
->cr3
, save
->cr4
);
2849 pr_err("dr6: %016llx dr7: %016llx\n",
2850 save
->dr6
, save
->dr7
);
2851 pr_err("rip: %016llx rflags: %016llx\n",
2852 save
->rip
, save
->rflags
);
2853 pr_err("rsp: %016llx rax: %016llx\n",
2854 save
->rsp
, save
->rax
);
2855 pr_err("star: %016llx lstar: %016llx\n",
2856 save
->star
, save
->lstar
);
2857 pr_err("cstar: %016llx sfmask: %016llx\n",
2858 save
->cstar
, save
->sfmask
);
2859 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2860 save
->kernel_gs_base
, save
->sysenter_cs
);
2861 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2862 save
->sysenter_esp
, save
->sysenter_eip
);
2863 pr_err("gpat: %016llx dbgctl: %016llx\n",
2864 save
->g_pat
, save
->dbgctl
);
2865 pr_err("br_from: %016llx br_to: %016llx\n",
2866 save
->br_from
, save
->br_to
);
2867 pr_err("excp_from: %016llx excp_to: %016llx\n",
2868 save
->last_excp_from
, save
->last_excp_to
);
2872 static int handle_exit(struct kvm_vcpu
*vcpu
)
2874 struct vcpu_svm
*svm
= to_svm(vcpu
);
2875 struct kvm_run
*kvm_run
= vcpu
->run
;
2876 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2878 trace_kvm_exit(exit_code
, vcpu
);
2880 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR0_MASK
))
2881 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2883 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2885 if (unlikely(svm
->nested
.exit_required
)) {
2886 nested_svm_vmexit(svm
);
2887 svm
->nested
.exit_required
= false;
2892 if (is_nested(svm
)) {
2895 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
2896 svm
->vmcb
->control
.exit_info_1
,
2897 svm
->vmcb
->control
.exit_info_2
,
2898 svm
->vmcb
->control
.exit_int_info
,
2899 svm
->vmcb
->control
.exit_int_info_err
);
2901 vmexit
= nested_svm_exit_special(svm
);
2903 if (vmexit
== NESTED_EXIT_CONTINUE
)
2904 vmexit
= nested_svm_exit_handled(svm
);
2906 if (vmexit
== NESTED_EXIT_DONE
)
2910 svm_complete_interrupts(svm
);
2912 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2913 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2914 kvm_run
->fail_entry
.hardware_entry_failure_reason
2915 = svm
->vmcb
->control
.exit_code
;
2916 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2921 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2922 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2923 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2924 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2926 __func__
, svm
->vmcb
->control
.exit_int_info
,
2929 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2930 || !svm_exit_handlers
[exit_code
]) {
2931 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2932 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2936 return svm_exit_handlers
[exit_code
](svm
);
2939 static void reload_tss(struct kvm_vcpu
*vcpu
)
2941 int cpu
= raw_smp_processor_id();
2943 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2944 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2948 static void pre_svm_run(struct vcpu_svm
*svm
)
2950 int cpu
= raw_smp_processor_id();
2952 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2954 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2955 /* FIXME: handle wraparound of asid_generation */
2956 if (svm
->asid_generation
!= sd
->asid_generation
)
2960 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2962 struct vcpu_svm
*svm
= to_svm(vcpu
);
2964 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2965 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2966 svm
->vmcb
->control
.intercept
|= (1ULL << INTERCEPT_IRET
);
2967 ++vcpu
->stat
.nmi_injections
;
2970 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2972 struct vmcb_control_area
*control
;
2974 control
= &svm
->vmcb
->control
;
2975 control
->int_vector
= irq
;
2976 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2977 control
->int_ctl
|= V_IRQ_MASK
|
2978 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2981 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2983 struct vcpu_svm
*svm
= to_svm(vcpu
);
2985 BUG_ON(!(gif_set(svm
)));
2987 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
2988 ++vcpu
->stat
.irq_injections
;
2990 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
2991 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2994 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2996 struct vcpu_svm
*svm
= to_svm(vcpu
);
2998 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3005 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
3008 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3010 struct vcpu_svm
*svm
= to_svm(vcpu
);
3011 struct vmcb
*vmcb
= svm
->vmcb
;
3013 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3014 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3015 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3020 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3022 struct vcpu_svm
*svm
= to_svm(vcpu
);
3024 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3027 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3029 struct vcpu_svm
*svm
= to_svm(vcpu
);
3032 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3033 svm
->vmcb
->control
.intercept
|= (1ULL << INTERCEPT_IRET
);
3035 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3036 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_IRET
);
3040 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3042 struct vcpu_svm
*svm
= to_svm(vcpu
);
3043 struct vmcb
*vmcb
= svm
->vmcb
;
3046 if (!gif_set(svm
) ||
3047 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3050 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3053 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3058 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3060 struct vcpu_svm
*svm
= to_svm(vcpu
);
3063 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3064 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3065 * get that intercept, this function will be called again though and
3066 * we'll get the vintr intercept.
3068 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3070 svm_inject_irq(svm
, 0x0);
3074 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3076 struct vcpu_svm
*svm
= to_svm(vcpu
);
3078 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3080 return; /* IRET will cause a vm exit */
3083 * Something prevents NMI from been injected. Single step over possible
3084 * problem (IRET or exception injection or interrupt shadow)
3086 svm
->nmi_singlestep
= true;
3087 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3088 update_db_intercept(vcpu
);
3091 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3096 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3098 force_new_asid(vcpu
);
3101 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3105 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3107 struct vcpu_svm
*svm
= to_svm(vcpu
);
3109 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3112 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
3113 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3114 kvm_set_cr8(vcpu
, cr8
);
3118 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3120 struct vcpu_svm
*svm
= to_svm(vcpu
);
3123 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3126 cr8
= kvm_get_cr8(vcpu
);
3127 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3128 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3131 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3135 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3136 unsigned int3_injected
= svm
->int3_injected
;
3138 svm
->int3_injected
= 0;
3140 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3141 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3143 svm
->vcpu
.arch
.nmi_injected
= false;
3144 kvm_clear_exception_queue(&svm
->vcpu
);
3145 kvm_clear_interrupt_queue(&svm
->vcpu
);
3147 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3150 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3151 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3154 case SVM_EXITINTINFO_TYPE_NMI
:
3155 svm
->vcpu
.arch
.nmi_injected
= true;
3157 case SVM_EXITINTINFO_TYPE_EXEPT
:
3159 * In case of software exceptions, do not reinject the vector,
3160 * but re-execute the instruction instead. Rewind RIP first
3161 * if we emulated INT3 before.
3163 if (kvm_exception_is_soft(vector
)) {
3164 if (vector
== BP_VECTOR
&& int3_injected
&&
3165 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3166 kvm_rip_write(&svm
->vcpu
,
3167 kvm_rip_read(&svm
->vcpu
) -
3171 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3172 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3173 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3176 kvm_requeue_exception(&svm
->vcpu
, vector
);
3178 case SVM_EXITINTINFO_TYPE_INTR
:
3179 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3186 #ifdef CONFIG_X86_64
3192 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3194 struct vcpu_svm
*svm
= to_svm(vcpu
);
3199 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3200 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3201 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3204 * A vmexit emulation is required before the vcpu can be executed
3207 if (unlikely(svm
->nested
.exit_required
))
3212 sync_lapic_to_cr8(vcpu
);
3214 save_host_msrs(vcpu
);
3215 savesegment(fs
, fs_selector
);
3216 savesegment(gs
, gs_selector
);
3217 ldt_selector
= kvm_read_ldt();
3218 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3225 "push %%"R
"bp; \n\t"
3226 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3227 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3228 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3229 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3230 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3231 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3232 #ifdef CONFIG_X86_64
3233 "mov %c[r8](%[svm]), %%r8 \n\t"
3234 "mov %c[r9](%[svm]), %%r9 \n\t"
3235 "mov %c[r10](%[svm]), %%r10 \n\t"
3236 "mov %c[r11](%[svm]), %%r11 \n\t"
3237 "mov %c[r12](%[svm]), %%r12 \n\t"
3238 "mov %c[r13](%[svm]), %%r13 \n\t"
3239 "mov %c[r14](%[svm]), %%r14 \n\t"
3240 "mov %c[r15](%[svm]), %%r15 \n\t"
3243 /* Enter guest mode */
3245 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3246 __ex(SVM_VMLOAD
) "\n\t"
3247 __ex(SVM_VMRUN
) "\n\t"
3248 __ex(SVM_VMSAVE
) "\n\t"
3251 /* Save guest registers, load host registers */
3252 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3253 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3254 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3255 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3256 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3257 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3258 #ifdef CONFIG_X86_64
3259 "mov %%r8, %c[r8](%[svm]) \n\t"
3260 "mov %%r9, %c[r9](%[svm]) \n\t"
3261 "mov %%r10, %c[r10](%[svm]) \n\t"
3262 "mov %%r11, %c[r11](%[svm]) \n\t"
3263 "mov %%r12, %c[r12](%[svm]) \n\t"
3264 "mov %%r13, %c[r13](%[svm]) \n\t"
3265 "mov %%r14, %c[r14](%[svm]) \n\t"
3266 "mov %%r15, %c[r15](%[svm]) \n\t"
3271 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3272 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3273 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3274 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3275 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3276 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3277 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3278 #ifdef CONFIG_X86_64
3279 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3280 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3281 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3282 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3283 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3284 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3285 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3286 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3289 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3290 #ifdef CONFIG_X86_64
3291 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3295 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3296 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3297 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3298 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3300 load_host_msrs(vcpu
);
3301 loadsegment(fs
, fs_selector
);
3302 #ifdef CONFIG_X86_64
3303 load_gs_index(gs_selector
);
3304 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
3306 loadsegment(gs
, gs_selector
);
3308 kvm_load_ldt(ldt_selector
);
3312 local_irq_disable();
3316 sync_cr8_to_lapic(vcpu
);
3321 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3322 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3326 * We need to handle MC intercepts here before the vcpu has a chance to
3327 * change the physical cpu
3329 if (unlikely(svm
->vmcb
->control
.exit_code
==
3330 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3331 svm_handle_mce(svm
);
3336 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3338 struct vcpu_svm
*svm
= to_svm(vcpu
);
3340 svm
->vmcb
->save
.cr3
= root
;
3341 force_new_asid(vcpu
);
3344 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3346 struct vcpu_svm
*svm
= to_svm(vcpu
);
3348 svm
->vmcb
->control
.nested_cr3
= root
;
3350 /* Also sync guest cr3 here in case we live migrate */
3351 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
3353 force_new_asid(vcpu
);
3356 static int is_disabled(void)
3360 rdmsrl(MSR_VM_CR
, vm_cr
);
3361 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3368 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3371 * Patch in the VMMCALL instruction:
3373 hypercall
[0] = 0x0f;
3374 hypercall
[1] = 0x01;
3375 hypercall
[2] = 0xd9;
3378 static void svm_check_processor_compat(void *rtn
)
3383 static bool svm_cpu_has_accelerated_tpr(void)
3388 static int get_npt_level(void)
3390 #ifdef CONFIG_X86_64
3391 return PT64_ROOT_LEVEL
;
3393 return PT32E_ROOT_LEVEL
;
3397 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3402 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3406 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3410 entry
->eax
= 1; /* SVM revision 1 */
3411 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3412 ASID emulation to nested SVM */
3413 entry
->ecx
= 0; /* Reserved */
3414 entry
->edx
= 0; /* Per default do not support any
3415 additional features */
3417 /* Support next_rip if host supports it */
3418 if (svm_has(SVM_FEATURE_NRIP
))
3419 entry
->edx
|= SVM_FEATURE_NRIP
;
3425 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3426 { SVM_EXIT_READ_CR0
, "read_cr0" },
3427 { SVM_EXIT_READ_CR3
, "read_cr3" },
3428 { SVM_EXIT_READ_CR4
, "read_cr4" },
3429 { SVM_EXIT_READ_CR8
, "read_cr8" },
3430 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3431 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3432 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3433 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3434 { SVM_EXIT_READ_DR0
, "read_dr0" },
3435 { SVM_EXIT_READ_DR1
, "read_dr1" },
3436 { SVM_EXIT_READ_DR2
, "read_dr2" },
3437 { SVM_EXIT_READ_DR3
, "read_dr3" },
3438 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3439 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3440 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3441 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3442 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3443 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3444 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3445 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3446 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3447 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3448 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3449 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3450 { SVM_EXIT_INTR
, "interrupt" },
3451 { SVM_EXIT_NMI
, "nmi" },
3452 { SVM_EXIT_SMI
, "smi" },
3453 { SVM_EXIT_INIT
, "init" },
3454 { SVM_EXIT_VINTR
, "vintr" },
3455 { SVM_EXIT_CPUID
, "cpuid" },
3456 { SVM_EXIT_INVD
, "invd" },
3457 { SVM_EXIT_HLT
, "hlt" },
3458 { SVM_EXIT_INVLPG
, "invlpg" },
3459 { SVM_EXIT_INVLPGA
, "invlpga" },
3460 { SVM_EXIT_IOIO
, "io" },
3461 { SVM_EXIT_MSR
, "msr" },
3462 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3463 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3464 { SVM_EXIT_VMRUN
, "vmrun" },
3465 { SVM_EXIT_VMMCALL
, "hypercall" },
3466 { SVM_EXIT_VMLOAD
, "vmload" },
3467 { SVM_EXIT_VMSAVE
, "vmsave" },
3468 { SVM_EXIT_STGI
, "stgi" },
3469 { SVM_EXIT_CLGI
, "clgi" },
3470 { SVM_EXIT_SKINIT
, "skinit" },
3471 { SVM_EXIT_WBINVD
, "wbinvd" },
3472 { SVM_EXIT_MONITOR
, "monitor" },
3473 { SVM_EXIT_MWAIT
, "mwait" },
3474 { SVM_EXIT_NPF
, "npf" },
3478 static int svm_get_lpage_level(void)
3480 return PT_PDPE_LEVEL
;
3483 static bool svm_rdtscp_supported(void)
3488 static bool svm_has_wbinvd_exit(void)
3493 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3495 struct vcpu_svm
*svm
= to_svm(vcpu
);
3497 svm
->vmcb
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3499 svm
->nested
.hsave
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3500 update_cr0_intercept(svm
);
3503 static struct kvm_x86_ops svm_x86_ops
= {
3504 .cpu_has_kvm_support
= has_svm
,
3505 .disabled_by_bios
= is_disabled
,
3506 .hardware_setup
= svm_hardware_setup
,
3507 .hardware_unsetup
= svm_hardware_unsetup
,
3508 .check_processor_compatibility
= svm_check_processor_compat
,
3509 .hardware_enable
= svm_hardware_enable
,
3510 .hardware_disable
= svm_hardware_disable
,
3511 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3513 .vcpu_create
= svm_create_vcpu
,
3514 .vcpu_free
= svm_free_vcpu
,
3515 .vcpu_reset
= svm_vcpu_reset
,
3517 .prepare_guest_switch
= svm_prepare_guest_switch
,
3518 .vcpu_load
= svm_vcpu_load
,
3519 .vcpu_put
= svm_vcpu_put
,
3521 .set_guest_debug
= svm_guest_debug
,
3522 .get_msr
= svm_get_msr
,
3523 .set_msr
= svm_set_msr
,
3524 .get_segment_base
= svm_get_segment_base
,
3525 .get_segment
= svm_get_segment
,
3526 .set_segment
= svm_set_segment
,
3527 .get_cpl
= svm_get_cpl
,
3528 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3529 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3530 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3531 .set_cr0
= svm_set_cr0
,
3532 .set_cr3
= svm_set_cr3
,
3533 .set_cr4
= svm_set_cr4
,
3534 .set_efer
= svm_set_efer
,
3535 .get_idt
= svm_get_idt
,
3536 .set_idt
= svm_set_idt
,
3537 .get_gdt
= svm_get_gdt
,
3538 .set_gdt
= svm_set_gdt
,
3539 .set_dr7
= svm_set_dr7
,
3540 .cache_reg
= svm_cache_reg
,
3541 .get_rflags
= svm_get_rflags
,
3542 .set_rflags
= svm_set_rflags
,
3543 .fpu_activate
= svm_fpu_activate
,
3544 .fpu_deactivate
= svm_fpu_deactivate
,
3546 .tlb_flush
= svm_flush_tlb
,
3548 .run
= svm_vcpu_run
,
3549 .handle_exit
= handle_exit
,
3550 .skip_emulated_instruction
= skip_emulated_instruction
,
3551 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3552 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3553 .patch_hypercall
= svm_patch_hypercall
,
3554 .set_irq
= svm_set_irq
,
3555 .set_nmi
= svm_inject_nmi
,
3556 .queue_exception
= svm_queue_exception
,
3557 .interrupt_allowed
= svm_interrupt_allowed
,
3558 .nmi_allowed
= svm_nmi_allowed
,
3559 .get_nmi_mask
= svm_get_nmi_mask
,
3560 .set_nmi_mask
= svm_set_nmi_mask
,
3561 .enable_nmi_window
= enable_nmi_window
,
3562 .enable_irq_window
= enable_irq_window
,
3563 .update_cr8_intercept
= update_cr8_intercept
,
3565 .set_tss_addr
= svm_set_tss_addr
,
3566 .get_tdp_level
= get_npt_level
,
3567 .get_mt_mask
= svm_get_mt_mask
,
3569 .exit_reasons_str
= svm_exit_reasons_str
,
3570 .get_lpage_level
= svm_get_lpage_level
,
3572 .cpuid_update
= svm_cpuid_update
,
3574 .rdtscp_supported
= svm_rdtscp_supported
,
3576 .set_supported_cpuid
= svm_set_supported_cpuid
,
3578 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3580 .write_tsc_offset
= svm_write_tsc_offset
,
3581 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
3583 .set_tdp_cr3
= set_tdp_cr3
,
3586 static int __init
svm_init(void)
3588 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3589 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3592 static void __exit
svm_exit(void)
3597 module_init(svm_init
)
3598 module_exit(svm_exit
)