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KVM: MMU: Track NX state in struct kvm_mmu
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
221d059d 7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
6aa8b732 34
63d1142f 35#include <asm/virtext.h>
229456fc 36#include "trace.h"
63d1142f 37
4ecac3fd
AK		 38#define __ex(x) __kvm_handle_fault_on_reboot(x)
39
6aa8b732
AK		 40MODULE_AUTHOR("Qumranet");
41MODULE_LICENSE("GPL");
42
43#define IOPM_ALLOC_ORDER 2
44#define MSRPM_ALLOC_ORDER 1
45
6aa8b732
AK		 46#define SEG_TYPE_LDT 2
47#define SEG_TYPE_BUSY_TSS16 3
48
6bc31bdc
AP		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_FEATURE_SVML (1 << 2)
52#define SVM_FEATURE_NRIP (1 << 3)
53#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 54
410e4d57
JR		 55#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
24e09cbf
JR		 59#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
67ec6607
JR		 61static bool erratum_383_found __read_mostly;
62
6c8166a7
AK		 63static const u32 host_save_user_msrs[] = {
64#ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67#endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69};
70
71#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73struct kvm_vcpu;
74
e6aa9abd
JR		 75struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
4a810181 78 u64 vm_cr_msr;
e6aa9abd
JR		 79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
ce2ac085 86 u64 vmcb_iopm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
cda00082
JR		 91 /*
92 * If we vmexit during an instruction emulation we need this to restore
93 * the l1 guest rip after the emulation
94 */
95 unsigned long vmexit_rip;
96 unsigned long vmexit_rsp;
97 unsigned long vmexit_rax;
98
aad42c64
JR		 99 /* cache for intercepts of the guest */
100 u16 intercept_cr_read;
101 u16 intercept_cr_write;
102 u16 intercept_dr_read;
103 u16 intercept_dr_write;
104 u32 intercept_exceptions;
105 u64 intercept;
106
e6aa9abd
JR		 107};
108
323c3d80
JR		 109#define MSRPM_OFFSETS 16
110static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
111
6c8166a7
AK		 112struct vcpu_svm {
113 struct kvm_vcpu vcpu;
114 struct vmcb *vmcb;
115 unsigned long vmcb_pa;
116 struct svm_cpu_data *svm_data;
117 uint64_t asid_generation;
118 uint64_t sysenter_esp;
119 uint64_t sysenter_eip;
120
121 u64 next_rip;
122
123 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
124 u64 host_gs_base;
6c8166a7
AK		 125
126 u32 *msrpm;
6c8166a7 127
e6aa9abd 128 struct nested_state nested;
6be7d306
JK		 129
130 bool nmi_singlestep;
66b7138f
JK		 131
132 unsigned int3_injected;
133 unsigned long int3_rip;
6c8166a7
AK		 134};
135
455716fa
JR		 136#define MSR_INVALID 0xffffffffU
137
ac72a9b7
JR		 138static struct svm_direct_access_msrs {
139 u32 index; /* Index of the MSR */
140 bool always; /* True if intercept is always on */
141} direct_access_msrs[] = {
8c06585d 142 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 143 { .index = MSR_IA32_SYSENTER_CS, .always = true },
144#ifdef CONFIG_X86_64
145 { .index = MSR_GS_BASE, .always = true },
146 { .index = MSR_FS_BASE, .always = true },
147 { .index = MSR_KERNEL_GS_BASE, .always = true },
148 { .index = MSR_LSTAR, .always = true },
149 { .index = MSR_CSTAR, .always = true },
150 { .index = MSR_SYSCALL_MASK, .always = true },
151#endif
152 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
153 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
154 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
155 { .index = MSR_IA32_LASTINTTOIP, .always = false },
156 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 157};
158
709ddebf
JR		 159/* enable NPT for AMD64 and X86 with PAE */
160#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
161static bool npt_enabled = true;
162#else
e0231715 163static bool npt_enabled;
709ddebf 164#endif
6c7dac72
JR		 165static int npt = 1;
166
167module_param(npt, int, S_IRUGO);
e3da3acd 168
4b6e4dca 169static int nested = 1;
236de055
AG		 170module_param(nested, int, S_IRUGO);
171
44874f84 172static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 173static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 174
410e4d57 175static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 176static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 177static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 178static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
179 bool has_error_code, u32 error_code);
180
a2fa3e9f
GH		 181static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
182{
fb3f0f51 183 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 184}
185
3d6368ef
AG		 186static inline bool is_nested(struct vcpu_svm *svm)
187{
e6aa9abd 188 return svm->nested.vmcb;
3d6368ef
AG		 189}
190
2af9194d
JR		 191static inline void enable_gif(struct vcpu_svm *svm)
192{
193 svm->vcpu.arch.hflags |= HF_GIF_MASK;
194}
195
196static inline void disable_gif(struct vcpu_svm *svm)
197{
198 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
199}
200
201static inline bool gif_set(struct vcpu_svm *svm)
202{
203 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
204}
205
4866d5e3 206static unsigned long iopm_base;
6aa8b732
AK		 207
208struct kvm_ldttss_desc {
209 u16 limit0;
210 u16 base0;
e0231715
JR		 211 unsigned base1:8, type:5, dpl:2, p:1;
212 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 213 u32 base3;
214 u32 zero1;
215} __attribute__((packed));
216
217struct svm_cpu_data {
218 int cpu;
219
5008fdf5
AK		 220 u64 asid_generation;
221 u32 max_asid;
222 u32 next_asid;
6aa8b732
AK		 223 struct kvm_ldttss_desc *tss_desc;
224
225 struct page *save_area;
226};
227
228static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 229static uint32_t svm_features;
6aa8b732
AK		 230
231struct svm_init_data {
232 int cpu;
233 int r;
234};
235
236static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
237
9d8f549d 238#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 239#define MSRS_RANGE_SIZE 2048
240#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
241
455716fa
JR		 242static u32 svm_msrpm_offset(u32 msr)
243{
244 u32 offset;
245 int i;
246
247 for (i = 0; i < NUM_MSR_MAPS; i++) {
248 if (msr < msrpm_ranges[i] ||
249 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
250 continue;
251
252 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
253 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
254
255 /* Now we have the u8 offset - but need the u32 offset */
256 return offset / 4;
257 }
258
259 /* MSR not in any range */
260 return MSR_INVALID;
261}
262
6aa8b732
AK		 263#define MAX_INST_SIZE 15
264
80b7706e
JR		 265static inline u32 svm_has(u32 feat)
266{
267 return svm_features & feat;
268}
269
6aa8b732
AK		 270static inline void clgi(void)
271{
4ecac3fd 272 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 273}
274
275static inline void stgi(void)
276{
4ecac3fd 277 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 278}
279
280static inline void invlpga(unsigned long addr, u32 asid)
281{
e0231715 282 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 283}
284
6aa8b732
AK		 285static inline void force_new_asid(struct kvm_vcpu *vcpu)
286{
a2fa3e9f 287 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 288}
289
290static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
291{
292 force_new_asid(vcpu);
293}
294
295static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
296{
6dc696d4 297 vcpu->arch.efer = efer;
709ddebf 298 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 299 efer &= ~EFER_LME;
6aa8b732 300
9962d032 301 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 302}
303
6aa8b732
AK		 304static int is_external_interrupt(u32 info)
305{
306 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
307 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
308}
309
2809f5d2
GC		 310static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
311{
312 struct vcpu_svm *svm = to_svm(vcpu);
313 u32 ret = 0;
314
315 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 316 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 317 return ret & mask;
318}
319
320static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
321{
322 struct vcpu_svm *svm = to_svm(vcpu);
323
324 if (mask == 0)
325 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
326 else
327 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
328
329}
330
6aa8b732
AK		 331static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
332{
a2fa3e9f
GH		 333 struct vcpu_svm *svm = to_svm(vcpu);
334
6bc31bdc
AP		 335 if (svm->vmcb->control.next_rip != 0)
336 svm->next_rip = svm->vmcb->control.next_rip;
337
a2fa3e9f 338 if (!svm->next_rip) {
851ba692 339 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 340 EMULATE_DONE)
341 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 342 return;
343 }
5fdbf976
MT		 344 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
345 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
346 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 347
5fdbf976 348 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 349 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 350}
351
116a4752 352static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 353 bool has_error_code, u32 error_code,
354 bool reinject)
116a4752
JK		 355{
356 struct vcpu_svm *svm = to_svm(vcpu);
357
e0231715
JR		 358 /*
359 * If we are within a nested VM we'd better #VMEXIT and let the guest
360 * handle the exception
361 */
ce7ddec4
JR		 362 if (!reinject &&
363 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 364 return;
365
66b7138f
JK		 366 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
367 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
368
369 /*
370 * For guest debugging where we have to reinject #BP if some
371 * INT3 is guest-owned:
372 * Emulate nRIP by moving RIP forward. Will fail if injection
373 * raises a fault that is not intercepted. Still better than
374 * failing in all cases.
375 */
376 skip_emulated_instruction(&svm->vcpu);
377 rip = kvm_rip_read(&svm->vcpu);
378 svm->int3_rip = rip + svm->vmcb->save.cs.base;
379 svm->int3_injected = rip - old_rip;
380 }
381
116a4752
JK		 382 svm->vmcb->control.event_inj = nr
383 | SVM_EVTINJ_VALID
384 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
385 | SVM_EVTINJ_TYPE_EXEPT;
386 svm->vmcb->control.event_inj_err = error_code;
387}
388
67ec6607
JR		 389static void svm_init_erratum_383(void)
390{
391 u32 low, high;
392 int err;
393 u64 val;
394
1be85a6d 395 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 396 return;
397
398 /* Use _safe variants to not break nested virtualization */
399 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
400 if (err)
401 return;
402
403 val |= (1ULL << 47);
404
405 low = lower_32_bits(val);
406 high = upper_32_bits(val);
407
408 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
409
410 erratum_383_found = true;
411}
412
6aa8b732
AK		 413static int has_svm(void)
414{
63d1142f 415 const char *msg;
6aa8b732 416
63d1142f 417 if (!cpu_has_svm(&msg)) {
ff81ff10 418 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 419 return 0;
420 }
421
6aa8b732
AK		 422 return 1;
423}
424
425static void svm_hardware_disable(void *garbage)
426{
2c8dceeb 427 cpu_svm_disable();
6aa8b732
AK		 428}
429
10474ae8 430static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 431{
432
0fe1e009 433 struct svm_cpu_data *sd;
6aa8b732 434 uint64_t efer;
89a27f4d 435 struct desc_ptr gdt_descr;
6aa8b732
AK		 436 struct desc_struct *gdt;
437 int me = raw_smp_processor_id();
438
10474ae8
AG		 439 rdmsrl(MSR_EFER, efer);
440 if (efer & EFER_SVME)
441 return -EBUSY;
442
6aa8b732 443 if (!has_svm()) {
e6732a5a
ZA		 444 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
445 me);
10474ae8 446 return -EINVAL;
6aa8b732 447 }
0fe1e009 448 sd = per_cpu(svm_data, me);
6aa8b732 449
0fe1e009 450 if (!sd) {
e6732a5a 451 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 452 me);
10474ae8 453 return -EINVAL;
6aa8b732
AK		 454 }
455
0fe1e009
TH		 456 sd->asid_generation = 1;
457 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
458 sd->next_asid = sd->max_asid + 1;
6aa8b732 459
d6ab1ed4 460 native_store_gdt(&gdt_descr);
89a27f4d 461 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 462 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 463
9962d032 464 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 465
d0316554 466 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 467
67ec6607
JR		 468 svm_init_erratum_383();
469
10474ae8 470 return 0;
6aa8b732
AK		 471}
472
0da1db75
JR		 473static void svm_cpu_uninit(int cpu)
474{
0fe1e009 475 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 476
0fe1e009 477 if (!sd)
0da1db75
JR		 478 return;
479
480 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 481 __free_page(sd->save_area);
482 kfree(sd);
0da1db75
JR		 483}
484
6aa8b732
AK		 485static int svm_cpu_init(int cpu)
486{
0fe1e009 487 struct svm_cpu_data *sd;
6aa8b732
AK		 488 int r;
489
0fe1e009
TH		 490 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
491 if (!sd)
6aa8b732 492 return -ENOMEM;
0fe1e009
TH		 493 sd->cpu = cpu;
494 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 495 r = -ENOMEM;
0fe1e009 496 if (!sd->save_area)
6aa8b732
AK		 497 goto err_1;
498
0fe1e009 499 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 500
501 return 0;
502
503err_1:
0fe1e009 504 kfree(sd);
6aa8b732
AK		 505 return r;
506
507}
508
ac72a9b7
JR		 509static bool valid_msr_intercept(u32 index)
510{
511 int i;
512
513 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
514 if (direct_access_msrs[i].index == index)
515 return true;
516
517 return false;
518}
519
bfc733a7
RR		 520static void set_msr_interception(u32 *msrpm, unsigned msr,
521 int read, int write)
6aa8b732 522{
455716fa
JR		 523 u8 bit_read, bit_write;
524 unsigned long tmp;
525 u32 offset;
6aa8b732 526
ac72a9b7
JR		 527 /*
528 * If this warning triggers extend the direct_access_msrs list at the
529 * beginning of the file
530 */
531 WARN_ON(!valid_msr_intercept(msr));
532
455716fa
JR		 533 offset = svm_msrpm_offset(msr);
534 bit_read = 2 * (msr & 0x0f);
535 bit_write = 2 * (msr & 0x0f) + 1;
536 tmp = msrpm[offset];
537
538 BUG_ON(offset == MSR_INVALID);
539
540 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
541 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
542
543 msrpm[offset] = tmp;
6aa8b732
AK		 544}
545
f65c229c 546static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 547{
548 int i;
549
f65c229c
JR		 550 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
551
ac72a9b7
JR		 552 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
553 if (!direct_access_msrs[i].always)
554 continue;
555
556 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
557 }
f65c229c
JR		 558}
559
323c3d80
JR		 560static void add_msr_offset(u32 offset)
561{
562 int i;
563
564 for (i = 0; i < MSRPM_OFFSETS; ++i) {
565
566 /* Offset already in list? */
567 if (msrpm_offsets[i] == offset)
bfc733a7 568 return;
323c3d80
JR		 569
570 /* Slot used by another offset? */
571 if (msrpm_offsets[i] != MSR_INVALID)
572 continue;
573
574 /* Add offset to list */
575 msrpm_offsets[i] = offset;
576
577 return;
6aa8b732 578 }
323c3d80
JR		 579
580 /*
581 * If this BUG triggers the msrpm_offsets table has an overflow. Just
582 * increase MSRPM_OFFSETS in this case.
583 */
bfc733a7 584 BUG();
6aa8b732
AK		 585}
586
323c3d80 587static void init_msrpm_offsets(void)
f65c229c 588{
323c3d80 589 int i;
f65c229c 590
323c3d80
JR		 591 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
592
593 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
594 u32 offset;
595
596 offset = svm_msrpm_offset(direct_access_msrs[i].index);
597 BUG_ON(offset == MSR_INVALID);
598
599 add_msr_offset(offset);
600 }
f65c229c
JR		 601}
602
24e09cbf
JR		 603static void svm_enable_lbrv(struct vcpu_svm *svm)
604{
605 u32 *msrpm = svm->msrpm;
606
607 svm->vmcb->control.lbr_ctl = 1;
608 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
609 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
610 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
611 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
612}
613
614static void svm_disable_lbrv(struct vcpu_svm *svm)
615{
616 u32 *msrpm = svm->msrpm;
617
618 svm->vmcb->control.lbr_ctl = 0;
619 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
620 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
621 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
622 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
623}
624
6aa8b732
AK		 625static __init int svm_hardware_setup(void)
626{
627 int cpu;
628 struct page *iopm_pages;
f65c229c 629 void *iopm_va;
6aa8b732
AK		 630 int r;
631
6aa8b732
AK		 632 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
633
634 if (!iopm_pages)
635 return -ENOMEM;
c8681339
AL		 636
637 iopm_va = page_address(iopm_pages);
638 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 639 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
640
323c3d80
JR		 641 init_msrpm_offsets();
642
50a37eb4
JR		 643 if (boot_cpu_has(X86_FEATURE_NX))
644 kvm_enable_efer_bits(EFER_NX);
645
1b2fd70c
AG		 646 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
647 kvm_enable_efer_bits(EFER_FFXSR);
648
236de055
AG		 649 if (nested) {
650 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 651 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 652 }
653
3230bb47 654 for_each_possible_cpu(cpu) {
6aa8b732
AK		 655 r = svm_cpu_init(cpu);
656 if (r)
f65c229c 657 goto err;
6aa8b732 658 }
33bd6a0b
JR		 659
660 svm_features = cpuid_edx(SVM_CPUID_FUNC);
661
e3da3acd
JR		 662 if (!svm_has(SVM_FEATURE_NPT))
663 npt_enabled = false;
664
6c7dac72
JR		 665 if (npt_enabled && !npt) {
666 printk(KERN_INFO "kvm: Nested Paging disabled\n");
667 npt_enabled = false;
668 }
669
18552672 670 if (npt_enabled) {
e3da3acd 671 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 672 kvm_enable_tdp();
5f4cb662
JR		 673 } else
674 kvm_disable_tdp();
e3da3acd 675
6aa8b732
AK		 676 return 0;
677
f65c229c 678err:
6aa8b732
AK		 679 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
680 iopm_base = 0;
681 return r;
682}
683
684static __exit void svm_hardware_unsetup(void)
685{
0da1db75
JR		 686 int cpu;
687
3230bb47 688 for_each_possible_cpu(cpu)
0da1db75
JR		 689 svm_cpu_uninit(cpu);
690
6aa8b732 691 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 692 iopm_base = 0;
6aa8b732
AK		 693}
694
695static void init_seg(struct vmcb_seg *seg)
696{
697 seg->selector = 0;
698 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 699 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 700 seg->limit = 0xffff;
701 seg->base = 0;
702}
703
704static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
705{
706 seg->selector = 0;
707 seg->attrib = SVM_SELECTOR_P_MASK | type;
708 seg->limit = 0xffff;
709 seg->base = 0;
710}
711
f4e1b3c8
ZA		 712static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
713{
714 struct vcpu_svm *svm = to_svm(vcpu);
715 u64 g_tsc_offset = 0;
716
717 if (is_nested(svm)) {
718 g_tsc_offset = svm->vmcb->control.tsc_offset -
719 svm->nested.hsave->control.tsc_offset;
720 svm->nested.hsave->control.tsc_offset = offset;
721 }
722
723 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
724}
725
e48672fa
ZA		 726static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
727{
728 struct vcpu_svm *svm = to_svm(vcpu);
729
730 svm->vmcb->control.tsc_offset += adjustment;
731 if (is_nested(svm))
732 svm->nested.hsave->control.tsc_offset += adjustment;
733}
734
e6101a96 735static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 736{
e6101a96
JR		 737 struct vmcb_control_area *control = &svm->vmcb->control;
738 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 739
bff78274
AK		 740 svm->vcpu.fpu_active = 1;
741
e0231715 742 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 743 INTERCEPT_CR3_MASK |
649d6864 744 INTERCEPT_CR4_MASK;
6aa8b732 745
e0231715 746 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 747 INTERCEPT_CR3_MASK |
80a8119c
AK		 748 INTERCEPT_CR4_MASK |
749 INTERCEPT_CR8_MASK;
6aa8b732 750
e0231715 751 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 752 INTERCEPT_DR1_MASK |
753 INTERCEPT_DR2_MASK |
727f5a23
JK		 754 INTERCEPT_DR3_MASK |
755 INTERCEPT_DR4_MASK |
756 INTERCEPT_DR5_MASK |
757 INTERCEPT_DR6_MASK |
758 INTERCEPT_DR7_MASK;
6aa8b732 759
e0231715 760 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 761 INTERCEPT_DR1_MASK |
762 INTERCEPT_DR2_MASK |
763 INTERCEPT_DR3_MASK |
727f5a23 764 INTERCEPT_DR4_MASK |
6aa8b732 765 INTERCEPT_DR5_MASK |
727f5a23 766 INTERCEPT_DR6_MASK |
6aa8b732
AK		 767 INTERCEPT_DR7_MASK;
768
7aa81cc0 769 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 770 (1 << UD_VECTOR) |
771 (1 << MC_VECTOR);
6aa8b732
AK		 772
773
e0231715 774 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 775 (1ULL << INTERCEPT_NMI) |
0152527b 776 (1ULL << INTERCEPT_SMI) |
d225157b 777 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 778 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 779 (1ULL << INTERCEPT_INVD) |
6aa8b732 780 (1ULL << INTERCEPT_HLT) |
a7052897 781 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 782 (1ULL << INTERCEPT_INVLPGA) |
783 (1ULL << INTERCEPT_IOIO_PROT) |
784 (1ULL << INTERCEPT_MSR_PROT) |
785 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 786 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 787 (1ULL << INTERCEPT_VMRUN) |
788 (1ULL << INTERCEPT_VMMCALL) |
789 (1ULL << INTERCEPT_VMLOAD) |
790 (1ULL << INTERCEPT_VMSAVE) |
791 (1ULL << INTERCEPT_STGI) |
792 (1ULL << INTERCEPT_CLGI) |
916ce236 793 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 794 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 795 (1ULL << INTERCEPT_MONITOR) |
796 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 797
798 control->iopm_base_pa = iopm_base;
f65c229c 799 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 800 control->int_ctl = V_INTR_MASKING_MASK;
801
802 init_seg(&save->es);
803 init_seg(&save->ss);
804 init_seg(&save->ds);
805 init_seg(&save->fs);
806 init_seg(&save->gs);
807
808 save->cs.selector = 0xf000;
809 /* Executable/Readable Code Segment */
810 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
811 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
812 save->cs.limit = 0xffff;
d92899a0
AK		 813 /*
814 * cs.base should really be 0xffff0000, but vmx can't handle that, so
815 * be consistent with it.
816 *
817 * Replace when we have real mode working for vmx.
818 */
819 save->cs.base = 0xf0000;
6aa8b732
AK		 820
821 save->gdtr.limit = 0xffff;
822 save->idtr.limit = 0xffff;
823
824 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
825 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
826
eaa48512 827 svm_set_efer(&svm->vcpu, 0);
d77c26fc 828 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 829 save->dr7 = 0x400;
830 save->rflags = 2;
831 save->rip = 0x0000fff0;
5fdbf976 832 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 833
e0231715
JR		 834 /*
835 * This is the guest-visible cr0 value.
18fa000a 836 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 837 */
678041ad
MT		 838 svm->vcpu.arch.cr0 = 0;
839 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 840
66aee91a 841 save->cr4 = X86_CR4_PAE;
6aa8b732 842 /* rdx = ?? */
709ddebf
JR		 843
844 if (npt_enabled) {
845 /* Setup VMCB for Nested Paging */
846 control->nested_ctl = 1;
a7052897
MT		 847 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
848 (1ULL << INTERCEPT_INVLPG));
709ddebf 849 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 850 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
851 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 852 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 853 save->cr3 = 0;
854 save->cr4 = 0;
855 }
a79d2f18 856 force_new_asid(&svm->vcpu);
1371d904 857
e6aa9abd 858 svm->nested.vmcb = 0;
2af9194d
JR		 859 svm->vcpu.arch.hflags = 0;
860
565d0998
ML		 861 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
862 control->pause_filter_count = 3000;
863 control->intercept |= (1ULL << INTERCEPT_PAUSE);
864 }
865
2af9194d 866 enable_gif(svm);
6aa8b732
AK		 867}
868
e00c8cf2 869static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 870{
871 struct vcpu_svm *svm = to_svm(vcpu);
872
e6101a96 873 init_vmcb(svm);
70433389 874
c5af89b6 875 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 876 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 877 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
878 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 879 }
5fdbf976
MT		 880 vcpu->arch.regs_avail = ~0;
881 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 882
883 return 0;
04d2cc77
AK		 884}
885
fb3f0f51 886static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 887{
a2fa3e9f 888 struct vcpu_svm *svm;
6aa8b732 889 struct page *page;
f65c229c 890 struct page *msrpm_pages;
b286d5d8 891 struct page *hsave_page;
3d6368ef 892 struct page *nested_msrpm_pages;
fb3f0f51 893 int err;
6aa8b732 894
c16f862d 895 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 896 if (!svm) {
897 err = -ENOMEM;
898 goto out;
899 }
900
901 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
902 if (err)
903 goto free_svm;
904
b7af4043 905 err = -ENOMEM;
6aa8b732 906 page = alloc_page(GFP_KERNEL);
b7af4043 907 if (!page)
fb3f0f51 908 goto uninit;
6aa8b732 909
f65c229c
JR		 910 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
911 if (!msrpm_pages)
b7af4043 912 goto free_page1;
3d6368ef
AG		 913
914 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
915 if (!nested_msrpm_pages)
b7af4043 916 goto free_page2;
f65c229c 917
b286d5d8
AG		 918 hsave_page = alloc_page(GFP_KERNEL);
919 if (!hsave_page)
b7af4043
TY		 920 goto free_page3;
921
e6aa9abd 922 svm->nested.hsave = page_address(hsave_page);
b286d5d8 923
b7af4043
TY		 924 svm->msrpm = page_address(msrpm_pages);
925 svm_vcpu_init_msrpm(svm->msrpm);
926
e6aa9abd 927 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 928 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 929
a2fa3e9f
GH		 930 svm->vmcb = page_address(page);
931 clear_page(svm->vmcb);
932 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
933 svm->asid_generation = 0;
e6101a96 934 init_vmcb(svm);
99e3e30a 935 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 936
10ab25cd
JK		 937 err = fx_init(&svm->vcpu);
938 if (err)
939 goto free_page4;
940
ad312c7c 941 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 942 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 943 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 944
fb3f0f51 945 return &svm->vcpu;
36241b8c 946
10ab25cd
JK		 947free_page4:
948 __free_page(hsave_page);
b7af4043
TY		 949free_page3:
950 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
951free_page2:
952 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
953free_page1:
954 __free_page(page);
fb3f0f51
RR		 955uninit:
956 kvm_vcpu_uninit(&svm->vcpu);
957free_svm:
a4770347 958 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 959out:
960 return ERR_PTR(err);
6aa8b732
AK		 961}
962
963static void svm_free_vcpu(struct kvm_vcpu *vcpu)
964{
a2fa3e9f
GH		 965 struct vcpu_svm *svm = to_svm(vcpu);
966
fb3f0f51 967 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 968 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 969 __free_page(virt_to_page(svm->nested.hsave));
970 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 971 kvm_vcpu_uninit(vcpu);
a4770347 972 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 973}
974
15ad7146 975static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 976{
a2fa3e9f 977 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 978 int i;
0cc5064d 979
0cc5064d 980 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 981 svm->asid_generation = 0;
0cc5064d 982 }
94dfbdb3
AL		 983
984 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 985 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 986}
987
988static void svm_vcpu_put(struct kvm_vcpu *vcpu)
989{
a2fa3e9f 990 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 991 int i;
992
e1beb1d3 993 ++vcpu->stat.host_state_reload;
94dfbdb3 994 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 995 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 996}
997
6aa8b732
AK		 998static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
999{
a2fa3e9f 1000 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1001}
1002
1003static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1004{
a2fa3e9f 1005 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1006}
1007
6de4f3ad
AK		 1008static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1009{
1010 switch (reg) {
1011 case VCPU_EXREG_PDPTR:
1012 BUG_ON(!npt_enabled);
ff03a073 1013 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1014 break;
1015 default:
1016 BUG();
1017 }
1018}
1019
f0b85051
AG		 1020static void svm_set_vintr(struct vcpu_svm *svm)
1021{
1022 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1023}
1024
1025static void svm_clear_vintr(struct vcpu_svm *svm)
1026{
1027 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1028}
1029
6aa8b732
AK		 1030static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1031{
a2fa3e9f 1032 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1033
1034 switch (seg) {
1035 case VCPU_SREG_CS: return &save->cs;
1036 case VCPU_SREG_DS: return &save->ds;
1037 case VCPU_SREG_ES: return &save->es;
1038 case VCPU_SREG_FS: return &save->fs;
1039 case VCPU_SREG_GS: return &save->gs;
1040 case VCPU_SREG_SS: return &save->ss;
1041 case VCPU_SREG_TR: return &save->tr;
1042 case VCPU_SREG_LDTR: return &save->ldtr;
1043 }
1044 BUG();
8b6d44c7 1045 return NULL;
6aa8b732
AK		 1046}
1047
1048static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1049{
1050 struct vmcb_seg *s = svm_seg(vcpu, seg);
1051
1052 return s->base;
1053}
1054
1055static void svm_get_segment(struct kvm_vcpu *vcpu,
1056 struct kvm_segment *var, int seg)
1057{
1058 struct vmcb_seg *s = svm_seg(vcpu, seg);
1059
1060 var->base = s->base;
1061 var->limit = s->limit;
1062 var->selector = s->selector;
1063 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1064 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1065 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1066 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1067 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1068 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1069 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1070 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1071
e0231715
JR		 1072 /*
1073 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1074 * for cross vendor migration purposes by "not present"
1075 */
1076 var->unusable = !var->present || (var->type == 0);
1077
1fbdc7a5
AP		 1078 switch (seg) {
1079 case VCPU_SREG_CS:
1080 /*
1081 * SVM always stores 0 for the 'G' bit in the CS selector in
1082 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1083 * Intel's VMENTRY has a check on the 'G' bit.
1084 */
25022acc 1085 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1086 break;
1087 case VCPU_SREG_TR:
1088 /*
1089 * Work around a bug where the busy flag in the tr selector
1090 * isn't exposed
1091 */
c0d09828 1092 var->type |= 0x2;
1fbdc7a5
AP		 1093 break;
1094 case VCPU_SREG_DS:
1095 case VCPU_SREG_ES:
1096 case VCPU_SREG_FS:
1097 case VCPU_SREG_GS:
1098 /*
1099 * The accessed bit must always be set in the segment
1100 * descriptor cache, although it can be cleared in the
1101 * descriptor, the cached bit always remains at 1. Since
1102 * Intel has a check on this, set it here to support
1103 * cross-vendor migration.
1104 */
1105 if (!var->unusable)
1106 var->type |= 0x1;
1107 break;
b586eb02 1108 case VCPU_SREG_SS:
e0231715
JR		 1109 /*
1110 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1111 * descriptor is left as 1, although the whole segment has
1112 * been made unusable. Clear it here to pass an Intel VMX
1113 * entry check when cross vendor migrating.
1114 */
1115 if (var->unusable)
1116 var->db = 0;
1117 break;
1fbdc7a5 1118 }
6aa8b732
AK		 1119}
1120
2e4d2653
IE		 1121static int svm_get_cpl(struct kvm_vcpu *vcpu)
1122{
1123 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1124
1125 return save->cpl;
1126}
1127
89a27f4d 1128static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1129{
a2fa3e9f
GH		 1130 struct vcpu_svm *svm = to_svm(vcpu);
1131
89a27f4d
GN		 1132 dt->size = svm->vmcb->save.idtr.limit;
1133 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1134}
1135
89a27f4d 1136static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1137{
a2fa3e9f
GH		 1138 struct vcpu_svm *svm = to_svm(vcpu);
1139
89a27f4d
GN		 1140 svm->vmcb->save.idtr.limit = dt->size;
1141 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1142}
1143
89a27f4d 1144static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1145{
a2fa3e9f
GH		 1146 struct vcpu_svm *svm = to_svm(vcpu);
1147
89a27f4d
GN		 1148 dt->size = svm->vmcb->save.gdtr.limit;
1149 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1150}
1151
89a27f4d 1152static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1153{
a2fa3e9f
GH		 1154 struct vcpu_svm *svm = to_svm(vcpu);
1155
89a27f4d
GN		 1156 svm->vmcb->save.gdtr.limit = dt->size;
1157 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1158}
1159
e8467fda
AK		 1160static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1161{
1162}
1163
25c4c276 1164static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1165{
1166}
1167
d225157b
AK		 1168static void update_cr0_intercept(struct vcpu_svm *svm)
1169{
66a562f7 1170 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1171 ulong gcr0 = svm->vcpu.arch.cr0;
1172 u64 *hcr0 = &svm->vmcb->save.cr0;
1173
1174 if (!svm->vcpu.fpu_active)
1175 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1176 else
1177 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1178 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1179
1180
1181 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1182 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1183 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1184 if (is_nested(svm)) {
1185 struct vmcb *hsave = svm->nested.hsave;
1186
1187 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1188 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1189 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1190 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1191 }
d225157b
AK		 1192 } else {
1193 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1194 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1195 if (is_nested(svm)) {
1196 struct vmcb *hsave = svm->nested.hsave;
1197
1198 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1199 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1200 }
d225157b
AK		 1201 }
1202}
1203
6aa8b732
AK		 1204static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1205{
a2fa3e9f
GH		 1206 struct vcpu_svm *svm = to_svm(vcpu);
1207
7f5d8b56
JR		 1208 if (is_nested(svm)) {
1209 /*
1210 * We are here because we run in nested mode, the host kvm
1211 * intercepts cr0 writes but the l1 hypervisor does not.
1212 * But the L1 hypervisor may intercept selective cr0 writes.
1213 * This needs to be checked here.
1214 */
1215 unsigned long old, new;
1216
1217 /* Remove bits that would trigger a real cr0 write intercept */
1218 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1219 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1220
1221 if (old == new) {
1222 /* cr0 write with ts and mp unchanged */
1223 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1224 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1225 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1226 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1227 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1228 return;
cda00082 1229 }
7f5d8b56
JR		 1230 }
1231 }
1232
05b3e0c2 1233#ifdef CONFIG_X86_64
f6801dff 1234 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1235 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1236 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1237 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1238 }
1239
d77c26fc 1240 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1241 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1242 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1243 }
1244 }
1245#endif
ad312c7c 1246 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1247
1248 if (!npt_enabled)
1249 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1250
1251 if (!vcpu->fpu_active)
334df50a 1252 cr0 |= X86_CR0_TS;
709ddebf
JR		 1253 /*
1254 * re-enable caching here because the QEMU bios
1255 * does not do it - this results in some delay at
1256 * reboot
1257 */
1258 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1259 svm->vmcb->save.cr0 = cr0;
d225157b 1260 update_cr0_intercept(svm);
6aa8b732
AK		 1261}
1262
1263static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1264{
6394b649 1265 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1266 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1267
1268 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1269 force_new_asid(vcpu);
6394b649 1270
ec077263
JR		 1271 vcpu->arch.cr4 = cr4;
1272 if (!npt_enabled)
1273 cr4 |= X86_CR4_PAE;
6394b649 1274 cr4 |= host_cr4_mce;
ec077263 1275 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1276}
1277
1278static void svm_set_segment(struct kvm_vcpu *vcpu,
1279 struct kvm_segment *var, int seg)
1280{
a2fa3e9f 1281 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1282 struct vmcb_seg *s = svm_seg(vcpu, seg);
1283
1284 s->base = var->base;
1285 s->limit = var->limit;
1286 s->selector = var->selector;
1287 if (var->unusable)
1288 s->attrib = 0;
1289 else {
1290 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1291 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1292 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1293 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1294 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1295 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1296 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1297 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1298 }
1299 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1300 svm->vmcb->save.cpl
1301 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1302 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1303
1304}
1305
44c11430 1306static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1307{
d0bfb940
JK		 1308 struct vcpu_svm *svm = to_svm(vcpu);
1309
d0bfb940
JK		 1310 svm->vmcb->control.intercept_exceptions &=
1311 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1312
6be7d306 1313 if (svm->nmi_singlestep)
44c11430
GN		 1314 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1315
d0bfb940
JK		 1316 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1317 if (vcpu->guest_debug &
1318 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1319 svm->vmcb->control.intercept_exceptions |=
1320 1 << DB_VECTOR;
1321 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1322 svm->vmcb->control.intercept_exceptions |=
1323 1 << BP_VECTOR;
1324 } else
1325 vcpu->guest_debug = 0;
44c11430
GN		 1326}
1327
355be0b9 1328static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1329{
44c11430
GN		 1330 struct vcpu_svm *svm = to_svm(vcpu);
1331
ae675ef0
JK		 1332 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1333 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1334 else
1335 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1336
355be0b9 1337 update_db_intercept(vcpu);
6aa8b732
AK		 1338}
1339
1340static void load_host_msrs(struct kvm_vcpu *vcpu)
1341{
94dfbdb3 1342#ifdef CONFIG_X86_64
a2fa3e9f 1343 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1344#endif
6aa8b732
AK		 1345}
1346
1347static void save_host_msrs(struct kvm_vcpu *vcpu)
1348{
94dfbdb3 1349#ifdef CONFIG_X86_64
a2fa3e9f 1350 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1351#endif
6aa8b732
AK		 1352}
1353
0fe1e009 1354static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1355{
0fe1e009
TH		 1356 if (sd->next_asid > sd->max_asid) {
1357 ++sd->asid_generation;
1358 sd->next_asid = 1;
a2fa3e9f 1359 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1360 }
1361
0fe1e009
TH		 1362 svm->asid_generation = sd->asid_generation;
1363 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1364}
1365
020df079 1366static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1367{
42dbaa5a 1368 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1369
020df079 1370 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1371}
1372
851ba692 1373static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1374{
6aa8b732
AK		 1375 u64 fault_address;
1376 u32 error_code;
6aa8b732 1377
a2fa3e9f
GH		 1378 fault_address = svm->vmcb->control.exit_info_2;
1379 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1380
229456fc 1381 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1382 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1383 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1384 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1385}
1386
851ba692 1387static int db_interception(struct vcpu_svm *svm)
d0bfb940 1388{
851ba692
AK		 1389 struct kvm_run *kvm_run = svm->vcpu.run;
1390
d0bfb940 1391 if (!(svm->vcpu.guest_debug &
44c11430 1392 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1393 !svm->nmi_singlestep) {
d0bfb940
JK		 1394 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1395 return 1;
1396 }
44c11430 1397
6be7d306
JK		 1398 if (svm->nmi_singlestep) {
1399 svm->nmi_singlestep = false;
44c11430
GN		 1400 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1401 svm->vmcb->save.rflags &=
1402 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1403 update_db_intercept(&svm->vcpu);
1404 }
1405
1406 if (svm->vcpu.guest_debug &
e0231715 1407 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1408 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1409 kvm_run->debug.arch.pc =
1410 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1411 kvm_run->debug.arch.exception = DB_VECTOR;
1412 return 0;
1413 }
1414
1415 return 1;
d0bfb940
JK		 1416}
1417
851ba692 1418static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1419{
851ba692
AK		 1420 struct kvm_run *kvm_run = svm->vcpu.run;
1421
d0bfb940
JK		 1422 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1423 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1424 kvm_run->debug.arch.exception = BP_VECTOR;
1425 return 0;
1426}
1427
851ba692 1428static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1429{
1430 int er;
1431
851ba692 1432 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1433 if (er != EMULATE_DONE)
7ee5d940 1434 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1435 return 1;
1436}
1437
6b52d186 1438static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1439{
6b52d186 1440 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1441 u32 excp;
1442
1443 if (is_nested(svm)) {
1444 u32 h_excp, n_excp;
1445
1446 h_excp = svm->nested.hsave->control.intercept_exceptions;
1447 n_excp = svm->nested.intercept_exceptions;
1448 h_excp &= ~(1 << NM_VECTOR);
1449 excp = h_excp | n_excp;
1450 } else {
1451 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1452 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1453 }
1454
1455 svm->vmcb->control.intercept_exceptions = excp;
1456
e756fc62 1457 svm->vcpu.fpu_active = 1;
d225157b 1458 update_cr0_intercept(svm);
6b52d186 1459}
a2fa3e9f 1460
6b52d186
AK		 1461static int nm_interception(struct vcpu_svm *svm)
1462{
1463 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1464 return 1;
7807fa6c
AL		 1465}
1466
67ec6607
JR		 1467static bool is_erratum_383(void)
1468{
1469 int err, i;
1470 u64 value;
1471
1472 if (!erratum_383_found)
1473 return false;
1474
1475 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1476 if (err)
1477 return false;
1478
1479 /* Bit 62 may or may not be set for this mce */
1480 value &= ~(1ULL << 62);
1481
1482 if (value != 0xb600000000010015ULL)
1483 return false;
1484
1485 /* Clear MCi_STATUS registers */
1486 for (i = 0; i < 6; ++i)
1487 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1488
1489 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1490 if (!err) {
1491 u32 low, high;
1492
1493 value &= ~(1ULL << 2);
1494 low = lower_32_bits(value);
1495 high = upper_32_bits(value);
1496
1497 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1498 }
1499
1500 /* Flush tlb to evict multi-match entries */
1501 __flush_tlb_all();
1502
1503 return true;
1504}
1505
fe5913e4 1506static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1507{
67ec6607
JR		 1508 if (is_erratum_383()) {
1509 /*
1510 * Erratum 383 triggered. Guest state is corrupt so kill the
1511 * guest.
1512 */
1513 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1514
a8eeb04a 1515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1516
1517 return;
1518 }
1519
53371b50
JR		 1520 /*
1521 * On an #MC intercept the MCE handler is not called automatically in
1522 * the host. So do it by hand here.
1523 */
1524 asm volatile (
1525 "int $0x12\n");
1526 /* not sure if we ever come back to this point */
1527
fe5913e4
JR		 1528 return;
1529}
1530
1531static int mc_interception(struct vcpu_svm *svm)
1532{
53371b50
JR		 1533 return 1;
1534}
1535
851ba692 1536static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1537{
851ba692
AK		 1538 struct kvm_run *kvm_run = svm->vcpu.run;
1539
46fe4ddd
JR		 1540 /*
1541 * VMCB is undefined after a SHUTDOWN intercept
1542 * so reinitialize it.
1543 */
a2fa3e9f 1544 clear_page(svm->vmcb);
e6101a96 1545 init_vmcb(svm);
46fe4ddd
JR		 1546
1547 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1548 return 0;
1549}
1550
851ba692 1551static int io_interception(struct vcpu_svm *svm)
6aa8b732 1552{
cf8f70bf 1553 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1554 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1555 int size, in, string;
039576c0 1556 unsigned port;
6aa8b732 1557
e756fc62 1558 ++svm->vcpu.stat.io_exits;
e70669ab 1559 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1560 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1561 if (string || in)
6d77dbfc 1562 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1563
039576c0
AK		 1564 port = io_info >> 16;
1565 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1566 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1567 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1568
1569 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1570}
1571
851ba692 1572static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1573{
1574 return 1;
1575}
1576
851ba692 1577static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1578{
1579 ++svm->vcpu.stat.irq_exits;
1580 return 1;
1581}
1582
851ba692 1583static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1584{
1585 return 1;
1586}
1587
851ba692 1588static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1589{
5fdbf976 1590 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1591 skip_emulated_instruction(&svm->vcpu);
1592 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1593}
1594
851ba692 1595static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1596{
5fdbf976 1597 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1598 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1599 kvm_emulate_hypercall(&svm->vcpu);
1600 return 1;
02e235bc
AK		 1601}
1602
c0725420
AG		 1603static int nested_svm_check_permissions(struct vcpu_svm *svm)
1604{
f6801dff 1605 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1606 || !is_paging(&svm->vcpu)) {
1607 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1608 return 1;
1609 }
1610
1611 if (svm->vmcb->save.cpl) {
1612 kvm_inject_gp(&svm->vcpu, 0);
1613 return 1;
1614 }
1615
1616 return 0;
1617}
1618
cf74a78b
AG		 1619static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1620 bool has_error_code, u32 error_code)
1621{
b8e88bc8
JR		 1622 int vmexit;
1623
0295ad7d
JR		 1624 if (!is_nested(svm))
1625 return 0;
cf74a78b 1626
0295ad7d
JR		 1627 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1628 svm->vmcb->control.exit_code_hi = 0;
1629 svm->vmcb->control.exit_info_1 = error_code;
1630 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1631
b8e88bc8
JR		 1632 vmexit = nested_svm_intercept(svm);
1633 if (vmexit == NESTED_EXIT_DONE)
1634 svm->nested.exit_required = true;
1635
1636 return vmexit;
cf74a78b
AG		 1637}
1638
8fe54654
JR		 1639/* This function returns true if it is save to enable the irq window */
1640static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1641{
26666957 1642 if (!is_nested(svm))
8fe54654 1643 return true;
cf74a78b 1644
26666957 1645 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1646 return true;
cf74a78b 1647
26666957 1648 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1649 return false;
cf74a78b 1650
197717d5
JR		 1651 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1652 svm->vmcb->control.exit_info_1 = 0;
1653 svm->vmcb->control.exit_info_2 = 0;
26666957 1654
cd3ff653
JR		 1655 if (svm->nested.intercept & 1ULL) {
1656 /*
1657 * The #vmexit can't be emulated here directly because this
1658 * code path runs with irqs and preemtion disabled. A
1659 * #vmexit emulation might sleep. Only signal request for
1660 * the #vmexit here.
1661 */
1662 svm->nested.exit_required = true;
236649de 1663 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1664 return false;
cf74a78b
AG		 1665 }
1666
8fe54654 1667 return true;
cf74a78b
AG		 1668}
1669
887f500c
JR		 1670/* This function returns true if it is save to enable the nmi window */
1671static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1672{
1673 if (!is_nested(svm))
1674 return true;
1675
1676 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1677 return true;
1678
1679 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1680 svm->nested.exit_required = true;
1681
1682 return false;
cf74a78b
AG		 1683}
1684
7597f129 1685static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1686{
1687 struct page *page;
1688
6c3bd3d7
JR		 1689 might_sleep();
1690
34f80cfa 1691 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1692 if (is_error_page(page))
1693 goto error;
1694
7597f129
JR		 1695 *_page = page;
1696
1697 return kmap(page);
34f80cfa
JR		 1698
1699error:
1700 kvm_release_page_clean(page);
1701 kvm_inject_gp(&svm->vcpu, 0);
1702
1703 return NULL;
1704}
1705
7597f129 1706static void nested_svm_unmap(struct page *page)
34f80cfa 1707{
7597f129 1708 kunmap(page);
34f80cfa
JR		 1709 kvm_release_page_dirty(page);
1710}
34f80cfa 1711
ce2ac085
JR		 1712static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1713{
1714 unsigned port;
1715 u8 val, bit;
1716 u64 gpa;
34f80cfa 1717
ce2ac085
JR		 1718 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1719 return NESTED_EXIT_HOST;
34f80cfa 1720
ce2ac085
JR		 1721 port = svm->vmcb->control.exit_info_1 >> 16;
1722 gpa = svm->nested.vmcb_iopm + (port / 8);
1723 bit = port % 8;
1724 val = 0;
1725
1726 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1727 val &= (1 << bit);
1728
1729 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1730}
1731
d2477826 1732static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1733{
0d6b3537
JR		 1734 u32 offset, msr, value;
1735 int write, mask;
4c2161ae 1736
3d62d9aa 1737 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1738 return NESTED_EXIT_HOST;
3d62d9aa 1739
0d6b3537
JR		 1740 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1741 offset = svm_msrpm_offset(msr);
1742 write = svm->vmcb->control.exit_info_1 & 1;
1743 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1744
0d6b3537
JR		 1745 if (offset == MSR_INVALID)
1746 return NESTED_EXIT_DONE;
4c2161ae 1747
0d6b3537
JR		 1748 /* Offset is in 32 bit units but need in 8 bit units */
1749 offset *= 4;
4c2161ae 1750
0d6b3537
JR		 1751 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1752 return NESTED_EXIT_DONE;
3d62d9aa 1753
0d6b3537 1754 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1755}
1756
410e4d57 1757static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1758{
cf74a78b 1759 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1760
410e4d57
JR		 1761 switch (exit_code) {
1762 case SVM_EXIT_INTR:
1763 case SVM_EXIT_NMI:
ff47a49b 1764 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1765 return NESTED_EXIT_HOST;
410e4d57 1766 case SVM_EXIT_NPF:
e0231715 1767 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1768 if (npt_enabled)
1769 return NESTED_EXIT_HOST;
1770 break;
410e4d57 1771 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1772 /* When we're shadowing, trap PFs */
410e4d57
JR		 1773 if (!npt_enabled)
1774 return NESTED_EXIT_HOST;
1775 break;
66a562f7
JR		 1776 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1777 nm_interception(svm);
1778 break;
410e4d57
JR		 1779 default:
1780 break;
cf74a78b
AG		 1781 }
1782
410e4d57
JR		 1783 return NESTED_EXIT_CONTINUE;
1784}
1785
1786/*
1787 * If this function returns true, this #vmexit was already handled
1788 */
b8e88bc8 1789static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1790{
1791 u32 exit_code = svm->vmcb->control.exit_code;
1792 int vmexit = NESTED_EXIT_HOST;
1793
cf74a78b 1794 switch (exit_code) {
9c4e40b9 1795 case SVM_EXIT_MSR:
3d62d9aa 1796 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1797 break;
ce2ac085
JR		 1798 case SVM_EXIT_IOIO:
1799 vmexit = nested_svm_intercept_ioio(svm);
1800 break;
cf74a78b
AG		 1801 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1802 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1803 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1804 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1805 break;
1806 }
1807 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1808 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1809 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1810 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1811 break;
1812 }
1813 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1814 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1815 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1816 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1817 break;
1818 }
1819 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1820 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1821 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1822 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1823 break;
1824 }
1825 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1826 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1827 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1828 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1829 break;
1830 }
228070b1
JR		 1831 case SVM_EXIT_ERR: {
1832 vmexit = NESTED_EXIT_DONE;
1833 break;
1834 }
cf74a78b
AG		 1835 default: {
1836 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1837 if (svm->nested.intercept & exit_bits)
410e4d57 1838 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1839 }
1840 }
1841
b8e88bc8
JR		 1842 return vmexit;
1843}
1844
1845static int nested_svm_exit_handled(struct vcpu_svm *svm)
1846{
1847 int vmexit;
1848
1849 vmexit = nested_svm_intercept(svm);
1850
1851 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1852 nested_svm_vmexit(svm);
9c4e40b9
JR		 1853
1854 return vmexit;
cf74a78b
AG		 1855}
1856
0460a979
JR		 1857static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1858{
1859 struct vmcb_control_area *dst = &dst_vmcb->control;
1860 struct vmcb_control_area *from = &from_vmcb->control;
1861
1862 dst->intercept_cr_read = from->intercept_cr_read;
1863 dst->intercept_cr_write = from->intercept_cr_write;
1864 dst->intercept_dr_read = from->intercept_dr_read;
1865 dst->intercept_dr_write = from->intercept_dr_write;
1866 dst->intercept_exceptions = from->intercept_exceptions;
1867 dst->intercept = from->intercept;
1868 dst->iopm_base_pa = from->iopm_base_pa;
1869 dst->msrpm_base_pa = from->msrpm_base_pa;
1870 dst->tsc_offset = from->tsc_offset;
1871 dst->asid = from->asid;
1872 dst->tlb_ctl = from->tlb_ctl;
1873 dst->int_ctl = from->int_ctl;
1874 dst->int_vector = from->int_vector;
1875 dst->int_state = from->int_state;
1876 dst->exit_code = from->exit_code;
1877 dst->exit_code_hi = from->exit_code_hi;
1878 dst->exit_info_1 = from->exit_info_1;
1879 dst->exit_info_2 = from->exit_info_2;
1880 dst->exit_int_info = from->exit_int_info;
1881 dst->exit_int_info_err = from->exit_int_info_err;
1882 dst->nested_ctl = from->nested_ctl;
1883 dst->event_inj = from->event_inj;
1884 dst->event_inj_err = from->event_inj_err;
1885 dst->nested_cr3 = from->nested_cr3;
1886 dst->lbr_ctl = from->lbr_ctl;
1887}
1888
34f80cfa 1889static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1890{
34f80cfa 1891 struct vmcb *nested_vmcb;
e6aa9abd 1892 struct vmcb *hsave = svm->nested.hsave;
33740e40 1893 struct vmcb *vmcb = svm->vmcb;
7597f129 1894 struct page *page;
cf74a78b 1895
17897f36
JR		 1896 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1897 vmcb->control.exit_info_1,
1898 vmcb->control.exit_info_2,
1899 vmcb->control.exit_int_info,
1900 vmcb->control.exit_int_info_err);
1901
7597f129 1902 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1903 if (!nested_vmcb)
1904 return 1;
1905
06fc7772
JR		 1906 /* Exit nested SVM mode */
1907 svm->nested.vmcb = 0;
1908
cf74a78b 1909 /* Give the current vmcb to the guest */
33740e40
JR		 1910 disable_gif(svm);
1911
1912 nested_vmcb->save.es = vmcb->save.es;
1913 nested_vmcb->save.cs = vmcb->save.cs;
1914 nested_vmcb->save.ss = vmcb->save.ss;
1915 nested_vmcb->save.ds = vmcb->save.ds;
1916 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1917 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 1918 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 1919 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1920 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1921 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1922 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1923 nested_vmcb->save.rflags = vmcb->save.rflags;
1924 nested_vmcb->save.rip = vmcb->save.rip;
1925 nested_vmcb->save.rsp = vmcb->save.rsp;
1926 nested_vmcb->save.rax = vmcb->save.rax;
1927 nested_vmcb->save.dr7 = vmcb->save.dr7;
1928 nested_vmcb->save.dr6 = vmcb->save.dr6;
1929 nested_vmcb->save.cpl = vmcb->save.cpl;
1930
1931 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1932 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1933 nested_vmcb->control.int_state = vmcb->control.int_state;
1934 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1935 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1936 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1937 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1938 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1939 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 1940 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 1941
1942 /*
1943 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1944 * to make sure that we do not lose injected events. So check event_inj
1945 * here and copy it to exit_int_info if it is valid.
1946 * Exit_int_info and event_inj can't be both valid because the case
1947 * below only happens on a VMRUN instruction intercept which has
1948 * no valid exit_int_info set.
1949 */
1950 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1951 struct vmcb_control_area *nc = &nested_vmcb->control;
1952
1953 nc->exit_int_info = vmcb->control.event_inj;
1954 nc->exit_int_info_err = vmcb->control.event_inj_err;
1955 }
1956
33740e40
JR		 1957 nested_vmcb->control.tlb_ctl = 0;
1958 nested_vmcb->control.event_inj = 0;
1959 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1960
1961 /* We always set V_INTR_MASKING and remember the old value in hflags */
1962 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1963 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1964
cf74a78b 1965 /* Restore the original control entries */
0460a979 1966 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1967
219b65dc
AG		 1968 kvm_clear_exception_queue(&svm->vcpu);
1969 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1970
1971 /* Restore selected save entries */
1972 svm->vmcb->save.es = hsave->save.es;
1973 svm->vmcb->save.cs = hsave->save.cs;
1974 svm->vmcb->save.ss = hsave->save.ss;
1975 svm->vmcb->save.ds = hsave->save.ds;
1976 svm->vmcb->save.gdtr = hsave->save.gdtr;
1977 svm->vmcb->save.idtr = hsave->save.idtr;
1978 svm->vmcb->save.rflags = hsave->save.rflags;
1979 svm_set_efer(&svm->vcpu, hsave->save.efer);
1980 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1981 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1982 if (npt_enabled) {
1983 svm->vmcb->save.cr3 = hsave->save.cr3;
1984 svm->vcpu.arch.cr3 = hsave->save.cr3;
1985 } else {
2390218b 1986 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 1987 }
1988 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1989 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1990 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1991 svm->vmcb->save.dr7 = 0;
1992 svm->vmcb->save.cpl = 0;
1993 svm->vmcb->control.exit_int_info = 0;
1994
7597f129 1995 nested_svm_unmap(page);
cf74a78b
AG		 1996
1997 kvm_mmu_reset_context(&svm->vcpu);
1998 kvm_mmu_load(&svm->vcpu);
1999
2000 return 0;
2001}
3d6368ef 2002
9738b2c9 2003static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2004{
323c3d80
JR		 2005 /*
2006 * This function merges the msr permission bitmaps of kvm and the
2007 * nested vmcb. It is omptimized in that it only merges the parts where
2008 * the kvm msr permission bitmap may contain zero bits
2009 */
3d6368ef 2010 int i;
9738b2c9 2011
323c3d80
JR		 2012 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2013 return true;
9738b2c9 2014
323c3d80
JR		 2015 for (i = 0; i < MSRPM_OFFSETS; i++) {
2016 u32 value, p;
2017 u64 offset;
9738b2c9 2018
323c3d80
JR		 2019 if (msrpm_offsets[i] == 0xffffffff)
2020 break;
3d6368ef 2021
0d6b3537
JR		 2022 p = msrpm_offsets[i];
2023 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2024
2025 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2026 return false;
2027
2028 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2029 }
3d6368ef 2030
323c3d80 2031 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2032
2033 return true;
3d6368ef
AG		 2034}
2035
52c65a30
JR		 2036static bool nested_vmcb_checks(struct vmcb *vmcb)
2037{
2038 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2039 return false;
2040
dbe77584
JR		 2041 if (vmcb->control.asid == 0)
2042 return false;
2043
52c65a30
JR		 2044 return true;
2045}
2046
9738b2c9 2047static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2048{
9738b2c9 2049 struct vmcb *nested_vmcb;
e6aa9abd 2050 struct vmcb *hsave = svm->nested.hsave;
defbba56 2051 struct vmcb *vmcb = svm->vmcb;
7597f129 2052 struct page *page;
06fc7772 2053 u64 vmcb_gpa;
3d6368ef 2054
06fc7772 2055 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2056
7597f129 2057 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2058 if (!nested_vmcb)
2059 return false;
2060
52c65a30
JR		 2061 if (!nested_vmcb_checks(nested_vmcb)) {
2062 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2063 nested_vmcb->control.exit_code_hi = 0;
2064 nested_vmcb->control.exit_info_1 = 0;
2065 nested_vmcb->control.exit_info_2 = 0;
2066
2067 nested_svm_unmap(page);
2068
2069 return false;
2070 }
2071
b75f4eb3 2072 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2073 nested_vmcb->save.rip,
2074 nested_vmcb->control.int_ctl,
2075 nested_vmcb->control.event_inj,
2076 nested_vmcb->control.nested_ctl);
2077
2e554e8d
JR		 2078 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2079 nested_vmcb->control.intercept_cr_write,
2080 nested_vmcb->control.intercept_exceptions,
2081 nested_vmcb->control.intercept);
2082
3d6368ef 2083 /* Clear internal status */
219b65dc
AG		 2084 kvm_clear_exception_queue(&svm->vcpu);
2085 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2086
e0231715
JR		 2087 /*
2088 * Save the old vmcb, so we don't need to pick what we save, but can
2089 * restore everything when a VMEXIT occurs
2090 */
defbba56
JR		 2091 hsave->save.es = vmcb->save.es;
2092 hsave->save.cs = vmcb->save.cs;
2093 hsave->save.ss = vmcb->save.ss;
2094 hsave->save.ds = vmcb->save.ds;
2095 hsave->save.gdtr = vmcb->save.gdtr;
2096 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2097 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2098 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2099 hsave->save.cr4 = svm->vcpu.arch.cr4;
2100 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2101 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2102 hsave->save.rsp = vmcb->save.rsp;
2103 hsave->save.rax = vmcb->save.rax;
2104 if (npt_enabled)
2105 hsave->save.cr3 = vmcb->save.cr3;
2106 else
2107 hsave->save.cr3 = svm->vcpu.arch.cr3;
2108
0460a979 2109 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2110
2111 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2112 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2113 else
2114 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2115
2116 /* Load the nested guest state */
2117 svm->vmcb->save.es = nested_vmcb->save.es;
2118 svm->vmcb->save.cs = nested_vmcb->save.cs;
2119 svm->vmcb->save.ss = nested_vmcb->save.ss;
2120 svm->vmcb->save.ds = nested_vmcb->save.ds;
2121 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2122 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2123 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2124 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2125 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2126 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2127 if (npt_enabled) {
2128 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2129 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2130 } else
2390218b 2131 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2132
2133 /* Guest paging mode is active - reset mmu */
2134 kvm_mmu_reset_context(&svm->vcpu);
2135
defbba56 2136 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2137 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2138 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2139 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2140
3d6368ef
AG		 2141 /* In case we don't even reach vcpu_run, the fields are not updated */
2142 svm->vmcb->save.rax = nested_vmcb->save.rax;
2143 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2144 svm->vmcb->save.rip = nested_vmcb->save.rip;
2145 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2146 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2147 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2148
f7138538 2149 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2150 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2151
aad42c64
JR		 2152 /* cache intercepts */
2153 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2154 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2155 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2156 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2157 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2158 svm->nested.intercept = nested_vmcb->control.intercept;
2159
3d6368ef 2160 force_new_asid(&svm->vcpu);
3d6368ef 2161 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2162 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2163 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2164 else
2165 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2166
88ab24ad
JR		 2167 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2168 /* We only want the cr8 intercept bits of the guest */
2169 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2170 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2171 }
2172
0d945bd9
JR		 2173 /* We don't want to see VMMCALLs from a nested guest */
2174 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2175
e0231715
JR		 2176 /*
2177 * We don't want a nested guest to be more powerful than the guest, so
2178 * all intercepts are ORed
2179 */
88ab24ad
JR		 2180 svm->vmcb->control.intercept_cr_read |=
2181 nested_vmcb->control.intercept_cr_read;
2182 svm->vmcb->control.intercept_cr_write |=
2183 nested_vmcb->control.intercept_cr_write;
2184 svm->vmcb->control.intercept_dr_read |=
2185 nested_vmcb->control.intercept_dr_read;
2186 svm->vmcb->control.intercept_dr_write |=
2187 nested_vmcb->control.intercept_dr_write;
2188 svm->vmcb->control.intercept_exceptions |=
2189 nested_vmcb->control.intercept_exceptions;
2190
2191 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2192
2193 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2194 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2195 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2196 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2197 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2198 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2199
7597f129 2200 nested_svm_unmap(page);
9738b2c9 2201
06fc7772
JR		 2202 /* nested_vmcb is our indicator if nested SVM is activated */
2203 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2204
2af9194d 2205 enable_gif(svm);
3d6368ef 2206
9738b2c9 2207 return true;
3d6368ef
AG		 2208}
2209
9966bf68 2210static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2211{
2212 to_vmcb->save.fs = from_vmcb->save.fs;
2213 to_vmcb->save.gs = from_vmcb->save.gs;
2214 to_vmcb->save.tr = from_vmcb->save.tr;
2215 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2216 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2217 to_vmcb->save.star = from_vmcb->save.star;
2218 to_vmcb->save.lstar = from_vmcb->save.lstar;
2219 to_vmcb->save.cstar = from_vmcb->save.cstar;
2220 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2221 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2222 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2223 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2224}
2225
851ba692 2226static int vmload_interception(struct vcpu_svm *svm)
5542675b 2227{
9966bf68 2228 struct vmcb *nested_vmcb;
7597f129 2229 struct page *page;
9966bf68 2230
5542675b
AG		 2231 if (nested_svm_check_permissions(svm))
2232 return 1;
2233
2234 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2235 skip_emulated_instruction(&svm->vcpu);
2236
7597f129 2237 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2238 if (!nested_vmcb)
2239 return 1;
2240
2241 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2242 nested_svm_unmap(page);
5542675b
AG		 2243
2244 return 1;
2245}
2246
851ba692 2247static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2248{
9966bf68 2249 struct vmcb *nested_vmcb;
7597f129 2250 struct page *page;
9966bf68 2251
5542675b
AG		 2252 if (nested_svm_check_permissions(svm))
2253 return 1;
2254
2255 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2256 skip_emulated_instruction(&svm->vcpu);
2257
7597f129 2258 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2259 if (!nested_vmcb)
2260 return 1;
2261
2262 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2263 nested_svm_unmap(page);
5542675b
AG		 2264
2265 return 1;
2266}
2267
851ba692 2268static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2269{
3d6368ef
AG		 2270 if (nested_svm_check_permissions(svm))
2271 return 1;
2272
b75f4eb3
RJ		 2273 /* Save rip after vmrun instruction */
2274 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2275
9738b2c9 2276 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2277 return 1;
2278
9738b2c9 2279 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2280 goto failed;
2281
2282 return 1;
2283
2284failed:
2285
2286 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2287 svm->vmcb->control.exit_code_hi = 0;
2288 svm->vmcb->control.exit_info_1 = 0;
2289 svm->vmcb->control.exit_info_2 = 0;
2290
2291 nested_svm_vmexit(svm);
3d6368ef
AG		 2292
2293 return 1;
2294}
2295
851ba692 2296static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2297{
2298 if (nested_svm_check_permissions(svm))
2299 return 1;
2300
2301 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2302 skip_emulated_instruction(&svm->vcpu);
2303
2af9194d 2304 enable_gif(svm);
1371d904
AG		 2305
2306 return 1;
2307}
2308
851ba692 2309static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2310{
2311 if (nested_svm_check_permissions(svm))
2312 return 1;
2313
2314 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2315 skip_emulated_instruction(&svm->vcpu);
2316
2af9194d 2317 disable_gif(svm);
1371d904
AG		 2318
2319 /* After a CLGI no interrupts should come */
2320 svm_clear_vintr(svm);
2321 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2322
2323 return 1;
2324}
2325
851ba692 2326static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2327{
2328 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2329
ec1ff790
JR		 2330 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2331 vcpu->arch.regs[VCPU_REGS_RAX]);
2332
ff092385
AG		 2333 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2334 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2335
2336 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2337 skip_emulated_instruction(&svm->vcpu);
2338 return 1;
2339}
2340
532a46b9
JR		 2341static int skinit_interception(struct vcpu_svm *svm)
2342{
2343 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2344
2345 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2346 return 1;
2347}
2348
851ba692 2349static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2350{
7ee5d940 2351 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2352 return 1;
2353}
2354
851ba692 2355static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2356{
37817f29 2357 u16 tss_selector;
64a7ec06
GN		 2358 int reason;
2359 int int_type = svm->vmcb->control.exit_int_info &
2360 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2361 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2362 uint32_t type =
2363 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2364 uint32_t idt_v =
2365 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2366 bool has_error_code = false;
2367 u32 error_code = 0;
37817f29
IE		 2368
2369 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2370
37817f29
IE		 2371 if (svm->vmcb->control.exit_info_2 &
2372 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2373 reason = TASK_SWITCH_IRET;
2374 else if (svm->vmcb->control.exit_info_2 &
2375 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2376 reason = TASK_SWITCH_JMP;
fe8e7f83 2377 else if (idt_v)
64a7ec06
GN		 2378 reason = TASK_SWITCH_GATE;
2379 else
2380 reason = TASK_SWITCH_CALL;
2381
fe8e7f83
GN		 2382 if (reason == TASK_SWITCH_GATE) {
2383 switch (type) {
2384 case SVM_EXITINTINFO_TYPE_NMI:
2385 svm->vcpu.arch.nmi_injected = false;
2386 break;
2387 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2388 if (svm->vmcb->control.exit_info_2 &
2389 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2390 has_error_code = true;
2391 error_code =
2392 (u32)svm->vmcb->control.exit_info_2;
2393 }
fe8e7f83
GN		 2394 kvm_clear_exception_queue(&svm->vcpu);
2395 break;
2396 case SVM_EXITINTINFO_TYPE_INTR:
2397 kvm_clear_interrupt_queue(&svm->vcpu);
2398 break;
2399 default:
2400 break;
2401 }
2402 }
64a7ec06 2403
8317c298
GN		 2404 if (reason != TASK_SWITCH_GATE ||
2405 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2406 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2407 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2408 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2409
acb54517
GN		 2410 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2411 has_error_code, error_code) == EMULATE_FAIL) {
2412 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2413 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2414 svm->vcpu.run->internal.ndata = 0;
2415 return 0;
2416 }
2417 return 1;
6aa8b732
AK		 2418}
2419
851ba692 2420static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2421{
5fdbf976 2422 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2423 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2424 return 1;
6aa8b732
AK		 2425}
2426
851ba692 2427static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2428{
2429 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2430 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2431 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2432 return 1;
2433}
2434
851ba692 2435static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2436{
6d77dbfc 2437 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2438}
2439
851ba692 2440static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2441{
6d77dbfc 2442 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2443}
2444
cda00082
JR		 2445static int cr0_write_interception(struct vcpu_svm *svm)
2446{
2447 struct kvm_vcpu *vcpu = &svm->vcpu;
2448 int r;
2449
2450 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2451
2452 if (svm->nested.vmexit_rip) {
2453 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2454 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2455 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2456 svm->nested.vmexit_rip = 0;
2457 }
2458
2459 return r == EMULATE_DONE;
2460}
2461
851ba692 2462static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2463{
851ba692
AK		 2464 struct kvm_run *kvm_run = svm->vcpu.run;
2465
0a5fff19
GN		 2466 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2467 /* instruction emulation calls kvm_set_cr8() */
851ba692 2468 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2469 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2470 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2471 return 1;
95ba8273 2472 }
0a5fff19
GN		 2473 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2474 return 1;
1d075434
JR		 2475 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2476 return 0;
2477}
2478
6aa8b732
AK		 2479static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2480{
a2fa3e9f
GH		 2481 struct vcpu_svm *svm = to_svm(vcpu);
2482
6aa8b732 2483 switch (ecx) {
af24a4e4 2484 case MSR_IA32_TSC: {
20824f30 2485 u64 tsc_offset;
6aa8b732 2486
20824f30
JR		 2487 if (is_nested(svm))
2488 tsc_offset = svm->nested.hsave->control.tsc_offset;
2489 else
2490 tsc_offset = svm->vmcb->control.tsc_offset;
2491
2492 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2493 break;
2494 }
8c06585d 2495 case MSR_STAR:
a2fa3e9f 2496 *data = svm->vmcb->save.star;
6aa8b732 2497 break;
0e859cac 2498#ifdef CONFIG_X86_64
6aa8b732 2499 case MSR_LSTAR:
a2fa3e9f 2500 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2501 break;
2502 case MSR_CSTAR:
a2fa3e9f 2503 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2504 break;
2505 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2506 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2507 break;
2508 case MSR_SYSCALL_MASK:
a2fa3e9f 2509 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2510 break;
2511#endif
2512 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2513 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2514 break;
2515 case MSR_IA32_SYSENTER_EIP:
017cb99e 2516 *data = svm->sysenter_eip;
6aa8b732
AK		 2517 break;
2518 case MSR_IA32_SYSENTER_ESP:
017cb99e 2519 *data = svm->sysenter_esp;
6aa8b732 2520 break;
e0231715
JR		 2521 /*
2522 * Nobody will change the following 5 values in the VMCB so we can
2523 * safely return them on rdmsr. They will always be 0 until LBRV is
2524 * implemented.
2525 */
a2938c80
JR		 2526 case MSR_IA32_DEBUGCTLMSR:
2527 *data = svm->vmcb->save.dbgctl;
2528 break;
2529 case MSR_IA32_LASTBRANCHFROMIP:
2530 *data = svm->vmcb->save.br_from;
2531 break;
2532 case MSR_IA32_LASTBRANCHTOIP:
2533 *data = svm->vmcb->save.br_to;
2534 break;
2535 case MSR_IA32_LASTINTFROMIP:
2536 *data = svm->vmcb->save.last_excp_from;
2537 break;
2538 case MSR_IA32_LASTINTTOIP:
2539 *data = svm->vmcb->save.last_excp_to;
2540 break;
b286d5d8 2541 case MSR_VM_HSAVE_PA:
e6aa9abd 2542 *data = svm->nested.hsave_msr;
b286d5d8 2543 break;
eb6f302e 2544 case MSR_VM_CR:
4a810181 2545 *data = svm->nested.vm_cr_msr;
eb6f302e 2546 break;
c8a73f18
AG		 2547 case MSR_IA32_UCODE_REV:
2548 *data = 0x01000065;
2549 break;
6aa8b732 2550 default:
3bab1f5d 2551 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2552 }
2553 return 0;
2554}
2555
851ba692 2556static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2557{
ad312c7c 2558 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2559 u64 data;
2560
59200273
AK		 2561 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2562 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2563 kvm_inject_gp(&svm->vcpu, 0);
59200273 2564 } else {
229456fc 2565 trace_kvm_msr_read(ecx, data);
af9ca2d7 2566
5fdbf976 2567 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2568 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2569 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2570 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2571 }
2572 return 1;
2573}
2574
4a810181
JR		 2575static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2576{
2577 struct vcpu_svm *svm = to_svm(vcpu);
2578 int svm_dis, chg_mask;
2579
2580 if (data & ~SVM_VM_CR_VALID_MASK)
2581 return 1;
2582
2583 chg_mask = SVM_VM_CR_VALID_MASK;
2584
2585 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2586 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2587
2588 svm->nested.vm_cr_msr &= ~chg_mask;
2589 svm->nested.vm_cr_msr |= (data & chg_mask);
2590
2591 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2592
2593 /* check for svm_disable while efer.svme is set */
2594 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2595 return 1;
2596
2597 return 0;
2598}
2599
6aa8b732
AK		 2600static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2601{
a2fa3e9f
GH		 2602 struct vcpu_svm *svm = to_svm(vcpu);
2603
6aa8b732 2604 switch (ecx) {
f4e1b3c8 2605 case MSR_IA32_TSC:
99e3e30a 2606 kvm_write_tsc(vcpu, data);
6aa8b732 2607 break;
8c06585d 2608 case MSR_STAR:
a2fa3e9f 2609 svm->vmcb->save.star = data;
6aa8b732 2610 break;
49b14f24 2611#ifdef CONFIG_X86_64
6aa8b732 2612 case MSR_LSTAR:
a2fa3e9f 2613 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2614 break;
2615 case MSR_CSTAR:
a2fa3e9f 2616 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2617 break;
2618 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2619 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2620 break;
2621 case MSR_SYSCALL_MASK:
a2fa3e9f 2622 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2623 break;
2624#endif
2625 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2626 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2627 break;
2628 case MSR_IA32_SYSENTER_EIP:
017cb99e 2629 svm->sysenter_eip = data;
a2fa3e9f 2630 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2631 break;
2632 case MSR_IA32_SYSENTER_ESP:
017cb99e 2633 svm->sysenter_esp = data;
a2fa3e9f 2634 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2635 break;
a2938c80 2636 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2637 if (!svm_has(SVM_FEATURE_LBRV)) {
2638 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2639 __func__, data);
24e09cbf
JR		 2640 break;
2641 }
2642 if (data & DEBUGCTL_RESERVED_BITS)
2643 return 1;
2644
2645 svm->vmcb->save.dbgctl = data;
2646 if (data & (1ULL<<0))
2647 svm_enable_lbrv(svm);
2648 else
2649 svm_disable_lbrv(svm);
a2938c80 2650 break;
b286d5d8 2651 case MSR_VM_HSAVE_PA:
e6aa9abd 2652 svm->nested.hsave_msr = data;
62b9abaa 2653 break;
3c5d0a44 2654 case MSR_VM_CR:
4a810181 2655 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2656 case MSR_VM_IGNNE:
3c5d0a44
AG		 2657 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2658 break;
6aa8b732 2659 default:
3bab1f5d 2660 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2661 }
2662 return 0;
2663}
2664
851ba692 2665static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2666{
ad312c7c 2667 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2668 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2669 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2670
af9ca2d7 2671
5fdbf976 2672 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2673 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2674 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2675 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2676 } else {
2677 trace_kvm_msr_write(ecx, data);
e756fc62 2678 skip_emulated_instruction(&svm->vcpu);
59200273 2679 }
6aa8b732
AK		 2680 return 1;
2681}
2682
851ba692 2683static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2684{
e756fc62 2685 if (svm->vmcb->control.exit_info_1)
851ba692 2686 return wrmsr_interception(svm);
6aa8b732 2687 else
851ba692 2688 return rdmsr_interception(svm);
6aa8b732
AK		 2689}
2690
851ba692 2691static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2692{
851ba692
AK		 2693 struct kvm_run *kvm_run = svm->vcpu.run;
2694
f0b85051 2695 svm_clear_vintr(svm);
85f455f7 2696 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2697 /*
2698 * If the user space waits to inject interrupts, exit as soon as
2699 * possible
2700 */
8061823a
GN		 2701 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2702 kvm_run->request_interrupt_window &&
2703 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2704 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2705 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2706 return 0;
2707 }
2708
2709 return 1;
2710}
2711
565d0998
ML		 2712static int pause_interception(struct vcpu_svm *svm)
2713{
2714 kvm_vcpu_on_spin(&(svm->vcpu));
2715 return 1;
2716}
2717
851ba692 2718static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2719 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2720 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2721 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2722 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2723 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2724 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2725 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2726 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2727 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2728 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2729 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2730 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2731 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2732 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2733 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2734 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2735 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2736 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2737 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2738 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2739 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2740 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2741 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2742 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2743 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2744 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2745 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2746 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2747 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2748 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2749 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2750 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2751 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2752 [SVM_EXIT_SMI] = nop_on_interception,
2753 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2754 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2755 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2756 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2757 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2758 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2759 [SVM_EXIT_HLT] = halt_interception,
a7052897 2760 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2761 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2762 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2763 [SVM_EXIT_MSR] = msr_interception,
2764 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2765 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2766 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2767 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2768 [SVM_EXIT_VMLOAD] = vmload_interception,
2769 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2770 [SVM_EXIT_STGI] = stgi_interception,
2771 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2772 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2773 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2774 [SVM_EXIT_MONITOR] = invalid_op_interception,
2775 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2776 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2777};
2778
3f10c846
JR		 2779void dump_vmcb(struct kvm_vcpu *vcpu)
2780{
2781 struct vcpu_svm *svm = to_svm(vcpu);
2782 struct vmcb_control_area *control = &svm->vmcb->control;
2783 struct vmcb_save_area *save = &svm->vmcb->save;
2784
2785 pr_err("VMCB Control Area:\n");
2786 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2787 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2788 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2789 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2790 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2791 pr_err("intercepts: %016llx\n", control->intercept);
2792 pr_err("pause filter count: %d\n", control->pause_filter_count);
2793 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2794 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2795 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2796 pr_err("asid: %d\n", control->asid);
2797 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2798 pr_err("int_ctl: %08x\n", control->int_ctl);
2799 pr_err("int_vector: %08x\n", control->int_vector);
2800 pr_err("int_state: %08x\n", control->int_state);
2801 pr_err("exit_code: %08x\n", control->exit_code);
2802 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2803 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2804 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2805 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2806 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2807 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2808 pr_err("event_inj: %08x\n", control->event_inj);
2809 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2810 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2811 pr_err("next_rip: %016llx\n", control->next_rip);
2812 pr_err("VMCB State Save Area:\n");
2813 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2814 save->es.selector, save->es.attrib,
2815 save->es.limit, save->es.base);
2816 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2817 save->cs.selector, save->cs.attrib,
2818 save->cs.limit, save->cs.base);
2819 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2820 save->ss.selector, save->ss.attrib,
2821 save->ss.limit, save->ss.base);
2822 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2823 save->ds.selector, save->ds.attrib,
2824 save->ds.limit, save->ds.base);
2825 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2826 save->fs.selector, save->fs.attrib,
2827 save->fs.limit, save->fs.base);
2828 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2829 save->gs.selector, save->gs.attrib,
2830 save->gs.limit, save->gs.base);
2831 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2832 save->gdtr.selector, save->gdtr.attrib,
2833 save->gdtr.limit, save->gdtr.base);
2834 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2835 save->ldtr.selector, save->ldtr.attrib,
2836 save->ldtr.limit, save->ldtr.base);
2837 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2838 save->idtr.selector, save->idtr.attrib,
2839 save->idtr.limit, save->idtr.base);
2840 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2841 save->tr.selector, save->tr.attrib,
2842 save->tr.limit, save->tr.base);
2843 pr_err("cpl: %d efer: %016llx\n",
2844 save->cpl, save->efer);
2845 pr_err("cr0: %016llx cr2: %016llx\n",
2846 save->cr0, save->cr2);
2847 pr_err("cr3: %016llx cr4: %016llx\n",
2848 save->cr3, save->cr4);
2849 pr_err("dr6: %016llx dr7: %016llx\n",
2850 save->dr6, save->dr7);
2851 pr_err("rip: %016llx rflags: %016llx\n",
2852 save->rip, save->rflags);
2853 pr_err("rsp: %016llx rax: %016llx\n",
2854 save->rsp, save->rax);
2855 pr_err("star: %016llx lstar: %016llx\n",
2856 save->star, save->lstar);
2857 pr_err("cstar: %016llx sfmask: %016llx\n",
2858 save->cstar, save->sfmask);
2859 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2860 save->kernel_gs_base, save->sysenter_cs);
2861 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2862 save->sysenter_esp, save->sysenter_eip);
2863 pr_err("gpat: %016llx dbgctl: %016llx\n",
2864 save->g_pat, save->dbgctl);
2865 pr_err("br_from: %016llx br_to: %016llx\n",
2866 save->br_from, save->br_to);
2867 pr_err("excp_from: %016llx excp_to: %016llx\n",
2868 save->last_excp_from, save->last_excp_to);
2869
2870}
2871
851ba692 2872static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2873{
04d2cc77 2874 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2875 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2876 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2877
5bfd8b54 2878 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2879
2be4fc7a
JR		 2880 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2881 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2882 if (npt_enabled)
2883 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2884
cd3ff653
JR		 2885 if (unlikely(svm->nested.exit_required)) {
2886 nested_svm_vmexit(svm);
2887 svm->nested.exit_required = false;
2888
2889 return 1;
2890 }
2891
cf74a78b 2892 if (is_nested(svm)) {
410e4d57
JR		 2893 int vmexit;
2894
d8cabddf
JR		 2895 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2896 svm->vmcb->control.exit_info_1,
2897 svm->vmcb->control.exit_info_2,
2898 svm->vmcb->control.exit_int_info,
2899 svm->vmcb->control.exit_int_info_err);
2900
410e4d57
JR		 2901 vmexit = nested_svm_exit_special(svm);
2902
2903 if (vmexit == NESTED_EXIT_CONTINUE)
2904 vmexit = nested_svm_exit_handled(svm);
2905
2906 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2907 return 1;
cf74a78b
AG		 2908 }
2909
a5c3832d
JR		 2910 svm_complete_interrupts(svm);
2911
04d2cc77
AK		 2912 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2913 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2914 kvm_run->fail_entry.hardware_entry_failure_reason
2915 = svm->vmcb->control.exit_code;
3f10c846
JR		 2916 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2917 dump_vmcb(vcpu);
04d2cc77
AK		 2918 return 0;
2919 }
2920
a2fa3e9f 2921 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2922 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2923 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2924 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2925 "exit_code 0x%x\n",
b8688d51 2926 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2927 exit_code);
2928
9d8f549d 2929 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2930 || !svm_exit_handlers[exit_code]) {
6aa8b732 2931 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2932 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2933 return 0;
2934 }
2935
851ba692 2936 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2937}
2938
2939static void reload_tss(struct kvm_vcpu *vcpu)
2940{
2941 int cpu = raw_smp_processor_id();
2942
0fe1e009
TH		 2943 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2944 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2945 load_TR_desc();
2946}
2947
e756fc62 2948static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2949{
2950 int cpu = raw_smp_processor_id();
2951
0fe1e009 2952 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2953
a2fa3e9f 2954 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2955 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2956 if (svm->asid_generation != sd->asid_generation)
2957 new_asid(svm, sd);
6aa8b732
AK		 2958}
2959
95ba8273
GN		 2960static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2961{
2962 struct vcpu_svm *svm = to_svm(vcpu);
2963
2964 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2965 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2966 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2967 ++vcpu->stat.nmi_injections;
2968}
6aa8b732 2969
85f455f7 2970static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2971{
2972 struct vmcb_control_area *control;
2973
e756fc62 2974 control = &svm->vmcb->control;
85f455f7 2975 control->int_vector = irq;
6aa8b732
AK		 2976 control->int_ctl &= ~V_INTR_PRIO_MASK;
2977 control->int_ctl |= V_IRQ_MASK |
2978 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2979}
2980
66fd3f7f 2981static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2982{
2983 struct vcpu_svm *svm = to_svm(vcpu);
2984
2af9194d 2985 BUG_ON(!(gif_set(svm)));
cf74a78b 2986
9fb2d2b4
GN		 2987 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2988 ++vcpu->stat.irq_injections;
2989
219b65dc
AG		 2990 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2991 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2992}
2993
95ba8273 2994static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2995{
2996 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2997
88ab24ad
JR		 2998 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2999 return;
3000
95ba8273 3001 if (irr == -1)
aaacfc9a
JR		 3002 return;
3003
95ba8273
GN		 3004 if (tpr >= irr)
3005 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3006}
aaacfc9a 3007
95ba8273
GN		 3008static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3009{
3010 struct vcpu_svm *svm = to_svm(vcpu);
3011 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3012 int ret;
3013 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3014 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3015 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3016
3017 return ret;
aaacfc9a
JR		 3018}
3019
3cfc3092
JK		 3020static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3021{
3022 struct vcpu_svm *svm = to_svm(vcpu);
3023
3024 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3025}
3026
3027static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3028{
3029 struct vcpu_svm *svm = to_svm(vcpu);
3030
3031 if (masked) {
3032 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3033 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3034 } else {
3035 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3036 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3037 }
3038}
3039
78646121
GN		 3040static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3041{
3042 struct vcpu_svm *svm = to_svm(vcpu);
3043 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3044 int ret;
3045
3046 if (!gif_set(svm) ||
3047 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3048 return 0;
3049
3050 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3051
3052 if (is_nested(svm))
3053 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3054
3055 return ret;
78646121
GN		 3056}
3057
9222be18 3058static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3059{
219b65dc 3060 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3061
e0231715
JR		 3062 /*
3063 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3064 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3065 * get that intercept, this function will be called again though and
3066 * we'll get the vintr intercept.
3067 */
8fe54654 3068 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3069 svm_set_vintr(svm);
3070 svm_inject_irq(svm, 0x0);
3071 }
85f455f7
ED		 3072}
3073
95ba8273 3074static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3075{
04d2cc77 3076 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3077
44c11430
GN		 3078 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3079 == HF_NMI_MASK)
3080 return; /* IRET will cause a vm exit */
3081
e0231715
JR		 3082 /*
3083 * Something prevents NMI from been injected. Single step over possible
3084 * problem (IRET or exception injection or interrupt shadow)
3085 */
6be7d306 3086 svm->nmi_singlestep = true;
44c11430
GN		 3087 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3088 update_db_intercept(vcpu);
c1150d8c
DL		 3089}
3090
cbc94022
IE		 3091static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3092{
3093 return 0;
3094}
3095
d9e368d6
AK		 3096static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3097{
3098 force_new_asid(vcpu);
3099}
3100
04d2cc77
AK		 3101static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3102{
3103}
3104
d7bf8221
JR		 3105static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3106{
3107 struct vcpu_svm *svm = to_svm(vcpu);
3108
88ab24ad
JR		 3109 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3110 return;
3111
d7bf8221
JR		 3112 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3113 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3114 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3115 }
3116}
3117
649d6864
JR		 3118static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3119{
3120 struct vcpu_svm *svm = to_svm(vcpu);
3121 u64 cr8;
3122
88ab24ad
JR		 3123 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3124 return;
3125
649d6864
JR		 3126 cr8 = kvm_get_cr8(vcpu);
3127 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3128 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3129}
3130
9222be18
GN		 3131static void svm_complete_interrupts(struct vcpu_svm *svm)
3132{
3133 u8 vector;
3134 int type;
3135 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3136 unsigned int3_injected = svm->int3_injected;
3137
3138 svm->int3_injected = 0;
9222be18 3139
44c11430
GN		 3140 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3141 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3142
9222be18
GN		 3143 svm->vcpu.arch.nmi_injected = false;
3144 kvm_clear_exception_queue(&svm->vcpu);
3145 kvm_clear_interrupt_queue(&svm->vcpu);
3146
3147 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3148 return;
3149
3150 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3151 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3152
3153 switch (type) {
3154 case SVM_EXITINTINFO_TYPE_NMI:
3155 svm->vcpu.arch.nmi_injected = true;
3156 break;
3157 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3158 /*
3159 * In case of software exceptions, do not reinject the vector,
3160 * but re-execute the instruction instead. Rewind RIP first
3161 * if we emulated INT3 before.
3162 */
3163 if (kvm_exception_is_soft(vector)) {
3164 if (vector == BP_VECTOR && int3_injected &&
3165 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3166 kvm_rip_write(&svm->vcpu,
3167 kvm_rip_read(&svm->vcpu) -
3168 int3_injected);
9222be18 3169 break;
66b7138f 3170 }
9222be18
GN		 3171 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3172 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3173 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3174
3175 } else
ce7ddec4 3176 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3177 break;
3178 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3179 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3180 break;
3181 default:
3182 break;
3183 }
3184}
3185
80e31d4f
AK		 3186#ifdef CONFIG_X86_64
3187#define R "r"
3188#else
3189#define R "e"
3190#endif
3191
851ba692 3192static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3193{
a2fa3e9f 3194 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3195 u16 fs_selector;
3196 u16 gs_selector;
3197 u16 ldt_selector;
d9e368d6 3198
2041a06a
JR		 3199 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3200 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3201 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3202
cd3ff653
JR		 3203 /*
3204 * A vmexit emulation is required before the vcpu can be executed
3205 * again.
3206 */
3207 if (unlikely(svm->nested.exit_required))
3208 return;
3209
e756fc62 3210 pre_svm_run(svm);
6aa8b732 3211
649d6864
JR		 3212 sync_lapic_to_cr8(vcpu);
3213
6aa8b732 3214 save_host_msrs(vcpu);
9581d442
AK		 3215 savesegment(fs, fs_selector);
3216 savesegment(gs, gs_selector);
d6e88aec 3217 ldt_selector = kvm_read_ldt();
cda0ffdd 3218 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3219
04d2cc77
AK		 3220 clgi();
3221
3222 local_irq_enable();
36241b8c 3223
6aa8b732 3224 asm volatile (
80e31d4f
AK		 3225 "push %%"R"bp; \n\t"
3226 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3227 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3228 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3229 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3230 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3231 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3232#ifdef CONFIG_X86_64
fb3f0f51
RR		 3233 "mov %c[r8](%[svm]), %%r8 \n\t"
3234 "mov %c[r9](%[svm]), %%r9 \n\t"
3235 "mov %c[r10](%[svm]), %%r10 \n\t"
3236 "mov %c[r11](%[svm]), %%r11 \n\t"
3237 "mov %c[r12](%[svm]), %%r12 \n\t"
3238 "mov %c[r13](%[svm]), %%r13 \n\t"
3239 "mov %c[r14](%[svm]), %%r14 \n\t"
3240 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3241#endif
3242
6aa8b732 3243 /* Enter guest mode */
80e31d4f
AK		 3244 "push %%"R"ax \n\t"
3245 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3246 __ex(SVM_VMLOAD) "\n\t"
3247 __ex(SVM_VMRUN) "\n\t"
3248 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3249 "pop %%"R"ax \n\t"
6aa8b732
AK		 3250
3251 /* Save guest registers, load host registers */
80e31d4f
AK		 3252 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3253 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3254 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3255 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3256 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3257 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3258#ifdef CONFIG_X86_64
fb3f0f51
RR		 3259 "mov %%r8, %c[r8](%[svm]) \n\t"
3260 "mov %%r9, %c[r9](%[svm]) \n\t"
3261 "mov %%r10, %c[r10](%[svm]) \n\t"
3262 "mov %%r11, %c[r11](%[svm]) \n\t"
3263 "mov %%r12, %c[r12](%[svm]) \n\t"
3264 "mov %%r13, %c[r13](%[svm]) \n\t"
3265 "mov %%r14, %c[r14](%[svm]) \n\t"
3266 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3267#endif
80e31d4f 3268 "pop %%"R"bp"
6aa8b732 3269 :
fb3f0f51 3270 : [svm]"a"(svm),
6aa8b732 3271 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3272 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3273 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3274 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3275 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3276 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3277 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3278#ifdef CONFIG_X86_64
ad312c7c
ZX		 3279 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3280 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3281 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3282 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3283 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3284 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3285 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3286 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3287#endif
54a08c04 3288 : "cc", "memory"
80e31d4f 3289 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3290#ifdef CONFIG_X86_64
54a08c04
LV		 3291 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3292#endif
3293 );
6aa8b732 3294
ad312c7c 3295 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3296 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3297 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3298 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3299
6aa8b732 3300 load_host_msrs(vcpu);
9581d442
AK		 3301 loadsegment(fs, fs_selector);
3302#ifdef CONFIG_X86_64
3303 load_gs_index(gs_selector);
3304 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3305#else
3306 loadsegment(gs, gs_selector);
3307#endif
3308 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3309
3310 reload_tss(vcpu);
3311
56ba47dd
AK		 3312 local_irq_disable();
3313
3314 stgi();
3315
d7bf8221
JR		 3316 sync_cr8_to_lapic(vcpu);
3317
a2fa3e9f 3318 svm->next_rip = 0;
9222be18 3319
6de4f3ad
AK		 3320 if (npt_enabled) {
3321 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3322 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3323 }
fe5913e4
JR		 3324
3325 /*
3326 * We need to handle MC intercepts here before the vcpu has a chance to
3327 * change the physical cpu
3328 */
3329 if (unlikely(svm->vmcb->control.exit_code ==
3330 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3331 svm_handle_mce(svm);
6aa8b732
AK		 3332}
3333
80e31d4f
AK		 3334#undef R
3335
6aa8b732
AK		 3336static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3337{
a2fa3e9f
GH		 3338 struct vcpu_svm *svm = to_svm(vcpu);
3339
3340 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3341 force_new_asid(vcpu);
3342}
3343
1c97f0a0
JR		 3344static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3345{
3346 struct vcpu_svm *svm = to_svm(vcpu);
3347
3348 svm->vmcb->control.nested_cr3 = root;
3349
3350 /* Also sync guest cr3 here in case we live migrate */
3351 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3352
3353 force_new_asid(vcpu);
3354}
3355
6aa8b732
AK		 3356static int is_disabled(void)
3357{
6031a61c
JR		 3358 u64 vm_cr;
3359
3360 rdmsrl(MSR_VM_CR, vm_cr);
3361 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3362 return 1;
3363
6aa8b732
AK		 3364 return 0;
3365}
3366
102d8325
IM		 3367static void
3368svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3369{
3370 /*
3371 * Patch in the VMMCALL instruction:
3372 */
3373 hypercall[0] = 0x0f;
3374 hypercall[1] = 0x01;
3375 hypercall[2] = 0xd9;
102d8325
IM		 3376}
3377
002c7f7c
YS		 3378static void svm_check_processor_compat(void *rtn)
3379{
3380 *(int *)rtn = 0;
3381}
3382
774ead3a
AK		 3383static bool svm_cpu_has_accelerated_tpr(void)
3384{
3385 return false;
3386}
3387
67253af5
SY		 3388static int get_npt_level(void)
3389{
3390#ifdef CONFIG_X86_64
3391 return PT64_ROOT_LEVEL;
3392#else
3393 return PT32E_ROOT_LEVEL;
3394#endif
3395}
3396
4b12f0de 3397static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3398{
3399 return 0;
3400}
3401
0e851880
SY		 3402static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3403{
3404}
3405
d4330ef2
JR		 3406static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3407{
c2c63a49
JR		 3408 switch (func) {
3409 case 0x8000000A:
3410 entry->eax = 1; /* SVM revision 1 */
3411 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3412 ASID emulation to nested SVM */
3413 entry->ecx = 0; /* Reserved */
7a190667
JR		 3414 entry->edx = 0; /* Per default do not support any
3415 additional features */
3416
3417 /* Support next_rip if host supports it */
3418 if (svm_has(SVM_FEATURE_NRIP))
3419 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49
JR		 3420
3421 break;
3422 }
d4330ef2
JR		 3423}
3424
229456fc 3425static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3426 { SVM_EXIT_READ_CR0, "read_cr0" },
3427 { SVM_EXIT_READ_CR3, "read_cr3" },
3428 { SVM_EXIT_READ_CR4, "read_cr4" },
3429 { SVM_EXIT_READ_CR8, "read_cr8" },
3430 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3431 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3432 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3433 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3434 { SVM_EXIT_READ_DR0, "read_dr0" },
3435 { SVM_EXIT_READ_DR1, "read_dr1" },
3436 { SVM_EXIT_READ_DR2, "read_dr2" },
3437 { SVM_EXIT_READ_DR3, "read_dr3" },
3438 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3439 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3440 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3441 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3442 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3443 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3444 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3445 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3446 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3447 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3448 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3449 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3450 { SVM_EXIT_INTR, "interrupt" },
3451 { SVM_EXIT_NMI, "nmi" },
3452 { SVM_EXIT_SMI, "smi" },
3453 { SVM_EXIT_INIT, "init" },
3454 { SVM_EXIT_VINTR, "vintr" },
3455 { SVM_EXIT_CPUID, "cpuid" },
3456 { SVM_EXIT_INVD, "invd" },
3457 { SVM_EXIT_HLT, "hlt" },
3458 { SVM_EXIT_INVLPG, "invlpg" },
3459 { SVM_EXIT_INVLPGA, "invlpga" },
3460 { SVM_EXIT_IOIO, "io" },
3461 { SVM_EXIT_MSR, "msr" },
3462 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3463 { SVM_EXIT_SHUTDOWN, "shutdown" },
3464 { SVM_EXIT_VMRUN, "vmrun" },
3465 { SVM_EXIT_VMMCALL, "hypercall" },
3466 { SVM_EXIT_VMLOAD, "vmload" },
3467 { SVM_EXIT_VMSAVE, "vmsave" },
3468 { SVM_EXIT_STGI, "stgi" },
3469 { SVM_EXIT_CLGI, "clgi" },
3470 { SVM_EXIT_SKINIT, "skinit" },
3471 { SVM_EXIT_WBINVD, "wbinvd" },
3472 { SVM_EXIT_MONITOR, "monitor" },
3473 { SVM_EXIT_MWAIT, "mwait" },
3474 { SVM_EXIT_NPF, "npf" },
3475 { -1, NULL }
3476};
3477
17cc3935 3478static int svm_get_lpage_level(void)
344f414f 3479{
17cc3935 3480 return PT_PDPE_LEVEL;
344f414f
JR		 3481}
3482
4e47c7a6
SY		 3483static bool svm_rdtscp_supported(void)
3484{
3485 return false;
3486}
3487
f5f48ee1
SY		 3488static bool svm_has_wbinvd_exit(void)
3489{
3490 return true;
3491}
3492
02daab21
AK		 3493static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3494{
3495 struct vcpu_svm *svm = to_svm(vcpu);
3496
02daab21 3497 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3498 if (is_nested(svm))
3499 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3500 update_cr0_intercept(svm);
02daab21
AK		 3501}
3502
cbdd1bea 3503static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3504 .cpu_has_kvm_support = has_svm,
3505 .disabled_by_bios = is_disabled,
3506 .hardware_setup = svm_hardware_setup,
3507 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3508 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3509 .hardware_enable = svm_hardware_enable,
3510 .hardware_disable = svm_hardware_disable,
774ead3a 3511 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3512
3513 .vcpu_create = svm_create_vcpu,
3514 .vcpu_free = svm_free_vcpu,
04d2cc77 3515 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3516
04d2cc77 3517 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3518 .vcpu_load = svm_vcpu_load,
3519 .vcpu_put = svm_vcpu_put,
3520
3521 .set_guest_debug = svm_guest_debug,
3522 .get_msr = svm_get_msr,
3523 .set_msr = svm_set_msr,
3524 .get_segment_base = svm_get_segment_base,
3525 .get_segment = svm_get_segment,
3526 .set_segment = svm_set_segment,
2e4d2653 3527 .get_cpl = svm_get_cpl,
1747fb71 3528 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3529 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3530 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3531 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3532 .set_cr3 = svm_set_cr3,
3533 .set_cr4 = svm_set_cr4,
3534 .set_efer = svm_set_efer,
3535 .get_idt = svm_get_idt,
3536 .set_idt = svm_set_idt,
3537 .get_gdt = svm_get_gdt,
3538 .set_gdt = svm_set_gdt,
020df079 3539 .set_dr7 = svm_set_dr7,
6de4f3ad 3540 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3541 .get_rflags = svm_get_rflags,
3542 .set_rflags = svm_set_rflags,
6b52d186 3543 .fpu_activate = svm_fpu_activate,
02daab21 3544 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3545
6aa8b732 3546 .tlb_flush = svm_flush_tlb,
6aa8b732 3547
6aa8b732 3548 .run = svm_vcpu_run,
04d2cc77 3549 .handle_exit = handle_exit,
6aa8b732 3550 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3551 .set_interrupt_shadow = svm_set_interrupt_shadow,
3552 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3553 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3554 .set_irq = svm_set_irq,
95ba8273 3555 .set_nmi = svm_inject_nmi,
298101da 3556 .queue_exception = svm_queue_exception,
78646121 3557 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3558 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3559 .get_nmi_mask = svm_get_nmi_mask,
3560 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3561 .enable_nmi_window = enable_nmi_window,
3562 .enable_irq_window = enable_irq_window,
3563 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3564
3565 .set_tss_addr = svm_set_tss_addr,
67253af5 3566 .get_tdp_level = get_npt_level,
4b12f0de 3567 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3568
3569 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3570 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3571
3572 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3573
3574 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3575
3576 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3577
3578 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3579
3580 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3581 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3582
3583 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3584};
3585
3586static int __init svm_init(void)
3587{
cb498ea2 3588 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3589 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3590}
3591
3592static void __exit svm_exit(void)
3593{
cb498ea2 3594 kvm_exit();
6aa8b732
AK		 3595}
3596
3597module_init(svm_init)
3598module_exit(svm_exit)
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