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KVM: SVM: move nested svm state into seperate struct
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
24e09cbf
JR		 50#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
c0725420
AG		 52/* Turn on to get debugging output*/
53/* #define NESTED_DEBUG */
54
55#ifdef NESTED_DEBUG
56#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57#else
58#define nsvm_printk(fmt, args...) do {} while(0)
59#endif
60
6c8166a7
AK		 61static const u32 host_save_user_msrs[] = {
62#ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65#endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67};
68
69#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71struct kvm_vcpu;
72
e6aa9abd
JR		 73struct nested_state {
74 struct vmcb *hsave;
75 u64 hsave_msr;
76 u64 vmcb;
77
78 /* These are the merged vectors */
79 u32 *msrpm;
80
81 /* gpa pointers to the real vectors */
82 u64 vmcb_msrpm;
83};
84
6c8166a7
AK		 85struct vcpu_svm {
86 struct kvm_vcpu vcpu;
87 struct vmcb *vmcb;
88 unsigned long vmcb_pa;
89 struct svm_cpu_data *svm_data;
90 uint64_t asid_generation;
91 uint64_t sysenter_esp;
92 uint64_t sysenter_eip;
93
94 u64 next_rip;
95
96 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
97 u64 host_gs_base;
6c8166a7
AK		 98
99 u32 *msrpm;
6c8166a7 100
e6aa9abd 101 struct nested_state nested;
6c8166a7
AK		 102};
103
709ddebf
JR		 104/* enable NPT for AMD64 and X86 with PAE */
105#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
106static bool npt_enabled = true;
107#else
e3da3acd 108static bool npt_enabled = false;
709ddebf 109#endif
6c7dac72
JR		 110static int npt = 1;
111
112module_param(npt, int, S_IRUGO);
e3da3acd 113
236de055
AG		 114static int nested = 0;
115module_param(nested, int, S_IRUGO);
116
44874f84 117static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 118static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 119
cf74a78b
AG		 120static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
121static int nested_svm_vmexit(struct vcpu_svm *svm);
122static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
123 void *arg2, void *opaque);
124static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
125 bool has_error_code, u32 error_code);
126
a2fa3e9f
GH		 127static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
128{
fb3f0f51 129 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 130}
131
3d6368ef
AG		 132static inline bool is_nested(struct vcpu_svm *svm)
133{
e6aa9abd 134 return svm->nested.vmcb;
3d6368ef
AG		 135}
136
2af9194d
JR		 137static inline void enable_gif(struct vcpu_svm *svm)
138{
139 svm->vcpu.arch.hflags |= HF_GIF_MASK;
140}
141
142static inline void disable_gif(struct vcpu_svm *svm)
143{
144 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
145}
146
147static inline bool gif_set(struct vcpu_svm *svm)
148{
149 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
150}
151
4866d5e3 152static unsigned long iopm_base;
6aa8b732
AK		 153
154struct kvm_ldttss_desc {
155 u16 limit0;
156 u16 base0;
157 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
158 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
159 u32 base3;
160 u32 zero1;
161} __attribute__((packed));
162
163struct svm_cpu_data {
164 int cpu;
165
5008fdf5
AK		 166 u64 asid_generation;
167 u32 max_asid;
168 u32 next_asid;
6aa8b732
AK		 169 struct kvm_ldttss_desc *tss_desc;
170
171 struct page *save_area;
172};
173
174static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 175static uint32_t svm_features;
6aa8b732
AK		 176
177struct svm_init_data {
178 int cpu;
179 int r;
180};
181
182static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
183
9d8f549d 184#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 185#define MSRS_RANGE_SIZE 2048
186#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
187
188#define MAX_INST_SIZE 15
189
80b7706e
JR		 190static inline u32 svm_has(u32 feat)
191{
192 return svm_features & feat;
193}
194
6aa8b732
AK		 195static inline void clgi(void)
196{
4ecac3fd 197 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 198}
199
200static inline void stgi(void)
201{
4ecac3fd 202 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 203}
204
205static inline void invlpga(unsigned long addr, u32 asid)
206{
4ecac3fd 207 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 208}
209
6aa8b732
AK		 210static inline void force_new_asid(struct kvm_vcpu *vcpu)
211{
a2fa3e9f 212 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 213}
214
215static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
216{
217 force_new_asid(vcpu);
218}
219
220static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
221{
709ddebf 222 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 223 efer &= ~EFER_LME;
6aa8b732 224
9962d032 225 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 226 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 227}
228
298101da
AK		 229static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
230 bool has_error_code, u32 error_code)
231{
232 struct vcpu_svm *svm = to_svm(vcpu);
233
cf74a78b
AG		 234 /* If we are within a nested VM we'd better #VMEXIT and let the
235 guest handle the exception */
236 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
237 return;
238
298101da
AK		 239 svm->vmcb->control.event_inj = nr
240 | SVM_EVTINJ_VALID
241 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
242 | SVM_EVTINJ_TYPE_EXEPT;
243 svm->vmcb->control.event_inj_err = error_code;
244}
245
6aa8b732
AK		 246static int is_external_interrupt(u32 info)
247{
248 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
249 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
250}
251
2809f5d2
GC		 252static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
253{
254 struct vcpu_svm *svm = to_svm(vcpu);
255 u32 ret = 0;
256
257 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
258 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
259 return ret & mask;
260}
261
262static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
263{
264 struct vcpu_svm *svm = to_svm(vcpu);
265
266 if (mask == 0)
267 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
268 else
269 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
270
271}
272
6aa8b732
AK		 273static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
274{
a2fa3e9f
GH		 275 struct vcpu_svm *svm = to_svm(vcpu);
276
277 if (!svm->next_rip) {
f629cf84
GN		 278 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
279 EMULATE_DONE)
280 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 281 return;
282 }
5fdbf976
MT		 283 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
284 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
285 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 286
5fdbf976 287 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 288 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 289}
290
291static int has_svm(void)
292{
63d1142f 293 const char *msg;
6aa8b732 294
63d1142f 295 if (!cpu_has_svm(&msg)) {
ff81ff10 296 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 297 return 0;
298 }
299
6aa8b732
AK		 300 return 1;
301}
302
303static void svm_hardware_disable(void *garbage)
304{
2c8dceeb 305 cpu_svm_disable();
6aa8b732
AK		 306}
307
308static void svm_hardware_enable(void *garbage)
309{
310
311 struct svm_cpu_data *svm_data;
312 uint64_t efer;
b792c344 313 struct descriptor_table gdt_descr;
6aa8b732
AK		 314 struct desc_struct *gdt;
315 int me = raw_smp_processor_id();
316
317 if (!has_svm()) {
318 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
319 return;
320 }
321 svm_data = per_cpu(svm_data, me);
322
323 if (!svm_data) {
324 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
325 me);
326 return;
327 }
328
329 svm_data->asid_generation = 1;
330 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
331 svm_data->next_asid = svm_data->max_asid + 1;
332
b792c344
AM		 333 kvm_get_gdt(&gdt_descr);
334 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 335 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
336
337 rdmsrl(MSR_EFER, efer);
9962d032 338 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 339
340 wrmsrl(MSR_VM_HSAVE_PA,
341 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
342}
343
0da1db75
JR		 344static void svm_cpu_uninit(int cpu)
345{
346 struct svm_cpu_data *svm_data
347 = per_cpu(svm_data, raw_smp_processor_id());
348
349 if (!svm_data)
350 return;
351
352 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
353 __free_page(svm_data->save_area);
354 kfree(svm_data);
355}
356
6aa8b732
AK		 357static int svm_cpu_init(int cpu)
358{
359 struct svm_cpu_data *svm_data;
360 int r;
361
362 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
363 if (!svm_data)
364 return -ENOMEM;
365 svm_data->cpu = cpu;
366 svm_data->save_area = alloc_page(GFP_KERNEL);
367 r = -ENOMEM;
368 if (!svm_data->save_area)
369 goto err_1;
370
371 per_cpu(svm_data, cpu) = svm_data;
372
373 return 0;
374
375err_1:
376 kfree(svm_data);
377 return r;
378
379}
380
bfc733a7
RR		 381static void set_msr_interception(u32 *msrpm, unsigned msr,
382 int read, int write)
6aa8b732
AK		 383{
384 int i;
385
386 for (i = 0; i < NUM_MSR_MAPS; i++) {
387 if (msr >= msrpm_ranges[i] &&
388 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
389 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
390 msrpm_ranges[i]) * 2;
391
392 u32 *base = msrpm + (msr_offset / 32);
393 u32 msr_shift = msr_offset % 32;
394 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
395 *base = (*base & ~(0x3 << msr_shift)) |
396 (mask << msr_shift);
bfc733a7 397 return;
6aa8b732
AK		 398 }
399 }
bfc733a7 400 BUG();
6aa8b732
AK		 401}
402
f65c229c
JR		 403static void svm_vcpu_init_msrpm(u32 *msrpm)
404{
405 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
406
407#ifdef CONFIG_X86_64
408 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
409 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
410 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
411 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
412 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
413 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
414#endif
415 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
416 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 417}
418
24e09cbf
JR		 419static void svm_enable_lbrv(struct vcpu_svm *svm)
420{
421 u32 *msrpm = svm->msrpm;
422
423 svm->vmcb->control.lbr_ctl = 1;
424 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
425 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
426 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
427 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
428}
429
430static void svm_disable_lbrv(struct vcpu_svm *svm)
431{
432 u32 *msrpm = svm->msrpm;
433
434 svm->vmcb->control.lbr_ctl = 0;
435 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
437 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
439}
440
6aa8b732
AK		 441static __init int svm_hardware_setup(void)
442{
443 int cpu;
444 struct page *iopm_pages;
f65c229c 445 void *iopm_va;
6aa8b732
AK		 446 int r;
447
6aa8b732
AK		 448 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
449
450 if (!iopm_pages)
451 return -ENOMEM;
c8681339
AL		 452
453 iopm_va = page_address(iopm_pages);
454 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 455 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
456
50a37eb4
JR		 457 if (boot_cpu_has(X86_FEATURE_NX))
458 kvm_enable_efer_bits(EFER_NX);
459
1b2fd70c
AG		 460 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
461 kvm_enable_efer_bits(EFER_FFXSR);
462
236de055
AG		 463 if (nested) {
464 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
465 kvm_enable_efer_bits(EFER_SVME);
466 }
467
6aa8b732
AK		 468 for_each_online_cpu(cpu) {
469 r = svm_cpu_init(cpu);
470 if (r)
f65c229c 471 goto err;
6aa8b732 472 }
33bd6a0b
JR		 473
474 svm_features = cpuid_edx(SVM_CPUID_FUNC);
475
e3da3acd
JR		 476 if (!svm_has(SVM_FEATURE_NPT))
477 npt_enabled = false;
478
6c7dac72
JR		 479 if (npt_enabled && !npt) {
480 printk(KERN_INFO "kvm: Nested Paging disabled\n");
481 npt_enabled = false;
482 }
483
18552672 484 if (npt_enabled) {
e3da3acd 485 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 486 kvm_enable_tdp();
5f4cb662
JR		 487 } else
488 kvm_disable_tdp();
e3da3acd 489
6aa8b732
AK		 490 return 0;
491
f65c229c 492err:
6aa8b732
AK		 493 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
494 iopm_base = 0;
495 return r;
496}
497
498static __exit void svm_hardware_unsetup(void)
499{
0da1db75
JR		 500 int cpu;
501
502 for_each_online_cpu(cpu)
503 svm_cpu_uninit(cpu);
504
6aa8b732 505 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 506 iopm_base = 0;
6aa8b732
AK		 507}
508
509static void init_seg(struct vmcb_seg *seg)
510{
511 seg->selector = 0;
512 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
513 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
514 seg->limit = 0xffff;
515 seg->base = 0;
516}
517
518static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
519{
520 seg->selector = 0;
521 seg->attrib = SVM_SELECTOR_P_MASK | type;
522 seg->limit = 0xffff;
523 seg->base = 0;
524}
525
e6101a96 526static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 527{
e6101a96
JR		 528 struct vmcb_control_area *control = &svm->vmcb->control;
529 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 530
531 control->intercept_cr_read = INTERCEPT_CR0_MASK |
532 INTERCEPT_CR3_MASK |
649d6864 533 INTERCEPT_CR4_MASK;
6aa8b732
AK		 534
535 control->intercept_cr_write = INTERCEPT_CR0_MASK |
536 INTERCEPT_CR3_MASK |
80a8119c
AK		 537 INTERCEPT_CR4_MASK |
538 INTERCEPT_CR8_MASK;
6aa8b732
AK		 539
540 control->intercept_dr_read = INTERCEPT_DR0_MASK |
541 INTERCEPT_DR1_MASK |
542 INTERCEPT_DR2_MASK |
543 INTERCEPT_DR3_MASK;
544
545 control->intercept_dr_write = INTERCEPT_DR0_MASK |
546 INTERCEPT_DR1_MASK |
547 INTERCEPT_DR2_MASK |
548 INTERCEPT_DR3_MASK |
549 INTERCEPT_DR5_MASK |
550 INTERCEPT_DR7_MASK;
551
7aa81cc0 552 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 553 (1 << UD_VECTOR) |
554 (1 << MC_VECTOR);
6aa8b732
AK		 555
556
557 control->intercept = (1ULL << INTERCEPT_INTR) |
558 (1ULL << INTERCEPT_NMI) |
0152527b 559 (1ULL << INTERCEPT_SMI) |
6aa8b732 560 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 561 (1ULL << INTERCEPT_INVD) |
6aa8b732 562 (1ULL << INTERCEPT_HLT) |
a7052897 563 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 564 (1ULL << INTERCEPT_INVLPGA) |
565 (1ULL << INTERCEPT_IOIO_PROT) |
566 (1ULL << INTERCEPT_MSR_PROT) |
567 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 568 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 569 (1ULL << INTERCEPT_VMRUN) |
570 (1ULL << INTERCEPT_VMMCALL) |
571 (1ULL << INTERCEPT_VMLOAD) |
572 (1ULL << INTERCEPT_VMSAVE) |
573 (1ULL << INTERCEPT_STGI) |
574 (1ULL << INTERCEPT_CLGI) |
916ce236 575 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 576 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 577 (1ULL << INTERCEPT_MONITOR) |
578 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 579
580 control->iopm_base_pa = iopm_base;
f65c229c 581 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 582 control->tsc_offset = 0;
6aa8b732
AK		 583 control->int_ctl = V_INTR_MASKING_MASK;
584
585 init_seg(&save->es);
586 init_seg(&save->ss);
587 init_seg(&save->ds);
588 init_seg(&save->fs);
589 init_seg(&save->gs);
590
591 save->cs.selector = 0xf000;
592 /* Executable/Readable Code Segment */
593 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
594 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
595 save->cs.limit = 0xffff;
d92899a0
AK		 596 /*
597 * cs.base should really be 0xffff0000, but vmx can't handle that, so
598 * be consistent with it.
599 *
600 * Replace when we have real mode working for vmx.
601 */
602 save->cs.base = 0xf0000;
6aa8b732
AK		 603
604 save->gdtr.limit = 0xffff;
605 save->idtr.limit = 0xffff;
606
607 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
608 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
609
9962d032 610 save->efer = EFER_SVME;
d77c26fc 611 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 612 save->dr7 = 0x400;
613 save->rflags = 2;
614 save->rip = 0x0000fff0;
5fdbf976 615 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 616
617 /*
618 * cr0 val on cpu init should be 0x60000010, we enable cpu
619 * cache by default. the orderly way is to enable cache in bios.
620 */
707d92fa 621 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 622 save->cr4 = X86_CR4_PAE;
6aa8b732 623 /* rdx = ?? */
709ddebf
JR		 624
625 if (npt_enabled) {
626 /* Setup VMCB for Nested Paging */
627 control->nested_ctl = 1;
a7052897
MT		 628 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
629 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 630 control->intercept_exceptions &= ~(1 << PF_VECTOR);
631 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
632 INTERCEPT_CR3_MASK);
633 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
634 INTERCEPT_CR3_MASK);
635 save->g_pat = 0x0007040600070406ULL;
636 /* enable caching because the QEMU Bios doesn't enable it */
637 save->cr0 = X86_CR0_ET;
638 save->cr3 = 0;
639 save->cr4 = 0;
640 }
a79d2f18 641 force_new_asid(&svm->vcpu);
1371d904 642
e6aa9abd 643 svm->nested.vmcb = 0;
2af9194d
JR		 644 svm->vcpu.arch.hflags = 0;
645
646 enable_gif(svm);
6aa8b732
AK		 647}
648
e00c8cf2 649static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 650{
651 struct vcpu_svm *svm = to_svm(vcpu);
652
e6101a96 653 init_vmcb(svm);
70433389 654
c5af89b6 655 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 656 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 657 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
658 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 659 }
5fdbf976
MT		 660 vcpu->arch.regs_avail = ~0;
661 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 662
663 return 0;
04d2cc77
AK		 664}
665
fb3f0f51 666static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 667{
a2fa3e9f 668 struct vcpu_svm *svm;
6aa8b732 669 struct page *page;
f65c229c 670 struct page *msrpm_pages;
b286d5d8 671 struct page *hsave_page;
3d6368ef 672 struct page *nested_msrpm_pages;
fb3f0f51 673 int err;
6aa8b732 674
c16f862d 675 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 676 if (!svm) {
677 err = -ENOMEM;
678 goto out;
679 }
680
681 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
682 if (err)
683 goto free_svm;
684
6aa8b732 685 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 686 if (!page) {
687 err = -ENOMEM;
688 goto uninit;
689 }
6aa8b732 690
f65c229c
JR		 691 err = -ENOMEM;
692 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
693 if (!msrpm_pages)
694 goto uninit;
3d6368ef
AG		 695
696 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
697 if (!nested_msrpm_pages)
698 goto uninit;
699
f65c229c
JR		 700 svm->msrpm = page_address(msrpm_pages);
701 svm_vcpu_init_msrpm(svm->msrpm);
702
b286d5d8
AG		 703 hsave_page = alloc_page(GFP_KERNEL);
704 if (!hsave_page)
705 goto uninit;
e6aa9abd 706 svm->nested.hsave = page_address(hsave_page);
b286d5d8 707
e6aa9abd 708 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 709
a2fa3e9f
GH		 710 svm->vmcb = page_address(page);
711 clear_page(svm->vmcb);
712 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
713 svm->asid_generation = 0;
e6101a96 714 init_vmcb(svm);
a2fa3e9f 715
fb3f0f51
RR		 716 fx_init(&svm->vcpu);
717 svm->vcpu.fpu_active = 1;
ad312c7c 718 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 719 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 720 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 721
fb3f0f51 722 return &svm->vcpu;
36241b8c 723
fb3f0f51
RR		 724uninit:
725 kvm_vcpu_uninit(&svm->vcpu);
726free_svm:
a4770347 727 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 728out:
729 return ERR_PTR(err);
6aa8b732
AK		 730}
731
732static void svm_free_vcpu(struct kvm_vcpu *vcpu)
733{
a2fa3e9f
GH		 734 struct vcpu_svm *svm = to_svm(vcpu);
735
fb3f0f51 736 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 737 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 738 __free_page(virt_to_page(svm->nested.hsave));
739 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 740 kvm_vcpu_uninit(vcpu);
a4770347 741 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 742}
743
15ad7146 744static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 745{
a2fa3e9f 746 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 747 int i;
0cc5064d 748
0cc5064d
AK		 749 if (unlikely(cpu != vcpu->cpu)) {
750 u64 tsc_this, delta;
751
752 /*
753 * Make sure that the guest sees a monotonically
754 * increasing TSC.
755 */
756 rdtscll(tsc_this);
ad312c7c 757 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 758 svm->vmcb->control.tsc_offset += delta;
0cc5064d 759 vcpu->cpu = cpu;
2f599714 760 kvm_migrate_timers(vcpu);
4b656b12 761 svm->asid_generation = 0;
0cc5064d 762 }
94dfbdb3
AL		 763
764 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 765 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 766}
767
768static void svm_vcpu_put(struct kvm_vcpu *vcpu)
769{
a2fa3e9f 770 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 771 int i;
772
e1beb1d3 773 ++vcpu->stat.host_state_reload;
94dfbdb3 774 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 775 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 776
ad312c7c 777 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 778}
779
6aa8b732
AK		 780static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
781{
a2fa3e9f 782 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 783}
784
785static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
786{
a2fa3e9f 787 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 788}
789
6de4f3ad
AK		 790static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
791{
792 switch (reg) {
793 case VCPU_EXREG_PDPTR:
794 BUG_ON(!npt_enabled);
795 load_pdptrs(vcpu, vcpu->arch.cr3);
796 break;
797 default:
798 BUG();
799 }
800}
801
f0b85051
AG		 802static void svm_set_vintr(struct vcpu_svm *svm)
803{
804 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
805}
806
807static void svm_clear_vintr(struct vcpu_svm *svm)
808{
809 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
810}
811
6aa8b732
AK		 812static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
813{
a2fa3e9f 814 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 815
816 switch (seg) {
817 case VCPU_SREG_CS: return &save->cs;
818 case VCPU_SREG_DS: return &save->ds;
819 case VCPU_SREG_ES: return &save->es;
820 case VCPU_SREG_FS: return &save->fs;
821 case VCPU_SREG_GS: return &save->gs;
822 case VCPU_SREG_SS: return &save->ss;
823 case VCPU_SREG_TR: return &save->tr;
824 case VCPU_SREG_LDTR: return &save->ldtr;
825 }
826 BUG();
8b6d44c7 827 return NULL;
6aa8b732
AK		 828}
829
830static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
831{
832 struct vmcb_seg *s = svm_seg(vcpu, seg);
833
834 return s->base;
835}
836
837static void svm_get_segment(struct kvm_vcpu *vcpu,
838 struct kvm_segment *var, int seg)
839{
840 struct vmcb_seg *s = svm_seg(vcpu, seg);
841
842 var->base = s->base;
843 var->limit = s->limit;
844 var->selector = s->selector;
845 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
846 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
847 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
848 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
849 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
850 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
851 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
852 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 853
19bca6ab
AP		 854 /* AMD's VMCB does not have an explicit unusable field, so emulate it
855 * for cross vendor migration purposes by "not present"
856 */
857 var->unusable = !var->present || (var->type == 0);
858
1fbdc7a5
AP		 859 switch (seg) {
860 case VCPU_SREG_CS:
861 /*
862 * SVM always stores 0 for the 'G' bit in the CS selector in
863 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
864 * Intel's VMENTRY has a check on the 'G' bit.
865 */
25022acc 866 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 867 break;
868 case VCPU_SREG_TR:
869 /*
870 * Work around a bug where the busy flag in the tr selector
871 * isn't exposed
872 */
c0d09828 873 var->type |= 0x2;
1fbdc7a5
AP		 874 break;
875 case VCPU_SREG_DS:
876 case VCPU_SREG_ES:
877 case VCPU_SREG_FS:
878 case VCPU_SREG_GS:
879 /*
880 * The accessed bit must always be set in the segment
881 * descriptor cache, although it can be cleared in the
882 * descriptor, the cached bit always remains at 1. Since
883 * Intel has a check on this, set it here to support
884 * cross-vendor migration.
885 */
886 if (!var->unusable)
887 var->type |= 0x1;
888 break;
b586eb02
AP		 889 case VCPU_SREG_SS:
890 /* On AMD CPUs sometimes the DB bit in the segment
891 * descriptor is left as 1, although the whole segment has
892 * been made unusable. Clear it here to pass an Intel VMX
893 * entry check when cross vendor migrating.
894 */
895 if (var->unusable)
896 var->db = 0;
897 break;
1fbdc7a5 898 }
6aa8b732
AK		 899}
900
2e4d2653
IE		 901static int svm_get_cpl(struct kvm_vcpu *vcpu)
902{
903 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
904
905 return save->cpl;
906}
907
6aa8b732
AK		 908static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
909{
a2fa3e9f
GH		 910 struct vcpu_svm *svm = to_svm(vcpu);
911
912 dt->limit = svm->vmcb->save.idtr.limit;
913 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 914}
915
916static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
917{
a2fa3e9f
GH		 918 struct vcpu_svm *svm = to_svm(vcpu);
919
920 svm->vmcb->save.idtr.limit = dt->limit;
921 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 922}
923
924static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
925{
a2fa3e9f
GH		 926 struct vcpu_svm *svm = to_svm(vcpu);
927
928 dt->limit = svm->vmcb->save.gdtr.limit;
929 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 930}
931
932static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
933{
a2fa3e9f
GH		 934 struct vcpu_svm *svm = to_svm(vcpu);
935
936 svm->vmcb->save.gdtr.limit = dt->limit;
937 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 938}
939
25c4c276 940static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 941{
942}
943
6aa8b732
AK		 944static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
945{
a2fa3e9f
GH		 946 struct vcpu_svm *svm = to_svm(vcpu);
947
05b3e0c2 948#ifdef CONFIG_X86_64
ad312c7c 949 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 950 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 951 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 952 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 953 }
954
d77c26fc 955 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 956 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 957 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 958 }
959 }
960#endif
709ddebf
JR		 961 if (npt_enabled)
962 goto set;
963
ad312c7c 964 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 965 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 966 vcpu->fpu_active = 1;
967 }
968
ad312c7c 969 vcpu->arch.cr0 = cr0;
707d92fa 970 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 971 if (!vcpu->fpu_active) {
972 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 973 cr0 |= X86_CR0_TS;
6b390b63 974 }
709ddebf
JR		 975set:
976 /*
977 * re-enable caching here because the QEMU bios
978 * does not do it - this results in some delay at
979 * reboot
980 */
981 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 982 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 983}
984
985static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
986{
6394b649 987 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 988 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
989
990 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
991 force_new_asid(vcpu);
6394b649 992
ec077263
JR		 993 vcpu->arch.cr4 = cr4;
994 if (!npt_enabled)
995 cr4 |= X86_CR4_PAE;
6394b649 996 cr4 |= host_cr4_mce;
ec077263 997 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 998}
999
1000static void svm_set_segment(struct kvm_vcpu *vcpu,
1001 struct kvm_segment *var, int seg)
1002{
a2fa3e9f 1003 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1004 struct vmcb_seg *s = svm_seg(vcpu, seg);
1005
1006 s->base = var->base;
1007 s->limit = var->limit;
1008 s->selector = var->selector;
1009 if (var->unusable)
1010 s->attrib = 0;
1011 else {
1012 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1013 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1014 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1015 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1016 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1017 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1018 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1019 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1020 }
1021 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1022 svm->vmcb->save.cpl
1023 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1024 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1025
1026}
1027
44c11430 1028static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1029{
d0bfb940
JK		 1030 struct vcpu_svm *svm = to_svm(vcpu);
1031
d0bfb940
JK		 1032 svm->vmcb->control.intercept_exceptions &=
1033 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1034
1035 if (vcpu->arch.singlestep)
1036 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1037
d0bfb940
JK		 1038 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1039 if (vcpu->guest_debug &
1040 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1041 svm->vmcb->control.intercept_exceptions |=
1042 1 << DB_VECTOR;
1043 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1044 svm->vmcb->control.intercept_exceptions |=
1045 1 << BP_VECTOR;
1046 } else
1047 vcpu->guest_debug = 0;
44c11430
GN		 1048}
1049
1050static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1051{
1052 int old_debug = vcpu->guest_debug;
1053 struct vcpu_svm *svm = to_svm(vcpu);
1054
1055 vcpu->guest_debug = dbg->control;
1056
1057 update_db_intercept(vcpu);
d0bfb940 1058
ae675ef0
JK		 1059 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1060 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1061 else
1062 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1063
d0bfb940
JK		 1064 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1065 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1066 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1067 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1068
1069 return 0;
6aa8b732
AK		 1070}
1071
1072static void load_host_msrs(struct kvm_vcpu *vcpu)
1073{
94dfbdb3 1074#ifdef CONFIG_X86_64
a2fa3e9f 1075 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1076#endif
6aa8b732
AK		 1077}
1078
1079static void save_host_msrs(struct kvm_vcpu *vcpu)
1080{
94dfbdb3 1081#ifdef CONFIG_X86_64
a2fa3e9f 1082 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1083#endif
6aa8b732
AK		 1084}
1085
e756fc62 1086static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1087{
1088 if (svm_data->next_asid > svm_data->max_asid) {
1089 ++svm_data->asid_generation;
1090 svm_data->next_asid = 1;
a2fa3e9f 1091 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1092 }
1093
a2fa3e9f
GH		 1094 svm->asid_generation = svm_data->asid_generation;
1095 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1096}
1097
6aa8b732
AK		 1098static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1099{
42dbaa5a
JK		 1100 struct vcpu_svm *svm = to_svm(vcpu);
1101 unsigned long val;
1102
1103 switch (dr) {
1104 case 0 ... 3:
1105 val = vcpu->arch.db[dr];
1106 break;
1107 case 6:
1108 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1109 val = vcpu->arch.dr6;
1110 else
1111 val = svm->vmcb->save.dr6;
1112 break;
1113 case 7:
1114 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1115 val = vcpu->arch.dr7;
1116 else
1117 val = svm->vmcb->save.dr7;
1118 break;
1119 default:
1120 val = 0;
1121 }
1122
af9ca2d7 1123 return val;
6aa8b732
AK		 1124}
1125
1126static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1127 int *exception)
1128{
a2fa3e9f
GH		 1129 struct vcpu_svm *svm = to_svm(vcpu);
1130
42dbaa5a 1131 *exception = 0;
6aa8b732
AK		 1132
1133 switch (dr) {
1134 case 0 ... 3:
42dbaa5a
JK		 1135 vcpu->arch.db[dr] = value;
1136 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1137 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1138 return;
1139 case 4 ... 5:
42dbaa5a 1140 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1141 *exception = UD_VECTOR;
42dbaa5a
JK		 1142 return;
1143 case 6:
1144 if (value & 0xffffffff00000000ULL) {
1145 *exception = GP_VECTOR;
6aa8b732
AK		 1146 return;
1147 }
42dbaa5a
JK		 1148 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1149 return;
1150 case 7:
1151 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1152 *exception = GP_VECTOR;
1153 return;
1154 }
42dbaa5a
JK		 1155 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1156 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1157 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1158 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1159 }
6aa8b732 1160 return;
6aa8b732 1161 default:
42dbaa5a 1162 /* FIXME: Possible case? */
6aa8b732 1163 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1164 __func__, dr);
6aa8b732
AK		 1165 *exception = UD_VECTOR;
1166 return;
1167 }
1168}
1169
e756fc62 1170static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1171{
6aa8b732
AK		 1172 u64 fault_address;
1173 u32 error_code;
6aa8b732 1174
a2fa3e9f
GH		 1175 fault_address = svm->vmcb->control.exit_info_2;
1176 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1177
229456fc 1178 trace_kvm_page_fault(fault_address, error_code);
44874f84
JR		 1179 /*
1180 * FIXME: Tis shouldn't be necessary here, but there is a flush
1181 * missing in the MMU code. Until we find this bug, flush the
1182 * complete TLB here on an NPF
1183 */
1184 if (npt_enabled)
1185 svm_flush_tlb(&svm->vcpu);
9222be18 1186 else {
3298b75c 1187 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1188 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1189 }
3067714c 1190 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1191}
1192
d0bfb940
JK		 1193static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1194{
1195 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1196 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1197 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1198 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1199 return 1;
1200 }
44c11430
GN		 1201
1202 if (svm->vcpu.arch.singlestep) {
1203 svm->vcpu.arch.singlestep = false;
1204 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1205 svm->vmcb->save.rflags &=
1206 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1207 update_db_intercept(&svm->vcpu);
1208 }
1209
1210 if (svm->vcpu.guest_debug &
1211 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1212 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1213 kvm_run->debug.arch.pc =
1214 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1215 kvm_run->debug.arch.exception = DB_VECTOR;
1216 return 0;
1217 }
1218
1219 return 1;
d0bfb940
JK		 1220}
1221
1222static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1223{
1224 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1225 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1226 kvm_run->debug.arch.exception = BP_VECTOR;
1227 return 0;
1228}
1229
7aa81cc0
AL		 1230static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1231{
1232 int er;
1233
571008da 1234 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1235 if (er != EMULATE_DONE)
7ee5d940 1236 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1237 return 1;
1238}
1239
e756fc62 1240static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1241{
a2fa3e9f 1242 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1243 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1244 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1245 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1246
1247 return 1;
7807fa6c
AL		 1248}
1249
53371b50
JR		 1250static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1251{
1252 /*
1253 * On an #MC intercept the MCE handler is not called automatically in
1254 * the host. So do it by hand here.
1255 */
1256 asm volatile (
1257 "int $0x12\n");
1258 /* not sure if we ever come back to this point */
1259
1260 return 1;
1261}
1262
e756fc62 1263static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1264{
1265 /*
1266 * VMCB is undefined after a SHUTDOWN intercept
1267 * so reinitialize it.
1268 */
a2fa3e9f 1269 clear_page(svm->vmcb);
e6101a96 1270 init_vmcb(svm);
46fe4ddd
JR		 1271
1272 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1273 return 0;
1274}
1275
e756fc62 1276static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1277{
d77c26fc 1278 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1279 int size, in, string;
039576c0 1280 unsigned port;
6aa8b732 1281
e756fc62 1282 ++svm->vcpu.stat.io_exits;
6aa8b732 1283
a2fa3e9f 1284 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1285
e70669ab
LV		 1286 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1287
1288 if (string) {
3427318f
LV		 1289 if (emulate_instruction(&svm->vcpu,
1290 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1291 return 0;
1292 return 1;
1293 }
1294
039576c0
AK		 1295 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1296 port = io_info >> 16;
1297 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1298
e93f36bc 1299 skip_emulated_instruction(&svm->vcpu);
3090dd73 1300 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1301}
1302
c47f098d
JR		 1303static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1304{
1305 return 1;
1306}
1307
a0698055
JR		 1308static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1309{
1310 ++svm->vcpu.stat.irq_exits;
1311 return 1;
1312}
1313
e756fc62 1314static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1315{
1316 return 1;
1317}
1318
e756fc62 1319static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1320{
5fdbf976 1321 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1322 skip_emulated_instruction(&svm->vcpu);
1323 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1324}
1325
e756fc62 1326static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1327{
5fdbf976 1328 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1329 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1330 kvm_emulate_hypercall(&svm->vcpu);
1331 return 1;
02e235bc
AK		 1332}
1333
c0725420
AG		 1334static int nested_svm_check_permissions(struct vcpu_svm *svm)
1335{
1336 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1337 || !is_paging(&svm->vcpu)) {
1338 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1339 return 1;
1340 }
1341
1342 if (svm->vmcb->save.cpl) {
1343 kvm_inject_gp(&svm->vcpu, 0);
1344 return 1;
1345 }
1346
1347 return 0;
1348}
1349
cf74a78b
AG		 1350static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1351 bool has_error_code, u32 error_code)
1352{
1353 if (is_nested(svm)) {
1354 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1355 svm->vmcb->control.exit_code_hi = 0;
1356 svm->vmcb->control.exit_info_1 = error_code;
1357 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1358 if (nested_svm_exit_handled(svm, false)) {
1359 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1360
1361 nested_svm_vmexit(svm);
1362 return 1;
1363 }
1364 }
1365
1366 return 0;
1367}
1368
1369static inline int nested_svm_intr(struct vcpu_svm *svm)
1370{
1371 if (is_nested(svm)) {
1372 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1373 return 0;
1374
1375 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1376 return 0;
1377
1378 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1379
1380 if (nested_svm_exit_handled(svm, false)) {
1381 nsvm_printk("VMexit -> INTR\n");
1382 nested_svm_vmexit(svm);
1383 return 1;
1384 }
1385 }
1386
1387 return 0;
1388}
1389
c0725420
AG		 1390static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1391{
1392 struct page *page;
1393
1394 down_read(&current->mm->mmap_sem);
1395 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1396 up_read(&current->mm->mmap_sem);
1397
1398 if (is_error_page(page)) {
1399 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1400 __func__, gpa);
1401 kvm_release_page_clean(page);
1402 kvm_inject_gp(&svm->vcpu, 0);
1403 return NULL;
1404 }
1405 return page;
1406}
1407
1408static int nested_svm_do(struct vcpu_svm *svm,
1409 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1410 int (*handler)(struct vcpu_svm *svm,
1411 void *arg1,
1412 void *arg2,
1413 void *opaque))
1414{
1415 struct page *arg1_page;
1416 struct page *arg2_page = NULL;
1417 void *arg1;
1418 void *arg2 = NULL;
1419 int retval;
1420
1421 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1422 if(arg1_page == NULL)
1423 return 1;
1424
1425 if (arg2_gpa) {
1426 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1427 if(arg2_page == NULL) {
1428 kvm_release_page_clean(arg1_page);
1429 return 1;
1430 }
1431 }
1432
1433 arg1 = kmap_atomic(arg1_page, KM_USER0);
1434 if (arg2_gpa)
1435 arg2 = kmap_atomic(arg2_page, KM_USER1);
1436
1437 retval = handler(svm, arg1, arg2, opaque);
1438
1439 kunmap_atomic(arg1, KM_USER0);
1440 if (arg2_gpa)
1441 kunmap_atomic(arg2, KM_USER1);
1442
1443 kvm_release_page_dirty(arg1_page);
1444 if (arg2_gpa)
1445 kvm_release_page_dirty(arg2_page);
1446
1447 return retval;
1448}
1449
cf74a78b
AG		 1450static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1451 void *arg1,
1452 void *arg2,
1453 void *opaque)
1454{
1455 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1456 bool kvm_overrides = *(bool *)opaque;
1457 u32 exit_code = svm->vmcb->control.exit_code;
1458
1459 if (kvm_overrides) {
1460 switch (exit_code) {
1461 case SVM_EXIT_INTR:
1462 case SVM_EXIT_NMI:
1463 return 0;
1464 /* For now we are always handling NPFs when using them */
1465 case SVM_EXIT_NPF:
1466 if (npt_enabled)
1467 return 0;
1468 break;
1469 /* When we're shadowing, trap PFs */
1470 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1471 if (!npt_enabled)
1472 return 0;
1473 break;
1474 default:
1475 break;
1476 }
1477 }
1478
1479 switch (exit_code) {
1480 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1481 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1482 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1483 return 1;
1484 break;
1485 }
1486 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1487 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1488 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1489 return 1;
1490 break;
1491 }
1492 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1493 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1494 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1495 return 1;
1496 break;
1497 }
1498 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1499 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1500 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1501 return 1;
1502 break;
1503 }
1504 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1505 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1506 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1507 return 1;
1508 break;
1509 }
1510 default: {
1511 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1512 nsvm_printk("exit code: 0x%x\n", exit_code);
1513 if (nested_vmcb->control.intercept & exit_bits)
1514 return 1;
1515 }
1516 }
1517
1518 return 0;
1519}
1520
1521static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1522 void *arg1, void *arg2,
1523 void *opaque)
1524{
1525 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1526 u8 *msrpm = (u8 *)arg2;
1527 u32 t0, t1;
1528 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1529 u32 param = svm->vmcb->control.exit_info_1 & 1;
1530
1531 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1532 return 0;
1533
1534 switch(msr) {
1535 case 0 ... 0x1fff:
1536 t0 = (msr * 2) % 8;
1537 t1 = msr / 8;
1538 break;
1539 case 0xc0000000 ... 0xc0001fff:
1540 t0 = (8192 + msr - 0xc0000000) * 2;
1541 t1 = (t0 / 8);
1542 t0 %= 8;
1543 break;
1544 case 0xc0010000 ... 0xc0011fff:
1545 t0 = (16384 + msr - 0xc0010000) * 2;
1546 t1 = (t0 / 8);
1547 t0 %= 8;
1548 break;
1549 default:
1550 return 1;
1551 break;
1552 }
1553 if (msrpm[t1] & ((1 << param) << t0))
1554 return 1;
1555
1556 return 0;
1557}
1558
1559static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1560{
1561 bool k = kvm_override;
1562
1563 switch (svm->vmcb->control.exit_code) {
1564 case SVM_EXIT_MSR:
e6aa9abd
JR		 1565 return nested_svm_do(svm, svm->nested.vmcb,
1566 svm->nested.vmcb_msrpm, NULL,
cf74a78b
AG		 1567 nested_svm_exit_handled_msr);
1568 default: break;
1569 }
1570
e6aa9abd 1571 return nested_svm_do(svm, svm->nested.vmcb, 0, &k,
cf74a78b
AG		 1572 nested_svm_exit_handled_real);
1573}
1574
0460a979
JR		 1575static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1576{
1577 struct vmcb_control_area *dst = &dst_vmcb->control;
1578 struct vmcb_control_area *from = &from_vmcb->control;
1579
1580 dst->intercept_cr_read = from->intercept_cr_read;
1581 dst->intercept_cr_write = from->intercept_cr_write;
1582 dst->intercept_dr_read = from->intercept_dr_read;
1583 dst->intercept_dr_write = from->intercept_dr_write;
1584 dst->intercept_exceptions = from->intercept_exceptions;
1585 dst->intercept = from->intercept;
1586 dst->iopm_base_pa = from->iopm_base_pa;
1587 dst->msrpm_base_pa = from->msrpm_base_pa;
1588 dst->tsc_offset = from->tsc_offset;
1589 dst->asid = from->asid;
1590 dst->tlb_ctl = from->tlb_ctl;
1591 dst->int_ctl = from->int_ctl;
1592 dst->int_vector = from->int_vector;
1593 dst->int_state = from->int_state;
1594 dst->exit_code = from->exit_code;
1595 dst->exit_code_hi = from->exit_code_hi;
1596 dst->exit_info_1 = from->exit_info_1;
1597 dst->exit_info_2 = from->exit_info_2;
1598 dst->exit_int_info = from->exit_int_info;
1599 dst->exit_int_info_err = from->exit_int_info_err;
1600 dst->nested_ctl = from->nested_ctl;
1601 dst->event_inj = from->event_inj;
1602 dst->event_inj_err = from->event_inj_err;
1603 dst->nested_cr3 = from->nested_cr3;
1604 dst->lbr_ctl = from->lbr_ctl;
1605}
1606
cf74a78b
AG		 1607static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1608 void *arg2, void *opaque)
1609{
1610 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
e6aa9abd 1611 struct vmcb *hsave = svm->nested.hsave;
33740e40 1612 struct vmcb *vmcb = svm->vmcb;
cf74a78b
AG		 1613
1614 /* Give the current vmcb to the guest */
33740e40
JR		 1615 disable_gif(svm);
1616
1617 nested_vmcb->save.es = vmcb->save.es;
1618 nested_vmcb->save.cs = vmcb->save.cs;
1619 nested_vmcb->save.ss = vmcb->save.ss;
1620 nested_vmcb->save.ds = vmcb->save.ds;
1621 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1622 nested_vmcb->save.idtr = vmcb->save.idtr;
1623 if (npt_enabled)
1624 nested_vmcb->save.cr3 = vmcb->save.cr3;
1625 nested_vmcb->save.cr2 = vmcb->save.cr2;
1626 nested_vmcb->save.rflags = vmcb->save.rflags;
1627 nested_vmcb->save.rip = vmcb->save.rip;
1628 nested_vmcb->save.rsp = vmcb->save.rsp;
1629 nested_vmcb->save.rax = vmcb->save.rax;
1630 nested_vmcb->save.dr7 = vmcb->save.dr7;
1631 nested_vmcb->save.dr6 = vmcb->save.dr6;
1632 nested_vmcb->save.cpl = vmcb->save.cpl;
1633
1634 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1635 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1636 nested_vmcb->control.int_state = vmcb->control.int_state;
1637 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1638 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1639 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1640 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1641 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1642 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1643 nested_vmcb->control.tlb_ctl = 0;
1644 nested_vmcb->control.event_inj = 0;
1645 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1646
1647 /* We always set V_INTR_MASKING and remember the old value in hflags */
1648 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1649 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1650
cf74a78b 1651 /* Restore the original control entries */
0460a979 1652 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1653
1654 /* Kill any pending exceptions */
1655 if (svm->vcpu.arch.exception.pending == true)
1656 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1657
219b65dc
AG		 1658 kvm_clear_exception_queue(&svm->vcpu);
1659 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1660
1661 /* Restore selected save entries */
1662 svm->vmcb->save.es = hsave->save.es;
1663 svm->vmcb->save.cs = hsave->save.cs;
1664 svm->vmcb->save.ss = hsave->save.ss;
1665 svm->vmcb->save.ds = hsave->save.ds;
1666 svm->vmcb->save.gdtr = hsave->save.gdtr;
1667 svm->vmcb->save.idtr = hsave->save.idtr;
1668 svm->vmcb->save.rflags = hsave->save.rflags;
1669 svm_set_efer(&svm->vcpu, hsave->save.efer);
1670 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1671 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1672 if (npt_enabled) {
1673 svm->vmcb->save.cr3 = hsave->save.cr3;
1674 svm->vcpu.arch.cr3 = hsave->save.cr3;
1675 } else {
1676 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1677 }
1678 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1679 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1680 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1681 svm->vmcb->save.dr7 = 0;
1682 svm->vmcb->save.cpl = 0;
1683 svm->vmcb->control.exit_int_info = 0;
1684
cf74a78b 1685 /* Exit nested SVM mode */
e6aa9abd 1686 svm->nested.vmcb = 0;
cf74a78b
AG		 1687
1688 return 0;
1689}
1690
1691static int nested_svm_vmexit(struct vcpu_svm *svm)
1692{
1693 nsvm_printk("VMexit\n");
e6aa9abd 1694 if (nested_svm_do(svm, svm->nested.vmcb, 0,
cf74a78b
AG		 1695 NULL, nested_svm_vmexit_real))
1696 return 1;
1697
1698 kvm_mmu_reset_context(&svm->vcpu);
1699 kvm_mmu_load(&svm->vcpu);
1700
1701 return 0;
1702}
3d6368ef
AG		 1703
1704static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1705 void *arg2, void *opaque)
1706{
1707 int i;
1708 u32 *nested_msrpm = (u32*)arg1;
1709 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd
JR		 1710 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1711 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef
AG		 1712
1713 return 0;
1714}
1715
1716static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1717 void *arg2, void *opaque)
1718{
1719 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
e6aa9abd 1720 struct vmcb *hsave = svm->nested.hsave;
defbba56 1721 struct vmcb *vmcb = svm->vmcb;
3d6368ef
AG		 1722
1723 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1724 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef
AG		 1725
1726 /* Clear internal status */
219b65dc
AG		 1727 kvm_clear_exception_queue(&svm->vcpu);
1728 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1729
1730 /* Save the old vmcb, so we don't need to pick what we save, but
1731 can restore everything when a VMEXIT occurs */
defbba56
JR		 1732 hsave->save.es = vmcb->save.es;
1733 hsave->save.cs = vmcb->save.cs;
1734 hsave->save.ss = vmcb->save.ss;
1735 hsave->save.ds = vmcb->save.ds;
1736 hsave->save.gdtr = vmcb->save.gdtr;
1737 hsave->save.idtr = vmcb->save.idtr;
1738 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1739 hsave->save.cr0 = svm->vcpu.arch.cr0;
1740 hsave->save.cr4 = svm->vcpu.arch.cr4;
1741 hsave->save.rflags = vmcb->save.rflags;
1742 hsave->save.rip = svm->next_rip;
1743 hsave->save.rsp = vmcb->save.rsp;
1744 hsave->save.rax = vmcb->save.rax;
1745 if (npt_enabled)
1746 hsave->save.cr3 = vmcb->save.cr3;
1747 else
1748 hsave->save.cr3 = svm->vcpu.arch.cr3;
1749
0460a979 1750 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1751
1752 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1753 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1754 else
1755 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1756
1757 /* Load the nested guest state */
1758 svm->vmcb->save.es = nested_vmcb->save.es;
1759 svm->vmcb->save.cs = nested_vmcb->save.cs;
1760 svm->vmcb->save.ss = nested_vmcb->save.ss;
1761 svm->vmcb->save.ds = nested_vmcb->save.ds;
1762 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1763 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1764 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1765 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1766 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1767 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1768 if (npt_enabled) {
1769 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1770 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1771 } else {
1772 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1773 kvm_mmu_reset_context(&svm->vcpu);
1774 }
defbba56 1775 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1776 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1777 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1778 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1779 /* In case we don't even reach vcpu_run, the fields are not updated */
1780 svm->vmcb->save.rax = nested_vmcb->save.rax;
1781 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1782 svm->vmcb->save.rip = nested_vmcb->save.rip;
1783 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1784 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1785 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1786
1787 /* We don't want a nested guest to be more powerful than the guest,
1788 so all intercepts are ORed */
1789 svm->vmcb->control.intercept_cr_read |=
1790 nested_vmcb->control.intercept_cr_read;
1791 svm->vmcb->control.intercept_cr_write |=
1792 nested_vmcb->control.intercept_cr_write;
1793 svm->vmcb->control.intercept_dr_read |=
1794 nested_vmcb->control.intercept_dr_read;
1795 svm->vmcb->control.intercept_dr_write |=
1796 nested_vmcb->control.intercept_dr_write;
1797 svm->vmcb->control.intercept_exceptions |=
1798 nested_vmcb->control.intercept_exceptions;
1799
1800 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1801
e6aa9abd 1802 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef
AG		 1803
1804 force_new_asid(&svm->vcpu);
1805 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1806 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1807 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1808 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1809 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1810 nested_vmcb->control.int_ctl);
1811 }
1812 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1813 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1814 else
1815 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1816
1817 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1818 nested_vmcb->control.exit_int_info,
1819 nested_vmcb->control.int_state);
1820
1821 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1822 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1823 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1824 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1825 nsvm_printk("Injecting Event: 0x%x\n",
1826 nested_vmcb->control.event_inj);
1827 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1828 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1829
2af9194d 1830 enable_gif(svm);
3d6368ef
AG		 1831
1832 return 0;
1833}
1834
5542675b
AG		 1835static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1836{
1837 to_vmcb->save.fs = from_vmcb->save.fs;
1838 to_vmcb->save.gs = from_vmcb->save.gs;
1839 to_vmcb->save.tr = from_vmcb->save.tr;
1840 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1841 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1842 to_vmcb->save.star = from_vmcb->save.star;
1843 to_vmcb->save.lstar = from_vmcb->save.lstar;
1844 to_vmcb->save.cstar = from_vmcb->save.cstar;
1845 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1846 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1847 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1848 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1849
1850 return 1;
1851}
1852
1853static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1854 void *arg2, void *opaque)
1855{
1856 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1857}
1858
1859static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1860 void *arg2, void *opaque)
1861{
1862 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1863}
1864
1865static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1866{
1867 if (nested_svm_check_permissions(svm))
1868 return 1;
1869
1870 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1871 skip_emulated_instruction(&svm->vcpu);
1872
1873 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1874
1875 return 1;
1876}
1877
1878static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1879{
1880 if (nested_svm_check_permissions(svm))
1881 return 1;
1882
1883 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1884 skip_emulated_instruction(&svm->vcpu);
1885
1886 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1887
1888 return 1;
1889}
1890
3d6368ef
AG		 1891static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1892{
1893 nsvm_printk("VMrun\n");
1894 if (nested_svm_check_permissions(svm))
1895 return 1;
1896
1897 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1898 skip_emulated_instruction(&svm->vcpu);
1899
1900 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1901 NULL, nested_svm_vmrun))
1902 return 1;
1903
e6aa9abd 1904 if (nested_svm_do(svm, svm->nested.vmcb_msrpm, 0,
3d6368ef
AG		 1905 NULL, nested_svm_vmrun_msrpm))
1906 return 1;
1907
1908 return 1;
1909}
1910
1371d904
AG		 1911static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1912{
1913 if (nested_svm_check_permissions(svm))
1914 return 1;
1915
1916 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1917 skip_emulated_instruction(&svm->vcpu);
1918
2af9194d 1919 enable_gif(svm);
1371d904
AG		 1920
1921 return 1;
1922}
1923
1924static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1925{
1926 if (nested_svm_check_permissions(svm))
1927 return 1;
1928
1929 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1930 skip_emulated_instruction(&svm->vcpu);
1931
2af9194d 1932 disable_gif(svm);
1371d904
AG		 1933
1934 /* After a CLGI no interrupts should come */
1935 svm_clear_vintr(svm);
1936 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1937
1938 return 1;
1939}
1940
ff092385
AG		 1941static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1942{
1943 struct kvm_vcpu *vcpu = &svm->vcpu;
1944 nsvm_printk("INVLPGA\n");
1945
1946 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1947 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1948
1949 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1950 skip_emulated_instruction(&svm->vcpu);
1951 return 1;
1952}
1953
e756fc62
RR		 1954static int invalid_op_interception(struct vcpu_svm *svm,
1955 struct kvm_run *kvm_run)
6aa8b732 1956{
7ee5d940 1957 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1958 return 1;
1959}
1960
e756fc62
RR		 1961static int task_switch_interception(struct vcpu_svm *svm,
1962 struct kvm_run *kvm_run)
6aa8b732 1963{
37817f29 1964 u16 tss_selector;
64a7ec06
GN		 1965 int reason;
1966 int int_type = svm->vmcb->control.exit_int_info &
1967 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1968 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1969 uint32_t type =
1970 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1971 uint32_t idt_v =
1972 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1973
1974 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1975
37817f29
IE		 1976 if (svm->vmcb->control.exit_info_2 &
1977 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1978 reason = TASK_SWITCH_IRET;
1979 else if (svm->vmcb->control.exit_info_2 &
1980 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1981 reason = TASK_SWITCH_JMP;
fe8e7f83 1982 else if (idt_v)
64a7ec06
GN		 1983 reason = TASK_SWITCH_GATE;
1984 else
1985 reason = TASK_SWITCH_CALL;
1986
fe8e7f83
GN		 1987 if (reason == TASK_SWITCH_GATE) {
1988 switch (type) {
1989 case SVM_EXITINTINFO_TYPE_NMI:
1990 svm->vcpu.arch.nmi_injected = false;
1991 break;
1992 case SVM_EXITINTINFO_TYPE_EXEPT:
1993 kvm_clear_exception_queue(&svm->vcpu);
1994 break;
1995 case SVM_EXITINTINFO_TYPE_INTR:
1996 kvm_clear_interrupt_queue(&svm->vcpu);
1997 break;
1998 default:
1999 break;
2000 }
2001 }
64a7ec06 2002
8317c298
GN		 2003 if (reason != TASK_SWITCH_GATE ||
2004 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2005 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2006 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2007 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2008
2009 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2010}
2011
e756fc62 2012static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2013{
5fdbf976 2014 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2015 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2016 return 1;
6aa8b732
AK		 2017}
2018
95ba8273
GN		 2019static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2020{
2021 ++svm->vcpu.stat.nmi_window_exits;
2022 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2023 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2024 return 1;
2025}
2026
a7052897
MT		 2027static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2028{
2029 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2030 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2031 return 1;
2032}
2033
e756fc62
RR		 2034static int emulate_on_interception(struct vcpu_svm *svm,
2035 struct kvm_run *kvm_run)
6aa8b732 2036{
3427318f 2037 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 2038 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2039 return 1;
2040}
2041
1d075434
JR		 2042static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2043{
0a5fff19
GN		 2044 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2045 /* instruction emulation calls kvm_set_cr8() */
1d075434 2046 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 2047 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2048 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2049 return 1;
95ba8273 2050 }
0a5fff19
GN		 2051 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2052 return 1;
1d075434
JR		 2053 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2054 return 0;
2055}
2056
6aa8b732
AK		 2057static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2058{
a2fa3e9f
GH		 2059 struct vcpu_svm *svm = to_svm(vcpu);
2060
6aa8b732 2061 switch (ecx) {
af24a4e4 2062 case MSR_IA32_TSC: {
6aa8b732
AK		 2063 u64 tsc;
2064
2065 rdtscll(tsc);
a2fa3e9f 2066 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2067 break;
2068 }
0e859cac 2069 case MSR_K6_STAR:
a2fa3e9f 2070 *data = svm->vmcb->save.star;
6aa8b732 2071 break;
0e859cac 2072#ifdef CONFIG_X86_64
6aa8b732 2073 case MSR_LSTAR:
a2fa3e9f 2074 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2075 break;
2076 case MSR_CSTAR:
a2fa3e9f 2077 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2078 break;
2079 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2080 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2081 break;
2082 case MSR_SYSCALL_MASK:
a2fa3e9f 2083 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2084 break;
2085#endif
2086 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2087 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2088 break;
2089 case MSR_IA32_SYSENTER_EIP:
017cb99e 2090 *data = svm->sysenter_eip;
6aa8b732
AK		 2091 break;
2092 case MSR_IA32_SYSENTER_ESP:
017cb99e 2093 *data = svm->sysenter_esp;
6aa8b732 2094 break;
a2938c80
JR		 2095 /* Nobody will change the following 5 values in the VMCB so
2096 we can safely return them on rdmsr. They will always be 0
2097 until LBRV is implemented. */
2098 case MSR_IA32_DEBUGCTLMSR:
2099 *data = svm->vmcb->save.dbgctl;
2100 break;
2101 case MSR_IA32_LASTBRANCHFROMIP:
2102 *data = svm->vmcb->save.br_from;
2103 break;
2104 case MSR_IA32_LASTBRANCHTOIP:
2105 *data = svm->vmcb->save.br_to;
2106 break;
2107 case MSR_IA32_LASTINTFROMIP:
2108 *data = svm->vmcb->save.last_excp_from;
2109 break;
2110 case MSR_IA32_LASTINTTOIP:
2111 *data = svm->vmcb->save.last_excp_to;
2112 break;
b286d5d8 2113 case MSR_VM_HSAVE_PA:
e6aa9abd 2114 *data = svm->nested.hsave_msr;
b286d5d8 2115 break;
eb6f302e
JR		 2116 case MSR_VM_CR:
2117 *data = 0;
2118 break;
c8a73f18
AG		 2119 case MSR_IA32_UCODE_REV:
2120 *data = 0x01000065;
2121 break;
6aa8b732 2122 default:
3bab1f5d 2123 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2124 }
2125 return 0;
2126}
2127
e756fc62 2128static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2129{
ad312c7c 2130 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2131 u64 data;
2132
e756fc62 2133 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2134 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2135 else {
229456fc 2136 trace_kvm_msr_read(ecx, data);
af9ca2d7 2137
5fdbf976 2138 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2139 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2140 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2141 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2142 }
2143 return 1;
2144}
2145
2146static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2147{
a2fa3e9f
GH		 2148 struct vcpu_svm *svm = to_svm(vcpu);
2149
6aa8b732 2150 switch (ecx) {
af24a4e4 2151 case MSR_IA32_TSC: {
6aa8b732
AK		 2152 u64 tsc;
2153
2154 rdtscll(tsc);
a2fa3e9f 2155 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2156 break;
2157 }
0e859cac 2158 case MSR_K6_STAR:
a2fa3e9f 2159 svm->vmcb->save.star = data;
6aa8b732 2160 break;
49b14f24 2161#ifdef CONFIG_X86_64
6aa8b732 2162 case MSR_LSTAR:
a2fa3e9f 2163 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2164 break;
2165 case MSR_CSTAR:
a2fa3e9f 2166 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2167 break;
2168 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2169 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2170 break;
2171 case MSR_SYSCALL_MASK:
a2fa3e9f 2172 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2173 break;
2174#endif
2175 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2176 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2177 break;
2178 case MSR_IA32_SYSENTER_EIP:
017cb99e 2179 svm->sysenter_eip = data;
a2fa3e9f 2180 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2181 break;
2182 case MSR_IA32_SYSENTER_ESP:
017cb99e 2183 svm->sysenter_esp = data;
a2fa3e9f 2184 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2185 break;
a2938c80 2186 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2187 if (!svm_has(SVM_FEATURE_LBRV)) {
2188 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2189 __func__, data);
24e09cbf
JR		 2190 break;
2191 }
2192 if (data & DEBUGCTL_RESERVED_BITS)
2193 return 1;
2194
2195 svm->vmcb->save.dbgctl = data;
2196 if (data & (1ULL<<0))
2197 svm_enable_lbrv(svm);
2198 else
2199 svm_disable_lbrv(svm);
a2938c80 2200 break;
b286d5d8 2201 case MSR_VM_HSAVE_PA:
e6aa9abd 2202 svm->nested.hsave_msr = data;
62b9abaa 2203 break;
3c5d0a44
AG		 2204 case MSR_VM_CR:
2205 case MSR_VM_IGNNE:
3c5d0a44
AG		 2206 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2207 break;
6aa8b732 2208 default:
3bab1f5d 2209 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2210 }
2211 return 0;
2212}
2213
e756fc62 2214static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2215{
ad312c7c 2216 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2217 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2218 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2219
229456fc 2220 trace_kvm_msr_write(ecx, data);
af9ca2d7 2221
5fdbf976 2222 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2223 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2224 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2225 else
e756fc62 2226 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2227 return 1;
2228}
2229
e756fc62 2230static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2231{
e756fc62
RR		 2232 if (svm->vmcb->control.exit_info_1)
2233 return wrmsr_interception(svm, kvm_run);
6aa8b732 2234 else
e756fc62 2235 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2236}
2237
e756fc62 2238static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2239 struct kvm_run *kvm_run)
2240{
f0b85051 2241 svm_clear_vintr(svm);
85f455f7 2242 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2243 /*
2244 * If the user space waits to inject interrupts, exit as soon as
2245 * possible
2246 */
8061823a
GN		 2247 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2248 kvm_run->request_interrupt_window &&
2249 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2250 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2251 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2252 return 0;
2253 }
2254
2255 return 1;
2256}
2257
e756fc62 2258static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2259 struct kvm_run *kvm_run) = {
2260 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2261 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2262 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2263 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2264 /* for now: */
2265 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2266 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2267 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2268 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2269 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2270 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2271 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2272 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2273 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2274 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2275 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2276 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2277 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2278 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2279 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2280 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2281 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2282 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2283 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2284 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2285 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2286 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2287 [SVM_EXIT_SMI] = nop_on_interception,
2288 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2289 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2290 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2291 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2292 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2293 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2294 [SVM_EXIT_HLT] = halt_interception,
a7052897 2295 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2296 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2297 [SVM_EXIT_IOIO] = io_interception,
2298 [SVM_EXIT_MSR] = msr_interception,
2299 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2300 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2301 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2302 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2303 [SVM_EXIT_VMLOAD] = vmload_interception,
2304 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2305 [SVM_EXIT_STGI] = stgi_interception,
2306 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2307 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2308 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2309 [SVM_EXIT_MONITOR] = invalid_op_interception,
2310 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2311 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2312};
2313
04d2cc77 2314static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2315{
04d2cc77 2316 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2317 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2318
229456fc 2319 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2320
cf74a78b
AG		 2321 if (is_nested(svm)) {
2322 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2323 exit_code, svm->vmcb->control.exit_info_1,
2324 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2325 if (nested_svm_exit_handled(svm, true)) {
2326 nested_svm_vmexit(svm);
2327 nsvm_printk("-> #VMEXIT\n");
2328 return 1;
2329 }
2330 }
2331
a5c3832d
JR		 2332 svm_complete_interrupts(svm);
2333
709ddebf
JR		 2334 if (npt_enabled) {
2335 int mmu_reload = 0;
2336 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2337 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2338 mmu_reload = 1;
2339 }
2340 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2341 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2342 if (mmu_reload) {
2343 kvm_mmu_reset_context(vcpu);
2344 kvm_mmu_load(vcpu);
2345 }
2346 }
2347
04d2cc77
AK		 2348
2349 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2350 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2351 kvm_run->fail_entry.hardware_entry_failure_reason
2352 = svm->vmcb->control.exit_code;
2353 return 0;
2354 }
2355
a2fa3e9f 2356 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2357 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2358 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2359 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2360 "exit_code 0x%x\n",
b8688d51 2361 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2362 exit_code);
2363
9d8f549d 2364 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2365 || !svm_exit_handlers[exit_code]) {
6aa8b732 2366 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2367 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2368 return 0;
2369 }
2370
e756fc62 2371 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2372}
2373
2374static void reload_tss(struct kvm_vcpu *vcpu)
2375{
2376 int cpu = raw_smp_processor_id();
2377
2378 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2379 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2380 load_TR_desc();
2381}
2382
e756fc62 2383static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2384{
2385 int cpu = raw_smp_processor_id();
2386
2387 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2388
a2fa3e9f 2389 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2390 /* FIXME: handle wraparound of asid_generation */
2391 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2392 new_asid(svm, svm_data);
6aa8b732
AK		 2393}
2394
95ba8273
GN		 2395static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2396{
2397 struct vcpu_svm *svm = to_svm(vcpu);
2398
2399 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2400 vcpu->arch.hflags |= HF_NMI_MASK;
2401 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2402 ++vcpu->stat.nmi_injections;
2403}
6aa8b732 2404
85f455f7 2405static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2406{
2407 struct vmcb_control_area *control;
2408
229456fc 2409 trace_kvm_inj_virq(irq);
af9ca2d7 2410
fa89a817 2411 ++svm->vcpu.stat.irq_injections;
e756fc62 2412 control = &svm->vmcb->control;
85f455f7 2413 control->int_vector = irq;
6aa8b732
AK		 2414 control->int_ctl &= ~V_INTR_PRIO_MASK;
2415 control->int_ctl |= V_IRQ_MASK |
2416 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2417}
2418
66fd3f7f 2419static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2420{
2421 struct vcpu_svm *svm = to_svm(vcpu);
2422
2af9194d 2423 BUG_ON(!(gif_set(svm)));
cf74a78b 2424
219b65dc
AG		 2425 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2426 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2427}
2428
95ba8273 2429static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2430{
2431 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2432
95ba8273 2433 if (irr == -1)
aaacfc9a
JR		 2434 return;
2435
95ba8273
GN		 2436 if (tpr >= irr)
2437 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2438}
aaacfc9a 2439
95ba8273
GN		 2440static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2441{
2442 struct vcpu_svm *svm = to_svm(vcpu);
2443 struct vmcb *vmcb = svm->vmcb;
2444 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2445 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2446}
2447
78646121
GN		 2448static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2449{
2450 struct vcpu_svm *svm = to_svm(vcpu);
2451 struct vmcb *vmcb = svm->vmcb;
2452 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2453 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2454 gif_set(svm) &&
219b65dc 2455 !is_nested(svm);
78646121
GN		 2456}
2457
9222be18 2458static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2459{
219b65dc
AG		 2460 struct vcpu_svm *svm = to_svm(vcpu);
2461 nsvm_printk("Trying to open IRQ window\n");
2462
2463 nested_svm_intr(svm);
2464
2465 /* In case GIF=0 we can't rely on the CPU to tell us when
2466 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2467 * The next time we get that intercept, this function will be
2468 * called again though and we'll get the vintr intercept. */
2af9194d 2469 if (gif_set(svm)) {
219b65dc
AG		 2470 svm_set_vintr(svm);
2471 svm_inject_irq(svm, 0x0);
2472 }
85f455f7
ED		 2473}
2474
95ba8273 2475static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2476{
04d2cc77 2477 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2478
44c11430
GN		 2479 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2480 == HF_NMI_MASK)
2481 return; /* IRET will cause a vm exit */
2482
2483 /* Something prevents NMI from been injected. Single step over
2484 possible problem (IRET or exception injection or interrupt
2485 shadow) */
2486 vcpu->arch.singlestep = true;
2487 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2488 update_db_intercept(vcpu);
c1150d8c
DL		 2489}
2490
cbc94022
IE		 2491static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2492{
2493 return 0;
2494}
2495
d9e368d6
AK		 2496static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2497{
2498 force_new_asid(vcpu);
2499}
2500
04d2cc77
AK		 2501static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2502{
2503}
2504
d7bf8221
JR		 2505static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2506{
2507 struct vcpu_svm *svm = to_svm(vcpu);
2508
2509 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2510 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2511 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2512 }
2513}
2514
649d6864
JR		 2515static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2516{
2517 struct vcpu_svm *svm = to_svm(vcpu);
2518 u64 cr8;
2519
649d6864
JR		 2520 cr8 = kvm_get_cr8(vcpu);
2521 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2522 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2523}
2524
9222be18
GN		 2525static void svm_complete_interrupts(struct vcpu_svm *svm)
2526{
2527 u8 vector;
2528 int type;
2529 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2530
44c11430
GN		 2531 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2532 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2533
9222be18
GN		 2534 svm->vcpu.arch.nmi_injected = false;
2535 kvm_clear_exception_queue(&svm->vcpu);
2536 kvm_clear_interrupt_queue(&svm->vcpu);
2537
2538 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2539 return;
2540
2541 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2542 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2543
2544 switch (type) {
2545 case SVM_EXITINTINFO_TYPE_NMI:
2546 svm->vcpu.arch.nmi_injected = true;
2547 break;
2548 case SVM_EXITINTINFO_TYPE_EXEPT:
2549 /* In case of software exception do not reinject an exception
2550 vector, but re-execute and instruction instead */
219b65dc
AG		 2551 if (is_nested(svm))
2552 break;
66fd3f7f 2553 if (kvm_exception_is_soft(vector))
9222be18
GN		 2554 break;
2555 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2556 u32 err = svm->vmcb->control.exit_int_info_err;
2557 kvm_queue_exception_e(&svm->vcpu, vector, err);
2558
2559 } else
2560 kvm_queue_exception(&svm->vcpu, vector);
2561 break;
2562 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2563 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2564 break;
2565 default:
2566 break;
2567 }
2568}
2569
80e31d4f
AK		 2570#ifdef CONFIG_X86_64
2571#define R "r"
2572#else
2573#define R "e"
2574#endif
2575
04d2cc77 2576static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2577{
a2fa3e9f 2578 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2579 u16 fs_selector;
2580 u16 gs_selector;
2581 u16 ldt_selector;
d9e368d6 2582
5fdbf976
MT		 2583 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2584 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2585 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2586
e756fc62 2587 pre_svm_run(svm);
6aa8b732 2588
649d6864
JR		 2589 sync_lapic_to_cr8(vcpu);
2590
6aa8b732 2591 save_host_msrs(vcpu);
d6e88aec
AK		 2592 fs_selector = kvm_read_fs();
2593 gs_selector = kvm_read_gs();
2594 ldt_selector = kvm_read_ldt();
3d6368ef
AG		 2595 if (!is_nested(svm))
2596 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2597 /* required for live migration with NPT */
2598 if (npt_enabled)
2599 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2600
04d2cc77
AK		 2601 clgi();
2602
2603 local_irq_enable();
36241b8c 2604
6aa8b732 2605 asm volatile (
80e31d4f
AK		 2606 "push %%"R"bp; \n\t"
2607 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2608 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2609 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2610 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2611 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2612 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2613#ifdef CONFIG_X86_64
fb3f0f51
RR		 2614 "mov %c[r8](%[svm]), %%r8 \n\t"
2615 "mov %c[r9](%[svm]), %%r9 \n\t"
2616 "mov %c[r10](%[svm]), %%r10 \n\t"
2617 "mov %c[r11](%[svm]), %%r11 \n\t"
2618 "mov %c[r12](%[svm]), %%r12 \n\t"
2619 "mov %c[r13](%[svm]), %%r13 \n\t"
2620 "mov %c[r14](%[svm]), %%r14 \n\t"
2621 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2622#endif
2623
6aa8b732 2624 /* Enter guest mode */
80e31d4f
AK		 2625 "push %%"R"ax \n\t"
2626 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2627 __ex(SVM_VMLOAD) "\n\t"
2628 __ex(SVM_VMRUN) "\n\t"
2629 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2630 "pop %%"R"ax \n\t"
6aa8b732
AK		 2631
2632 /* Save guest registers, load host registers */
80e31d4f
AK		 2633 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2634 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2635 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2636 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2637 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2638 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2639#ifdef CONFIG_X86_64
fb3f0f51
RR		 2640 "mov %%r8, %c[r8](%[svm]) \n\t"
2641 "mov %%r9, %c[r9](%[svm]) \n\t"
2642 "mov %%r10, %c[r10](%[svm]) \n\t"
2643 "mov %%r11, %c[r11](%[svm]) \n\t"
2644 "mov %%r12, %c[r12](%[svm]) \n\t"
2645 "mov %%r13, %c[r13](%[svm]) \n\t"
2646 "mov %%r14, %c[r14](%[svm]) \n\t"
2647 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2648#endif
80e31d4f 2649 "pop %%"R"bp"
6aa8b732 2650 :
fb3f0f51 2651 : [svm]"a"(svm),
6aa8b732 2652 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2653 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2654 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2655 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2656 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2657 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2658 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2659#ifdef CONFIG_X86_64
ad312c7c
ZX		 2660 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2661 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2662 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2663 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2664 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2665 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2666 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2667 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2668#endif
54a08c04 2669 : "cc", "memory"
80e31d4f 2670 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2671#ifdef CONFIG_X86_64
54a08c04
LV		 2672 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2673#endif
2674 );
6aa8b732 2675
ad312c7c 2676 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2677 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2678 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2679 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2680
d6e88aec
AK		 2681 kvm_load_fs(fs_selector);
2682 kvm_load_gs(gs_selector);
2683 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2684 load_host_msrs(vcpu);
2685
2686 reload_tss(vcpu);
2687
56ba47dd
AK		 2688 local_irq_disable();
2689
2690 stgi();
2691
d7bf8221
JR		 2692 sync_cr8_to_lapic(vcpu);
2693
a2fa3e9f 2694 svm->next_rip = 0;
9222be18 2695
6de4f3ad
AK		 2696 if (npt_enabled) {
2697 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2698 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2699 }
6aa8b732
AK		 2700}
2701
80e31d4f
AK		 2702#undef R
2703
6aa8b732
AK		 2704static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2705{
a2fa3e9f
GH		 2706 struct vcpu_svm *svm = to_svm(vcpu);
2707
709ddebf
JR		 2708 if (npt_enabled) {
2709 svm->vmcb->control.nested_cr3 = root;
2710 force_new_asid(vcpu);
2711 return;
2712 }
2713
a2fa3e9f 2714 svm->vmcb->save.cr3 = root;
6aa8b732 2715 force_new_asid(vcpu);
7807fa6c
AL		 2716
2717 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2718 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2719 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2720 vcpu->fpu_active = 0;
2721 }
6aa8b732
AK		 2722}
2723
6aa8b732
AK		 2724static int is_disabled(void)
2725{
6031a61c
JR		 2726 u64 vm_cr;
2727
2728 rdmsrl(MSR_VM_CR, vm_cr);
2729 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2730 return 1;
2731
6aa8b732
AK		 2732 return 0;
2733}
2734
102d8325
IM		 2735static void
2736svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2737{
2738 /*
2739 * Patch in the VMMCALL instruction:
2740 */
2741 hypercall[0] = 0x0f;
2742 hypercall[1] = 0x01;
2743 hypercall[2] = 0xd9;
102d8325
IM		 2744}
2745
002c7f7c
YS		 2746static void svm_check_processor_compat(void *rtn)
2747{
2748 *(int *)rtn = 0;
2749}
2750
774ead3a
AK		 2751static bool svm_cpu_has_accelerated_tpr(void)
2752{
2753 return false;
2754}
2755
67253af5
SY		 2756static int get_npt_level(void)
2757{
2758#ifdef CONFIG_X86_64
2759 return PT64_ROOT_LEVEL;
2760#else
2761 return PT32E_ROOT_LEVEL;
2762#endif
2763}
2764
4b12f0de 2765static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2766{
2767 return 0;
2768}
2769
229456fc
MT		 2770static const struct trace_print_flags svm_exit_reasons_str[] = {
2771 { SVM_EXIT_READ_CR0, "read_cr0" },
2772 { SVM_EXIT_READ_CR3, "read_cr3" },
2773 { SVM_EXIT_READ_CR4, "read_cr4" },
2774 { SVM_EXIT_READ_CR8, "read_cr8" },
2775 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2776 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2777 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2778 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2779 { SVM_EXIT_READ_DR0, "read_dr0" },
2780 { SVM_EXIT_READ_DR1, "read_dr1" },
2781 { SVM_EXIT_READ_DR2, "read_dr2" },
2782 { SVM_EXIT_READ_DR3, "read_dr3" },
2783 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2784 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2785 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2786 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2787 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2788 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2789 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2790 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2791 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2792 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2793 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2794 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2795 { SVM_EXIT_INTR, "interrupt" },
2796 { SVM_EXIT_NMI, "nmi" },
2797 { SVM_EXIT_SMI, "smi" },
2798 { SVM_EXIT_INIT, "init" },
2799 { SVM_EXIT_VINTR, "vintr" },
2800 { SVM_EXIT_CPUID, "cpuid" },
2801 { SVM_EXIT_INVD, "invd" },
2802 { SVM_EXIT_HLT, "hlt" },
2803 { SVM_EXIT_INVLPG, "invlpg" },
2804 { SVM_EXIT_INVLPGA, "invlpga" },
2805 { SVM_EXIT_IOIO, "io" },
2806 { SVM_EXIT_MSR, "msr" },
2807 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2808 { SVM_EXIT_SHUTDOWN, "shutdown" },
2809 { SVM_EXIT_VMRUN, "vmrun" },
2810 { SVM_EXIT_VMMCALL, "hypercall" },
2811 { SVM_EXIT_VMLOAD, "vmload" },
2812 { SVM_EXIT_VMSAVE, "vmsave" },
2813 { SVM_EXIT_STGI, "stgi" },
2814 { SVM_EXIT_CLGI, "clgi" },
2815 { SVM_EXIT_SKINIT, "skinit" },
2816 { SVM_EXIT_WBINVD, "wbinvd" },
2817 { SVM_EXIT_MONITOR, "monitor" },
2818 { SVM_EXIT_MWAIT, "mwait" },
2819 { SVM_EXIT_NPF, "npf" },
2820 { -1, NULL }
2821};
2822
344f414f
JR		 2823static bool svm_gb_page_enable(void)
2824{
2825 return true;
2826}
2827
cbdd1bea 2828static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2829 .cpu_has_kvm_support = has_svm,
2830 .disabled_by_bios = is_disabled,
2831 .hardware_setup = svm_hardware_setup,
2832 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2833 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2834 .hardware_enable = svm_hardware_enable,
2835 .hardware_disable = svm_hardware_disable,
774ead3a 2836 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2837
2838 .vcpu_create = svm_create_vcpu,
2839 .vcpu_free = svm_free_vcpu,
04d2cc77 2840 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2841
04d2cc77 2842 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2843 .vcpu_load = svm_vcpu_load,
2844 .vcpu_put = svm_vcpu_put,
2845
2846 .set_guest_debug = svm_guest_debug,
2847 .get_msr = svm_get_msr,
2848 .set_msr = svm_set_msr,
2849 .get_segment_base = svm_get_segment_base,
2850 .get_segment = svm_get_segment,
2851 .set_segment = svm_set_segment,
2e4d2653 2852 .get_cpl = svm_get_cpl,
1747fb71 2853 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2854 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2855 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2856 .set_cr3 = svm_set_cr3,
2857 .set_cr4 = svm_set_cr4,
2858 .set_efer = svm_set_efer,
2859 .get_idt = svm_get_idt,
2860 .set_idt = svm_set_idt,
2861 .get_gdt = svm_get_gdt,
2862 .set_gdt = svm_set_gdt,
2863 .get_dr = svm_get_dr,
2864 .set_dr = svm_set_dr,
6de4f3ad 2865 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2866 .get_rflags = svm_get_rflags,
2867 .set_rflags = svm_set_rflags,
2868
6aa8b732 2869 .tlb_flush = svm_flush_tlb,
6aa8b732 2870
6aa8b732 2871 .run = svm_vcpu_run,
04d2cc77 2872 .handle_exit = handle_exit,
6aa8b732 2873 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2874 .set_interrupt_shadow = svm_set_interrupt_shadow,
2875 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2876 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2877 .set_irq = svm_set_irq,
95ba8273 2878 .set_nmi = svm_inject_nmi,
298101da 2879 .queue_exception = svm_queue_exception,
78646121 2880 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2881 .nmi_allowed = svm_nmi_allowed,
2882 .enable_nmi_window = enable_nmi_window,
2883 .enable_irq_window = enable_irq_window,
2884 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2885
2886 .set_tss_addr = svm_set_tss_addr,
67253af5 2887 .get_tdp_level = get_npt_level,
4b12f0de 2888 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2889
2890 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2891 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2892};
2893
2894static int __init svm_init(void)
2895{
cb498ea2 2896 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2897 THIS_MODULE);
6aa8b732
AK		 2898}
2899
2900static void __exit svm_exit(void)
2901{
cb498ea2 2902 kvm_exit();
6aa8b732
AK		 2903}
2904
2905module_init(svm_init)
2906module_exit(svm_exit)
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