]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/svm.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Report IRQ injection status to userspace.
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
e495606d 18#include "kvm_svm.h"
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
6aa8b732 28
e495606d 29#include <asm/desc.h>
6aa8b732 30
63d1142f
EH		 31#include <asm/virtext.h>
32
4ecac3fd
AK		 33#define __ex(x) __kvm_handle_fault_on_reboot(x)
34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
38#define IOPM_ALLOC_ORDER 2
39#define MSRPM_ALLOC_ORDER 1
40
6aa8b732
AK		 41#define SEG_TYPE_LDT 2
42#define SEG_TYPE_BUSY_TSS16 3
43
80b7706e
JR		 44#define SVM_FEATURE_NPT (1 << 0)
45#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 46#define SVM_FEATURE_SVML (1 << 2)
80b7706e 47
24e09cbf
JR		 48#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
49
c0725420
AG		 50/* Turn on to get debugging output*/
51/* #define NESTED_DEBUG */
52
53#ifdef NESTED_DEBUG
54#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
55#else
56#define nsvm_printk(fmt, args...) do {} while(0)
57#endif
58
709ddebf
JR		 59/* enable NPT for AMD64 and X86 with PAE */
60#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
61static bool npt_enabled = true;
62#else
e3da3acd 63static bool npt_enabled = false;
709ddebf 64#endif
6c7dac72
JR		 65static int npt = 1;
66
67module_param(npt, int, S_IRUGO);
e3da3acd 68
236de055
AG		 69static int nested = 0;
70module_param(nested, int, S_IRUGO);
71
04d2cc77 72static void kvm_reput_irq(struct vcpu_svm *svm);
44874f84 73static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 74
cf74a78b
AG		 75static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
76static int nested_svm_vmexit(struct vcpu_svm *svm);
77static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
78 void *arg2, void *opaque);
79static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
80 bool has_error_code, u32 error_code);
81
a2fa3e9f
GH		 82static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
83{
fb3f0f51 84 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 85}
86
3d6368ef
AG		 87static inline bool is_nested(struct vcpu_svm *svm)
88{
89 return svm->nested_vmcb;
90}
91
4866d5e3 92static unsigned long iopm_base;
6aa8b732
AK		 93
94struct kvm_ldttss_desc {
95 u16 limit0;
96 u16 base0;
97 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
98 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
99 u32 base3;
100 u32 zero1;
101} __attribute__((packed));
102
103struct svm_cpu_data {
104 int cpu;
105
5008fdf5
AK		 106 u64 asid_generation;
107 u32 max_asid;
108 u32 next_asid;
6aa8b732
AK		 109 struct kvm_ldttss_desc *tss_desc;
110
111 struct page *save_area;
112};
113
114static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 115static uint32_t svm_features;
6aa8b732
AK		 116
117struct svm_init_data {
118 int cpu;
119 int r;
120};
121
122static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
123
9d8f549d 124#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 125#define MSRS_RANGE_SIZE 2048
126#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
127
128#define MAX_INST_SIZE 15
129
80b7706e
JR		 130static inline u32 svm_has(u32 feat)
131{
132 return svm_features & feat;
133}
134
6aa8b732
AK		 135static inline u8 pop_irq(struct kvm_vcpu *vcpu)
136{
ad312c7c
ZX		 137 int word_index = __ffs(vcpu->arch.irq_summary);
138 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 139 int irq = word_index * BITS_PER_LONG + bit_index;
140
ad312c7c
ZX		 141 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
142 if (!vcpu->arch.irq_pending[word_index])
143 clear_bit(word_index, &vcpu->arch.irq_summary);
6aa8b732
AK		 144 return irq;
145}
146
147static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
148{
ad312c7c
ZX		 149 set_bit(irq, vcpu->arch.irq_pending);
150 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 151}
152
153static inline void clgi(void)
154{
4ecac3fd 155 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 156}
157
158static inline void stgi(void)
159{
4ecac3fd 160 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 161}
162
163static inline void invlpga(unsigned long addr, u32 asid)
164{
4ecac3fd 165 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 166}
167
168static inline unsigned long kvm_read_cr2(void)
169{
170 unsigned long cr2;
171
172 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
173 return cr2;
174}
175
176static inline void kvm_write_cr2(unsigned long val)
177{
178 asm volatile ("mov %0, %%cr2" :: "r" (val));
179}
180
6aa8b732
AK		 181static inline void force_new_asid(struct kvm_vcpu *vcpu)
182{
a2fa3e9f 183 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 184}
185
186static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
187{
188 force_new_asid(vcpu);
189}
190
191static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
192{
709ddebf 193 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 194 efer &= ~EFER_LME;
6aa8b732 195
9962d032 196 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 197 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 198}
199
298101da
AK		 200static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
201 bool has_error_code, u32 error_code)
202{
203 struct vcpu_svm *svm = to_svm(vcpu);
204
cf74a78b
AG		 205 /* If we are within a nested VM we'd better #VMEXIT and let the
206 guest handle the exception */
207 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
208 return;
209
298101da
AK		 210 svm->vmcb->control.event_inj = nr
211 | SVM_EVTINJ_VALID
212 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
213 | SVM_EVTINJ_TYPE_EXEPT;
214 svm->vmcb->control.event_inj_err = error_code;
215}
216
217static bool svm_exception_injected(struct kvm_vcpu *vcpu)
218{
219 struct vcpu_svm *svm = to_svm(vcpu);
220
221 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
222}
223
6aa8b732
AK		 224static int is_external_interrupt(u32 info)
225{
226 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
227 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
228}
229
230static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
231{
a2fa3e9f
GH		 232 struct vcpu_svm *svm = to_svm(vcpu);
233
234 if (!svm->next_rip) {
b8688d51 235 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 236 return;
237 }
5fdbf976
MT		 238 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
239 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
240 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 241
5fdbf976 242 kvm_rip_write(vcpu, svm->next_rip);
a2fa3e9f 243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c 244
1371d904 245 vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
6aa8b732
AK		 246}
247
248static int has_svm(void)
249{
63d1142f 250 const char *msg;
6aa8b732 251
63d1142f 252 if (!cpu_has_svm(&msg)) {
ff81ff10 253 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 254 return 0;
255 }
256
6aa8b732
AK		 257 return 1;
258}
259
260static void svm_hardware_disable(void *garbage)
261{
2c8dceeb 262 cpu_svm_disable();
6aa8b732
AK		 263}
264
265static void svm_hardware_enable(void *garbage)
266{
267
268 struct svm_cpu_data *svm_data;
269 uint64_t efer;
6aa8b732 270 struct desc_ptr gdt_descr;
6aa8b732
AK		 271 struct desc_struct *gdt;
272 int me = raw_smp_processor_id();
273
274 if (!has_svm()) {
275 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
276 return;
277 }
278 svm_data = per_cpu(svm_data, me);
279
280 if (!svm_data) {
281 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
282 me);
283 return;
284 }
285
286 svm_data->asid_generation = 1;
287 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
288 svm_data->next_asid = svm_data->max_asid + 1;
289
d77c26fc 290 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 291 gdt = (struct desc_struct *)gdt_descr.address;
292 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
293
294 rdmsrl(MSR_EFER, efer);
9962d032 295 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 296
297 wrmsrl(MSR_VM_HSAVE_PA,
298 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
299}
300
0da1db75
JR		 301static void svm_cpu_uninit(int cpu)
302{
303 struct svm_cpu_data *svm_data
304 = per_cpu(svm_data, raw_smp_processor_id());
305
306 if (!svm_data)
307 return;
308
309 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
310 __free_page(svm_data->save_area);
311 kfree(svm_data);
312}
313
6aa8b732
AK		 314static int svm_cpu_init(int cpu)
315{
316 struct svm_cpu_data *svm_data;
317 int r;
318
319 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
320 if (!svm_data)
321 return -ENOMEM;
322 svm_data->cpu = cpu;
323 svm_data->save_area = alloc_page(GFP_KERNEL);
324 r = -ENOMEM;
325 if (!svm_data->save_area)
326 goto err_1;
327
328 per_cpu(svm_data, cpu) = svm_data;
329
330 return 0;
331
332err_1:
333 kfree(svm_data);
334 return r;
335
336}
337
bfc733a7
RR		 338static void set_msr_interception(u32 *msrpm, unsigned msr,
339 int read, int write)
6aa8b732
AK		 340{
341 int i;
342
343 for (i = 0; i < NUM_MSR_MAPS; i++) {
344 if (msr >= msrpm_ranges[i] &&
345 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
346 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
347 msrpm_ranges[i]) * 2;
348
349 u32 *base = msrpm + (msr_offset / 32);
350 u32 msr_shift = msr_offset % 32;
351 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
352 *base = (*base & ~(0x3 << msr_shift)) |
353 (mask << msr_shift);
bfc733a7 354 return;
6aa8b732
AK		 355 }
356 }
bfc733a7 357 BUG();
6aa8b732
AK		 358}
359
f65c229c
JR		 360static void svm_vcpu_init_msrpm(u32 *msrpm)
361{
362 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
363
364#ifdef CONFIG_X86_64
365 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
366 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
367 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
368 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
369 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
370 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
371#endif
372 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
373 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
374 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
375 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
376}
377
24e09cbf
JR		 378static void svm_enable_lbrv(struct vcpu_svm *svm)
379{
380 u32 *msrpm = svm->msrpm;
381
382 svm->vmcb->control.lbr_ctl = 1;
383 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
384 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
386 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
387}
388
389static void svm_disable_lbrv(struct vcpu_svm *svm)
390{
391 u32 *msrpm = svm->msrpm;
392
393 svm->vmcb->control.lbr_ctl = 0;
394 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
395 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
396 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
397 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
398}
399
6aa8b732
AK		 400static __init int svm_hardware_setup(void)
401{
402 int cpu;
403 struct page *iopm_pages;
f65c229c 404 void *iopm_va;
6aa8b732
AK		 405 int r;
406
6aa8b732
AK		 407 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
408
409 if (!iopm_pages)
410 return -ENOMEM;
c8681339
AL		 411
412 iopm_va = page_address(iopm_pages);
413 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
414 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
6aa8b732
AK		 415 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
416
50a37eb4
JR		 417 if (boot_cpu_has(X86_FEATURE_NX))
418 kvm_enable_efer_bits(EFER_NX);
419
1b2fd70c
AG		 420 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
421 kvm_enable_efer_bits(EFER_FFXSR);
422
236de055
AG		 423 if (nested) {
424 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
425 kvm_enable_efer_bits(EFER_SVME);
426 }
427
6aa8b732
AK		 428 for_each_online_cpu(cpu) {
429 r = svm_cpu_init(cpu);
430 if (r)
f65c229c 431 goto err;
6aa8b732 432 }
33bd6a0b
JR		 433
434 svm_features = cpuid_edx(SVM_CPUID_FUNC);
435
e3da3acd
JR		 436 if (!svm_has(SVM_FEATURE_NPT))
437 npt_enabled = false;
438
6c7dac72
JR		 439 if (npt_enabled && !npt) {
440 printk(KERN_INFO "kvm: Nested Paging disabled\n");
441 npt_enabled = false;
442 }
443
18552672 444 if (npt_enabled) {
e3da3acd 445 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 446 kvm_enable_tdp();
5f4cb662
JR		 447 } else
448 kvm_disable_tdp();
e3da3acd 449
6aa8b732
AK		 450 return 0;
451
f65c229c 452err:
6aa8b732
AK		 453 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
454 iopm_base = 0;
455 return r;
456}
457
458static __exit void svm_hardware_unsetup(void)
459{
0da1db75
JR		 460 int cpu;
461
462 for_each_online_cpu(cpu)
463 svm_cpu_uninit(cpu);
464
6aa8b732 465 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 466 iopm_base = 0;
6aa8b732
AK		 467}
468
469static void init_seg(struct vmcb_seg *seg)
470{
471 seg->selector = 0;
472 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
473 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
474 seg->limit = 0xffff;
475 seg->base = 0;
476}
477
478static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
479{
480 seg->selector = 0;
481 seg->attrib = SVM_SELECTOR_P_MASK | type;
482 seg->limit = 0xffff;
483 seg->base = 0;
484}
485
e6101a96 486static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 487{
e6101a96
JR		 488 struct vmcb_control_area *control = &svm->vmcb->control;
489 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 490
491 control->intercept_cr_read = INTERCEPT_CR0_MASK |
492 INTERCEPT_CR3_MASK |
649d6864 493 INTERCEPT_CR4_MASK;
6aa8b732
AK		 494
495 control->intercept_cr_write = INTERCEPT_CR0_MASK |
496 INTERCEPT_CR3_MASK |
80a8119c
AK		 497 INTERCEPT_CR4_MASK |
498 INTERCEPT_CR8_MASK;
6aa8b732
AK		 499
500 control->intercept_dr_read = INTERCEPT_DR0_MASK |
501 INTERCEPT_DR1_MASK |
502 INTERCEPT_DR2_MASK |
503 INTERCEPT_DR3_MASK;
504
505 control->intercept_dr_write = INTERCEPT_DR0_MASK |
506 INTERCEPT_DR1_MASK |
507 INTERCEPT_DR2_MASK |
508 INTERCEPT_DR3_MASK |
509 INTERCEPT_DR5_MASK |
510 INTERCEPT_DR7_MASK;
511
7aa81cc0 512 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 513 (1 << UD_VECTOR) |
514 (1 << MC_VECTOR);
6aa8b732
AK		 515
516
517 control->intercept = (1ULL << INTERCEPT_INTR) |
518 (1ULL << INTERCEPT_NMI) |
0152527b 519 (1ULL << INTERCEPT_SMI) |
6aa8b732 520 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 521 (1ULL << INTERCEPT_INVD) |
6aa8b732 522 (1ULL << INTERCEPT_HLT) |
a7052897 523 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 524 (1ULL << INTERCEPT_INVLPGA) |
525 (1ULL << INTERCEPT_IOIO_PROT) |
526 (1ULL << INTERCEPT_MSR_PROT) |
527 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 528 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 529 (1ULL << INTERCEPT_VMRUN) |
530 (1ULL << INTERCEPT_VMMCALL) |
531 (1ULL << INTERCEPT_VMLOAD) |
532 (1ULL << INTERCEPT_VMSAVE) |
533 (1ULL << INTERCEPT_STGI) |
534 (1ULL << INTERCEPT_CLGI) |
916ce236 535 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 536 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 537 (1ULL << INTERCEPT_MONITOR) |
538 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 539
540 control->iopm_base_pa = iopm_base;
f65c229c 541 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 542 control->tsc_offset = 0;
6aa8b732
AK		 543 control->int_ctl = V_INTR_MASKING_MASK;
544
545 init_seg(&save->es);
546 init_seg(&save->ss);
547 init_seg(&save->ds);
548 init_seg(&save->fs);
549 init_seg(&save->gs);
550
551 save->cs.selector = 0xf000;
552 /* Executable/Readable Code Segment */
553 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
554 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
555 save->cs.limit = 0xffff;
d92899a0
AK		 556 /*
557 * cs.base should really be 0xffff0000, but vmx can't handle that, so
558 * be consistent with it.
559 *
560 * Replace when we have real mode working for vmx.
561 */
562 save->cs.base = 0xf0000;
6aa8b732
AK		 563
564 save->gdtr.limit = 0xffff;
565 save->idtr.limit = 0xffff;
566
567 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
568 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
569
9962d032 570 save->efer = EFER_SVME;
d77c26fc 571 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 572 save->dr7 = 0x400;
573 save->rflags = 2;
574 save->rip = 0x0000fff0;
5fdbf976 575 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 576
577 /*
578 * cr0 val on cpu init should be 0x60000010, we enable cpu
579 * cache by default. the orderly way is to enable cache in bios.
580 */
707d92fa 581 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 582 save->cr4 = X86_CR4_PAE;
6aa8b732 583 /* rdx = ?? */
709ddebf
JR		 584
585 if (npt_enabled) {
586 /* Setup VMCB for Nested Paging */
587 control->nested_ctl = 1;
a7052897
MT		 588 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
589 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 590 control->intercept_exceptions &= ~(1 << PF_VECTOR);
591 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
592 INTERCEPT_CR3_MASK);
593 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
594 INTERCEPT_CR3_MASK);
595 save->g_pat = 0x0007040600070406ULL;
596 /* enable caching because the QEMU Bios doesn't enable it */
597 save->cr0 = X86_CR0_ET;
598 save->cr3 = 0;
599 save->cr4 = 0;
600 }
a79d2f18 601 force_new_asid(&svm->vcpu);
1371d904 602
3d6368ef 603 svm->nested_vmcb = 0;
1371d904 604 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 605}
606
e00c8cf2 607static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 608{
609 struct vcpu_svm *svm = to_svm(vcpu);
610
e6101a96 611 init_vmcb(svm);
70433389
AK		 612
613 if (vcpu->vcpu_id != 0) {
5fdbf976 614 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 615 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
616 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 617 }
5fdbf976
MT		 618 vcpu->arch.regs_avail = ~0;
619 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 620
621 return 0;
04d2cc77
AK		 622}
623
fb3f0f51 624static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 625{
a2fa3e9f 626 struct vcpu_svm *svm;
6aa8b732 627 struct page *page;
f65c229c 628 struct page *msrpm_pages;
b286d5d8 629 struct page *hsave_page;
3d6368ef 630 struct page *nested_msrpm_pages;
fb3f0f51 631 int err;
6aa8b732 632
c16f862d 633 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 634 if (!svm) {
635 err = -ENOMEM;
636 goto out;
637 }
638
639 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
640 if (err)
641 goto free_svm;
642
6aa8b732 643 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 644 if (!page) {
645 err = -ENOMEM;
646 goto uninit;
647 }
6aa8b732 648
f65c229c
JR		 649 err = -ENOMEM;
650 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
651 if (!msrpm_pages)
652 goto uninit;
3d6368ef
AG		 653
654 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
655 if (!nested_msrpm_pages)
656 goto uninit;
657
f65c229c
JR		 658 svm->msrpm = page_address(msrpm_pages);
659 svm_vcpu_init_msrpm(svm->msrpm);
660
b286d5d8
AG		 661 hsave_page = alloc_page(GFP_KERNEL);
662 if (!hsave_page)
663 goto uninit;
664 svm->hsave = page_address(hsave_page);
665
3d6368ef
AG		 666 svm->nested_msrpm = page_address(nested_msrpm_pages);
667
a2fa3e9f
GH		 668 svm->vmcb = page_address(page);
669 clear_page(svm->vmcb);
670 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
671 svm->asid_generation = 0;
e6101a96 672 init_vmcb(svm);
a2fa3e9f 673
fb3f0f51
RR		 674 fx_init(&svm->vcpu);
675 svm->vcpu.fpu_active = 1;
ad312c7c 676 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 677 if (svm->vcpu.vcpu_id == 0)
ad312c7c 678 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 679
fb3f0f51 680 return &svm->vcpu;
36241b8c 681
fb3f0f51
RR		 682uninit:
683 kvm_vcpu_uninit(&svm->vcpu);
684free_svm:
a4770347 685 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 686out:
687 return ERR_PTR(err);
6aa8b732
AK		 688}
689
690static void svm_free_vcpu(struct kvm_vcpu *vcpu)
691{
a2fa3e9f
GH		 692 struct vcpu_svm *svm = to_svm(vcpu);
693
fb3f0f51 694 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 695 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 696 __free_page(virt_to_page(svm->hsave));
3d6368ef 697 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 698 kvm_vcpu_uninit(vcpu);
a4770347 699 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 700}
701
15ad7146 702static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 703{
a2fa3e9f 704 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 705 int i;
0cc5064d 706
0cc5064d
AK		 707 if (unlikely(cpu != vcpu->cpu)) {
708 u64 tsc_this, delta;
709
710 /*
711 * Make sure that the guest sees a monotonically
712 * increasing TSC.
713 */
714 rdtscll(tsc_this);
ad312c7c 715 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 716 svm->vmcb->control.tsc_offset += delta;
0cc5064d 717 vcpu->cpu = cpu;
2f599714 718 kvm_migrate_timers(vcpu);
0cc5064d 719 }
94dfbdb3
AL		 720
721 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 722 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 723}
724
725static void svm_vcpu_put(struct kvm_vcpu *vcpu)
726{
a2fa3e9f 727 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 728 int i;
729
e1beb1d3 730 ++vcpu->stat.host_state_reload;
94dfbdb3 731 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 732 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 733
ad312c7c 734 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 735}
736
6aa8b732
AK		 737static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
738{
a2fa3e9f 739 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 740}
741
742static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
743{
a2fa3e9f 744 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 745}
746
f0b85051
AG		 747static void svm_set_vintr(struct vcpu_svm *svm)
748{
749 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
750}
751
752static void svm_clear_vintr(struct vcpu_svm *svm)
753{
754 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
755}
756
6aa8b732
AK		 757static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
758{
a2fa3e9f 759 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 760
761 switch (seg) {
762 case VCPU_SREG_CS: return &save->cs;
763 case VCPU_SREG_DS: return &save->ds;
764 case VCPU_SREG_ES: return &save->es;
765 case VCPU_SREG_FS: return &save->fs;
766 case VCPU_SREG_GS: return &save->gs;
767 case VCPU_SREG_SS: return &save->ss;
768 case VCPU_SREG_TR: return &save->tr;
769 case VCPU_SREG_LDTR: return &save->ldtr;
770 }
771 BUG();
8b6d44c7 772 return NULL;
6aa8b732
AK		 773}
774
775static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
776{
777 struct vmcb_seg *s = svm_seg(vcpu, seg);
778
779 return s->base;
780}
781
782static void svm_get_segment(struct kvm_vcpu *vcpu,
783 struct kvm_segment *var, int seg)
784{
785 struct vmcb_seg *s = svm_seg(vcpu, seg);
786
787 var->base = s->base;
788 var->limit = s->limit;
789 var->selector = s->selector;
790 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
791 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
792 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
793 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
794 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
795 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
796 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
797 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc
AS		 798
799 /*
800 * SVM always stores 0 for the 'G' bit in the CS selector in
801 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
802 * Intel's VMENTRY has a check on the 'G' bit.
803 */
804 if (seg == VCPU_SREG_CS)
805 var->g = s->limit > 0xfffff;
806
c0d09828
AS		 807 /*
808 * Work around a bug where the busy flag in the tr selector
809 * isn't exposed
810 */
811 if (seg == VCPU_SREG_TR)
812 var->type |= 0x2;
813
6aa8b732
AK		 814 var->unusable = !var->present;
815}
816
2e4d2653
IE		 817static int svm_get_cpl(struct kvm_vcpu *vcpu)
818{
819 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
820
821 return save->cpl;
822}
823
6aa8b732
AK		 824static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
825{
a2fa3e9f
GH		 826 struct vcpu_svm *svm = to_svm(vcpu);
827
828 dt->limit = svm->vmcb->save.idtr.limit;
829 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 830}
831
832static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
833{
a2fa3e9f
GH		 834 struct vcpu_svm *svm = to_svm(vcpu);
835
836 svm->vmcb->save.idtr.limit = dt->limit;
837 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 838}
839
840static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
841{
a2fa3e9f
GH		 842 struct vcpu_svm *svm = to_svm(vcpu);
843
844 dt->limit = svm->vmcb->save.gdtr.limit;
845 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 846}
847
848static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
849{
a2fa3e9f
GH		 850 struct vcpu_svm *svm = to_svm(vcpu);
851
852 svm->vmcb->save.gdtr.limit = dt->limit;
853 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 854}
855
25c4c276 856static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 857{
858}
859
6aa8b732
AK		 860static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
861{
a2fa3e9f
GH		 862 struct vcpu_svm *svm = to_svm(vcpu);
863
05b3e0c2 864#ifdef CONFIG_X86_64
ad312c7c 865 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 866 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 867 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 868 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 869 }
870
d77c26fc 871 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 872 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 873 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 874 }
875 }
876#endif
709ddebf
JR		 877 if (npt_enabled)
878 goto set;
879
ad312c7c 880 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 881 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 882 vcpu->fpu_active = 1;
883 }
884
ad312c7c 885 vcpu->arch.cr0 = cr0;
707d92fa 886 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 887 if (!vcpu->fpu_active) {
888 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 889 cr0 |= X86_CR0_TS;
6b390b63 890 }
709ddebf
JR		 891set:
892 /*
893 * re-enable caching here because the QEMU bios
894 * does not do it - this results in some delay at
895 * reboot
896 */
897 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 898 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 899}
900
901static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
902{
6394b649 903 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 904 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
905
906 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
907 force_new_asid(vcpu);
6394b649 908
ec077263
JR		 909 vcpu->arch.cr4 = cr4;
910 if (!npt_enabled)
911 cr4 |= X86_CR4_PAE;
6394b649 912 cr4 |= host_cr4_mce;
ec077263 913 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 914}
915
916static void svm_set_segment(struct kvm_vcpu *vcpu,
917 struct kvm_segment *var, int seg)
918{
a2fa3e9f 919 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 920 struct vmcb_seg *s = svm_seg(vcpu, seg);
921
922 s->base = var->base;
923 s->limit = var->limit;
924 s->selector = var->selector;
925 if (var->unusable)
926 s->attrib = 0;
927 else {
928 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
929 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
930 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
931 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
932 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
933 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
934 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
935 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
936 }
937 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 938 svm->vmcb->save.cpl
939 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 940 >> SVM_SELECTOR_DPL_SHIFT) & 3;
941
942}
943
d0bfb940 944static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 945{
d0bfb940
JK		 946 int old_debug = vcpu->guest_debug;
947 struct vcpu_svm *svm = to_svm(vcpu);
948
949 vcpu->guest_debug = dbg->control;
950
951 svm->vmcb->control.intercept_exceptions &=
952 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
953 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
954 if (vcpu->guest_debug &
955 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
956 svm->vmcb->control.intercept_exceptions |=
957 1 << DB_VECTOR;
958 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
959 svm->vmcb->control.intercept_exceptions |=
960 1 << BP_VECTOR;
961 } else
962 vcpu->guest_debug = 0;
963
ae675ef0
JK		 964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
965 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
966 else
967 svm->vmcb->save.dr7 = vcpu->arch.dr7;
968
d0bfb940
JK		 969 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
970 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
971 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
972 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
973
974 return 0;
6aa8b732
AK		 975}
976
2a8067f1
ED		 977static int svm_get_irq(struct kvm_vcpu *vcpu)
978{
979 struct vcpu_svm *svm = to_svm(vcpu);
980 u32 exit_int_info = svm->vmcb->control.exit_int_info;
981
982 if (is_external_interrupt(exit_int_info))
983 return exit_int_info & SVM_EVTINJ_VEC_MASK;
984 return -1;
985}
986
6aa8b732
AK		 987static void load_host_msrs(struct kvm_vcpu *vcpu)
988{
94dfbdb3 989#ifdef CONFIG_X86_64
a2fa3e9f 990 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 991#endif
6aa8b732
AK		 992}
993
994static void save_host_msrs(struct kvm_vcpu *vcpu)
995{
94dfbdb3 996#ifdef CONFIG_X86_64
a2fa3e9f 997 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 998#endif
6aa8b732
AK		 999}
1000
e756fc62 1001static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1002{
1003 if (svm_data->next_asid > svm_data->max_asid) {
1004 ++svm_data->asid_generation;
1005 svm_data->next_asid = 1;
a2fa3e9f 1006 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1007 }
1008
e756fc62 1009 svm->vcpu.cpu = svm_data->cpu;
a2fa3e9f
GH		 1010 svm->asid_generation = svm_data->asid_generation;
1011 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1012}
1013
6aa8b732
AK		 1014static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1015{
42dbaa5a
JK		 1016 struct vcpu_svm *svm = to_svm(vcpu);
1017 unsigned long val;
1018
1019 switch (dr) {
1020 case 0 ... 3:
1021 val = vcpu->arch.db[dr];
1022 break;
1023 case 6:
1024 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1025 val = vcpu->arch.dr6;
1026 else
1027 val = svm->vmcb->save.dr6;
1028 break;
1029 case 7:
1030 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1031 val = vcpu->arch.dr7;
1032 else
1033 val = svm->vmcb->save.dr7;
1034 break;
1035 default:
1036 val = 0;
1037 }
1038
af9ca2d7
JR		 1039 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1040 return val;
6aa8b732
AK		 1041}
1042
1043static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1044 int *exception)
1045{
a2fa3e9f
GH		 1046 struct vcpu_svm *svm = to_svm(vcpu);
1047
42dbaa5a 1048 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
6aa8b732 1049
42dbaa5a 1050 *exception = 0;
6aa8b732
AK		 1051
1052 switch (dr) {
1053 case 0 ... 3:
42dbaa5a
JK		 1054 vcpu->arch.db[dr] = value;
1055 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1056 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1057 return;
1058 case 4 ... 5:
42dbaa5a 1059 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1060 *exception = UD_VECTOR;
42dbaa5a
JK		 1061 return;
1062 case 6:
1063 if (value & 0xffffffff00000000ULL) {
1064 *exception = GP_VECTOR;
6aa8b732
AK		 1065 return;
1066 }
42dbaa5a
JK		 1067 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1068 return;
1069 case 7:
1070 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1071 *exception = GP_VECTOR;
1072 return;
1073 }
42dbaa5a
JK		 1074 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1075 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1076 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1077 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1078 }
6aa8b732 1079 return;
6aa8b732 1080 default:
42dbaa5a 1081 /* FIXME: Possible case? */
6aa8b732 1082 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1083 __func__, dr);
6aa8b732
AK		 1084 *exception = UD_VECTOR;
1085 return;
1086 }
1087}
1088
e756fc62 1089static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1090{
a2fa3e9f 1091 u32 exit_int_info = svm->vmcb->control.exit_int_info;
e756fc62 1092 struct kvm *kvm = svm->vcpu.kvm;
6aa8b732
AK		 1093 u64 fault_address;
1094 u32 error_code;
577bdc49 1095 bool event_injection = false;
6aa8b732 1096
85f455f7 1097 if (!irqchip_in_kernel(kvm) &&
577bdc49
AK		 1098 is_external_interrupt(exit_int_info)) {
1099 event_injection = true;
e756fc62 1100 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
577bdc49 1101 }
6aa8b732 1102
a2fa3e9f
GH		 1103 fault_address = svm->vmcb->control.exit_info_2;
1104 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1105
1106 if (!npt_enabled)
1107 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1108 (u32)fault_address, (u32)(fault_address >> 32),
1109 handler);
d2ebb410
JR		 1110 else
1111 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1112 (u32)fault_address, (u32)(fault_address >> 32),
1113 handler);
44874f84
JR		 1114 /*
1115 * FIXME: Tis shouldn't be necessary here, but there is a flush
1116 * missing in the MMU code. Until we find this bug, flush the
1117 * complete TLB here on an NPF
1118 */
1119 if (npt_enabled)
1120 svm_flush_tlb(&svm->vcpu);
af9ca2d7 1121
48d15039 1122 if (!npt_enabled && event_injection)
577bdc49 1123 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1124 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1125}
1126
d0bfb940
JK		 1127static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1128{
1129 if (!(svm->vcpu.guest_debug &
1130 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1131 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1132 return 1;
1133 }
1134 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1135 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1136 kvm_run->debug.arch.exception = DB_VECTOR;
1137 return 0;
1138}
1139
1140static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1141{
1142 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1143 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1144 kvm_run->debug.arch.exception = BP_VECTOR;
1145 return 0;
1146}
1147
7aa81cc0
AL		 1148static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1149{
1150 int er;
1151
571008da 1152 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1153 if (er != EMULATE_DONE)
7ee5d940 1154 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1155 return 1;
1156}
1157
e756fc62 1158static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1159{
a2fa3e9f 1160 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1161 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1162 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1163 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1164
1165 return 1;
7807fa6c
AL		 1166}
1167
53371b50
JR		 1168static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1169{
1170 /*
1171 * On an #MC intercept the MCE handler is not called automatically in
1172 * the host. So do it by hand here.
1173 */
1174 asm volatile (
1175 "int $0x12\n");
1176 /* not sure if we ever come back to this point */
1177
1178 return 1;
1179}
1180
e756fc62 1181static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1182{
1183 /*
1184 * VMCB is undefined after a SHUTDOWN intercept
1185 * so reinitialize it.
1186 */
a2fa3e9f 1187 clear_page(svm->vmcb);
e6101a96 1188 init_vmcb(svm);
46fe4ddd
JR		 1189
1190 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1191 return 0;
1192}
1193
e756fc62 1194static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1195{
d77c26fc 1196 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1197 int size, in, string;
039576c0 1198 unsigned port;
6aa8b732 1199
e756fc62 1200 ++svm->vcpu.stat.io_exits;
6aa8b732 1201
a2fa3e9f 1202 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1203
e70669ab
LV		 1204 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1205
1206 if (string) {
3427318f
LV		 1207 if (emulate_instruction(&svm->vcpu,
1208 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1209 return 0;
1210 return 1;
1211 }
1212
039576c0
AK		 1213 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1214 port = io_info >> 16;
1215 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1216
e93f36bc 1217 skip_emulated_instruction(&svm->vcpu);
3090dd73 1218 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1219}
1220
c47f098d
JR		 1221static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1222{
af9ca2d7 1223 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1224 return 1;
1225}
1226
a0698055
JR		 1227static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1228{
1229 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1230 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1231 return 1;
1232}
1233
e756fc62 1234static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1235{
1236 return 1;
1237}
1238
e756fc62 1239static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1240{
5fdbf976 1241 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1242 skip_emulated_instruction(&svm->vcpu);
1243 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1244}
1245
e756fc62 1246static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1247{
5fdbf976 1248 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1249 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1250 kvm_emulate_hypercall(&svm->vcpu);
1251 return 1;
02e235bc
AK		 1252}
1253
c0725420
AG		 1254static int nested_svm_check_permissions(struct vcpu_svm *svm)
1255{
1256 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1257 || !is_paging(&svm->vcpu)) {
1258 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1259 return 1;
1260 }
1261
1262 if (svm->vmcb->save.cpl) {
1263 kvm_inject_gp(&svm->vcpu, 0);
1264 return 1;
1265 }
1266
1267 return 0;
1268}
1269
cf74a78b
AG		 1270static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1271 bool has_error_code, u32 error_code)
1272{
1273 if (is_nested(svm)) {
1274 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1275 svm->vmcb->control.exit_code_hi = 0;
1276 svm->vmcb->control.exit_info_1 = error_code;
1277 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1278 if (nested_svm_exit_handled(svm, false)) {
1279 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1280
1281 nested_svm_vmexit(svm);
1282 return 1;
1283 }
1284 }
1285
1286 return 0;
1287}
1288
1289static inline int nested_svm_intr(struct vcpu_svm *svm)
1290{
1291 if (is_nested(svm)) {
1292 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1293 return 0;
1294
1295 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1296 return 0;
1297
1298 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1299
1300 if (nested_svm_exit_handled(svm, false)) {
1301 nsvm_printk("VMexit -> INTR\n");
1302 nested_svm_vmexit(svm);
1303 return 1;
1304 }
1305 }
1306
1307 return 0;
1308}
1309
c0725420
AG		 1310static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1311{
1312 struct page *page;
1313
1314 down_read(&current->mm->mmap_sem);
1315 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1316 up_read(&current->mm->mmap_sem);
1317
1318 if (is_error_page(page)) {
1319 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1320 __func__, gpa);
1321 kvm_release_page_clean(page);
1322 kvm_inject_gp(&svm->vcpu, 0);
1323 return NULL;
1324 }
1325 return page;
1326}
1327
1328static int nested_svm_do(struct vcpu_svm *svm,
1329 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1330 int (*handler)(struct vcpu_svm *svm,
1331 void *arg1,
1332 void *arg2,
1333 void *opaque))
1334{
1335 struct page *arg1_page;
1336 struct page *arg2_page = NULL;
1337 void *arg1;
1338 void *arg2 = NULL;
1339 int retval;
1340
1341 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1342 if(arg1_page == NULL)
1343 return 1;
1344
1345 if (arg2_gpa) {
1346 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1347 if(arg2_page == NULL) {
1348 kvm_release_page_clean(arg1_page);
1349 return 1;
1350 }
1351 }
1352
1353 arg1 = kmap_atomic(arg1_page, KM_USER0);
1354 if (arg2_gpa)
1355 arg2 = kmap_atomic(arg2_page, KM_USER1);
1356
1357 retval = handler(svm, arg1, arg2, opaque);
1358
1359 kunmap_atomic(arg1, KM_USER0);
1360 if (arg2_gpa)
1361 kunmap_atomic(arg2, KM_USER1);
1362
1363 kvm_release_page_dirty(arg1_page);
1364 if (arg2_gpa)
1365 kvm_release_page_dirty(arg2_page);
1366
1367 return retval;
1368}
1369
cf74a78b
AG		 1370static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1371 void *arg1,
1372 void *arg2,
1373 void *opaque)
1374{
1375 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1376 bool kvm_overrides = *(bool *)opaque;
1377 u32 exit_code = svm->vmcb->control.exit_code;
1378
1379 if (kvm_overrides) {
1380 switch (exit_code) {
1381 case SVM_EXIT_INTR:
1382 case SVM_EXIT_NMI:
1383 return 0;
1384 /* For now we are always handling NPFs when using them */
1385 case SVM_EXIT_NPF:
1386 if (npt_enabled)
1387 return 0;
1388 break;
1389 /* When we're shadowing, trap PFs */
1390 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1391 if (!npt_enabled)
1392 return 0;
1393 break;
1394 default:
1395 break;
1396 }
1397 }
1398
1399 switch (exit_code) {
1400 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1401 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1402 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1403 return 1;
1404 break;
1405 }
1406 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1407 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1408 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1409 return 1;
1410 break;
1411 }
1412 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1413 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1414 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1415 return 1;
1416 break;
1417 }
1418 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1419 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1420 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1421 return 1;
1422 break;
1423 }
1424 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1425 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1426 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1427 return 1;
1428 break;
1429 }
1430 default: {
1431 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1432 nsvm_printk("exit code: 0x%x\n", exit_code);
1433 if (nested_vmcb->control.intercept & exit_bits)
1434 return 1;
1435 }
1436 }
1437
1438 return 0;
1439}
1440
1441static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1442 void *arg1, void *arg2,
1443 void *opaque)
1444{
1445 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1446 u8 *msrpm = (u8 *)arg2;
1447 u32 t0, t1;
1448 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1449 u32 param = svm->vmcb->control.exit_info_1 & 1;
1450
1451 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1452 return 0;
1453
1454 switch(msr) {
1455 case 0 ... 0x1fff:
1456 t0 = (msr * 2) % 8;
1457 t1 = msr / 8;
1458 break;
1459 case 0xc0000000 ... 0xc0001fff:
1460 t0 = (8192 + msr - 0xc0000000) * 2;
1461 t1 = (t0 / 8);
1462 t0 %= 8;
1463 break;
1464 case 0xc0010000 ... 0xc0011fff:
1465 t0 = (16384 + msr - 0xc0010000) * 2;
1466 t1 = (t0 / 8);
1467 t0 %= 8;
1468 break;
1469 default:
1470 return 1;
1471 break;
1472 }
1473 if (msrpm[t1] & ((1 << param) << t0))
1474 return 1;
1475
1476 return 0;
1477}
1478
1479static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1480{
1481 bool k = kvm_override;
1482
1483 switch (svm->vmcb->control.exit_code) {
1484 case SVM_EXIT_MSR:
1485 return nested_svm_do(svm, svm->nested_vmcb,
1486 svm->nested_vmcb_msrpm, NULL,
1487 nested_svm_exit_handled_msr);
1488 default: break;
1489 }
1490
1491 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1492 nested_svm_exit_handled_real);
1493}
1494
1495static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1496 void *arg2, void *opaque)
1497{
1498 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1499 struct vmcb *hsave = svm->hsave;
1500 u64 nested_save[] = { nested_vmcb->save.cr0,
1501 nested_vmcb->save.cr3,
1502 nested_vmcb->save.cr4,
1503 nested_vmcb->save.efer,
1504 nested_vmcb->control.intercept_cr_read,
1505 nested_vmcb->control.intercept_cr_write,
1506 nested_vmcb->control.intercept_dr_read,
1507 nested_vmcb->control.intercept_dr_write,
1508 nested_vmcb->control.intercept_exceptions,
1509 nested_vmcb->control.intercept,
1510 nested_vmcb->control.msrpm_base_pa,
1511 nested_vmcb->control.iopm_base_pa,
1512 nested_vmcb->control.tsc_offset };
1513
1514 /* Give the current vmcb to the guest */
1515 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1516 nested_vmcb->save.cr0 = nested_save[0];
1517 if (!npt_enabled)
1518 nested_vmcb->save.cr3 = nested_save[1];
1519 nested_vmcb->save.cr4 = nested_save[2];
1520 nested_vmcb->save.efer = nested_save[3];
1521 nested_vmcb->control.intercept_cr_read = nested_save[4];
1522 nested_vmcb->control.intercept_cr_write = nested_save[5];
1523 nested_vmcb->control.intercept_dr_read = nested_save[6];
1524 nested_vmcb->control.intercept_dr_write = nested_save[7];
1525 nested_vmcb->control.intercept_exceptions = nested_save[8];
1526 nested_vmcb->control.intercept = nested_save[9];
1527 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1528 nested_vmcb->control.iopm_base_pa = nested_save[11];
1529 nested_vmcb->control.tsc_offset = nested_save[12];
1530
1531 /* We always set V_INTR_MASKING and remember the old value in hflags */
1532 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1533 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1534
1535 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1536 (nested_vmcb->control.int_vector)) {
1537 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1538 nested_vmcb->control.int_vector);
1539 }
1540
1541 /* Restore the original control entries */
1542 svm->vmcb->control = hsave->control;
1543
1544 /* Kill any pending exceptions */
1545 if (svm->vcpu.arch.exception.pending == true)
1546 nsvm_printk("WARNING: Pending Exception\n");
1547 svm->vcpu.arch.exception.pending = false;
1548
1549 /* Restore selected save entries */
1550 svm->vmcb->save.es = hsave->save.es;
1551 svm->vmcb->save.cs = hsave->save.cs;
1552 svm->vmcb->save.ss = hsave->save.ss;
1553 svm->vmcb->save.ds = hsave->save.ds;
1554 svm->vmcb->save.gdtr = hsave->save.gdtr;
1555 svm->vmcb->save.idtr = hsave->save.idtr;
1556 svm->vmcb->save.rflags = hsave->save.rflags;
1557 svm_set_efer(&svm->vcpu, hsave->save.efer);
1558 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1559 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1560 if (npt_enabled) {
1561 svm->vmcb->save.cr3 = hsave->save.cr3;
1562 svm->vcpu.arch.cr3 = hsave->save.cr3;
1563 } else {
1564 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1565 }
1566 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1567 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1568 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1569 svm->vmcb->save.dr7 = 0;
1570 svm->vmcb->save.cpl = 0;
1571 svm->vmcb->control.exit_int_info = 0;
1572
1573 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1574 /* Exit nested SVM mode */
1575 svm->nested_vmcb = 0;
1576
1577 return 0;
1578}
1579
1580static int nested_svm_vmexit(struct vcpu_svm *svm)
1581{
1582 nsvm_printk("VMexit\n");
1583 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1584 NULL, nested_svm_vmexit_real))
1585 return 1;
1586
1587 kvm_mmu_reset_context(&svm->vcpu);
1588 kvm_mmu_load(&svm->vcpu);
1589
1590 return 0;
1591}
3d6368ef
AG		 1592
1593static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1594 void *arg2, void *opaque)
1595{
1596 int i;
1597 u32 *nested_msrpm = (u32*)arg1;
1598 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1599 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1600 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1601
1602 return 0;
1603}
1604
1605static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1606 void *arg2, void *opaque)
1607{
1608 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1609 struct vmcb *hsave = svm->hsave;
1610
1611 /* nested_vmcb is our indicator if nested SVM is activated */
1612 svm->nested_vmcb = svm->vmcb->save.rax;
1613
1614 /* Clear internal status */
1615 svm->vcpu.arch.exception.pending = false;
1616
1617 /* Save the old vmcb, so we don't need to pick what we save, but
1618 can restore everything when a VMEXIT occurs */
1619 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1620 /* We need to remember the original CR3 in the SPT case */
1621 if (!npt_enabled)
1622 hsave->save.cr3 = svm->vcpu.arch.cr3;
1623 hsave->save.cr4 = svm->vcpu.arch.cr4;
1624 hsave->save.rip = svm->next_rip;
1625
1626 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1627 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1628 else
1629 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1630
1631 /* Load the nested guest state */
1632 svm->vmcb->save.es = nested_vmcb->save.es;
1633 svm->vmcb->save.cs = nested_vmcb->save.cs;
1634 svm->vmcb->save.ss = nested_vmcb->save.ss;
1635 svm->vmcb->save.ds = nested_vmcb->save.ds;
1636 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1637 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1638 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1639 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1640 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1641 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1642 if (npt_enabled) {
1643 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1644 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1645 } else {
1646 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1647 kvm_mmu_reset_context(&svm->vcpu);
1648 }
1649 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1650 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1651 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1652 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1653 /* In case we don't even reach vcpu_run, the fields are not updated */
1654 svm->vmcb->save.rax = nested_vmcb->save.rax;
1655 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1656 svm->vmcb->save.rip = nested_vmcb->save.rip;
1657 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1658 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1659 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1660
1661 /* We don't want a nested guest to be more powerful than the guest,
1662 so all intercepts are ORed */
1663 svm->vmcb->control.intercept_cr_read |=
1664 nested_vmcb->control.intercept_cr_read;
1665 svm->vmcb->control.intercept_cr_write |=
1666 nested_vmcb->control.intercept_cr_write;
1667 svm->vmcb->control.intercept_dr_read |=
1668 nested_vmcb->control.intercept_dr_read;
1669 svm->vmcb->control.intercept_dr_write |=
1670 nested_vmcb->control.intercept_dr_write;
1671 svm->vmcb->control.intercept_exceptions |=
1672 nested_vmcb->control.intercept_exceptions;
1673
1674 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1675
1676 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1677
1678 force_new_asid(&svm->vcpu);
1679 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1680 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1681 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1682 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1683 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1684 nested_vmcb->control.int_ctl);
1685 }
1686 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1687 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1688 else
1689 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1690
1691 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1692 nested_vmcb->control.exit_int_info,
1693 nested_vmcb->control.int_state);
1694
1695 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1696 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1697 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1698 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1699 nsvm_printk("Injecting Event: 0x%x\n",
1700 nested_vmcb->control.event_inj);
1701 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1702 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1703
1704 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1705
1706 return 0;
1707}
1708
5542675b
AG		 1709static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1710{
1711 to_vmcb->save.fs = from_vmcb->save.fs;
1712 to_vmcb->save.gs = from_vmcb->save.gs;
1713 to_vmcb->save.tr = from_vmcb->save.tr;
1714 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1715 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1716 to_vmcb->save.star = from_vmcb->save.star;
1717 to_vmcb->save.lstar = from_vmcb->save.lstar;
1718 to_vmcb->save.cstar = from_vmcb->save.cstar;
1719 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1720 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1721 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1722 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1723
1724 return 1;
1725}
1726
1727static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1728 void *arg2, void *opaque)
1729{
1730 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1731}
1732
1733static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1734 void *arg2, void *opaque)
1735{
1736 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1737}
1738
1739static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1740{
1741 if (nested_svm_check_permissions(svm))
1742 return 1;
1743
1744 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1745 skip_emulated_instruction(&svm->vcpu);
1746
1747 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1748
1749 return 1;
1750}
1751
1752static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1753{
1754 if (nested_svm_check_permissions(svm))
1755 return 1;
1756
1757 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1758 skip_emulated_instruction(&svm->vcpu);
1759
1760 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1761
1762 return 1;
1763}
1764
3d6368ef
AG		 1765static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1766{
1767 nsvm_printk("VMrun\n");
1768 if (nested_svm_check_permissions(svm))
1769 return 1;
1770
1771 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1772 skip_emulated_instruction(&svm->vcpu);
1773
1774 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1775 NULL, nested_svm_vmrun))
1776 return 1;
1777
1778 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1779 NULL, nested_svm_vmrun_msrpm))
1780 return 1;
1781
1782 return 1;
1783}
1784
1371d904
AG		 1785static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1786{
1787 if (nested_svm_check_permissions(svm))
1788 return 1;
1789
1790 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1791 skip_emulated_instruction(&svm->vcpu);
1792
1793 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1794
1795 return 1;
1796}
1797
1798static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1799{
1800 if (nested_svm_check_permissions(svm))
1801 return 1;
1802
1803 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1804 skip_emulated_instruction(&svm->vcpu);
1805
1806 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1807
1808 /* After a CLGI no interrupts should come */
1809 svm_clear_vintr(svm);
1810 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1811
1812 return 1;
1813}
1814
e756fc62
RR		 1815static int invalid_op_interception(struct vcpu_svm *svm,
1816 struct kvm_run *kvm_run)
6aa8b732 1817{
7ee5d940 1818 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1819 return 1;
1820}
1821
e756fc62
RR		 1822static int task_switch_interception(struct vcpu_svm *svm,
1823 struct kvm_run *kvm_run)
6aa8b732 1824{
37817f29
IE		 1825 u16 tss_selector;
1826
1827 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1828 if (svm->vmcb->control.exit_info_2 &
1829 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1830 return kvm_task_switch(&svm->vcpu, tss_selector,
1831 TASK_SWITCH_IRET);
1832 if (svm->vmcb->control.exit_info_2 &
1833 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1834 return kvm_task_switch(&svm->vcpu, tss_selector,
1835 TASK_SWITCH_JMP);
1836 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
6aa8b732
AK		 1837}
1838
e756fc62 1839static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1840{
5fdbf976 1841 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1842 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1843 return 1;
6aa8b732
AK		 1844}
1845
a7052897
MT		 1846static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1847{
1848 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1849 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1850 return 1;
1851}
1852
e756fc62
RR		 1853static int emulate_on_interception(struct vcpu_svm *svm,
1854 struct kvm_run *kvm_run)
6aa8b732 1855{
3427318f 1856 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1857 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1858 return 1;
1859}
1860
1d075434
JR		 1861static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1862{
1863 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1864 if (irqchip_in_kernel(svm->vcpu.kvm))
1865 return 1;
1866 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1867 return 0;
1868}
1869
6aa8b732
AK		 1870static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1871{
a2fa3e9f
GH		 1872 struct vcpu_svm *svm = to_svm(vcpu);
1873
6aa8b732 1874 switch (ecx) {
6aa8b732
AK		 1875 case MSR_IA32_TIME_STAMP_COUNTER: {
1876 u64 tsc;
1877
1878 rdtscll(tsc);
a2fa3e9f 1879 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 1880 break;
1881 }
0e859cac 1882 case MSR_K6_STAR:
a2fa3e9f 1883 *data = svm->vmcb->save.star;
6aa8b732 1884 break;
0e859cac 1885#ifdef CONFIG_X86_64
6aa8b732 1886 case MSR_LSTAR:
a2fa3e9f 1887 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 1888 break;
1889 case MSR_CSTAR:
a2fa3e9f 1890 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 1891 break;
1892 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1893 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 1894 break;
1895 case MSR_SYSCALL_MASK:
a2fa3e9f 1896 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 1897 break;
1898#endif
1899 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1900 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 1901 break;
1902 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1903 *data = svm->vmcb->save.sysenter_eip;
6aa8b732
AK		 1904 break;
1905 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1906 *data = svm->vmcb->save.sysenter_esp;
6aa8b732 1907 break;
a2938c80
JR		 1908 /* Nobody will change the following 5 values in the VMCB so
1909 we can safely return them on rdmsr. They will always be 0
1910 until LBRV is implemented. */
1911 case MSR_IA32_DEBUGCTLMSR:
1912 *data = svm->vmcb->save.dbgctl;
1913 break;
1914 case MSR_IA32_LASTBRANCHFROMIP:
1915 *data = svm->vmcb->save.br_from;
1916 break;
1917 case MSR_IA32_LASTBRANCHTOIP:
1918 *data = svm->vmcb->save.br_to;
1919 break;
1920 case MSR_IA32_LASTINTFROMIP:
1921 *data = svm->vmcb->save.last_excp_from;
1922 break;
1923 case MSR_IA32_LASTINTTOIP:
1924 *data = svm->vmcb->save.last_excp_to;
1925 break;
b286d5d8
AG		 1926 case MSR_VM_HSAVE_PA:
1927 *data = svm->hsave_msr;
1928 break;
eb6f302e
JR		 1929 case MSR_VM_CR:
1930 *data = 0;
1931 break;
c8a73f18
AG		 1932 case MSR_IA32_UCODE_REV:
1933 *data = 0x01000065;
1934 break;
6aa8b732 1935 default:
3bab1f5d 1936 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1937 }
1938 return 0;
1939}
1940
e756fc62 1941static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1942{
ad312c7c 1943 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 1944 u64 data;
1945
e756fc62 1946 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 1947 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 1948 else {
af9ca2d7
JR		 1949 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1950 (u32)(data >> 32), handler);
1951
5fdbf976 1952 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 1953 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 1954 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1955 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 1956 }
1957 return 1;
1958}
1959
1960static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1961{
a2fa3e9f
GH		 1962 struct vcpu_svm *svm = to_svm(vcpu);
1963
6aa8b732 1964 switch (ecx) {
6aa8b732
AK		 1965 case MSR_IA32_TIME_STAMP_COUNTER: {
1966 u64 tsc;
1967
1968 rdtscll(tsc);
a2fa3e9f 1969 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 1970 break;
1971 }
0e859cac 1972 case MSR_K6_STAR:
a2fa3e9f 1973 svm->vmcb->save.star = data;
6aa8b732 1974 break;
49b14f24 1975#ifdef CONFIG_X86_64
6aa8b732 1976 case MSR_LSTAR:
a2fa3e9f 1977 svm->vmcb->save.lstar = data;
6aa8b732
AK		 1978 break;
1979 case MSR_CSTAR:
a2fa3e9f 1980 svm->vmcb->save.cstar = data;
6aa8b732
AK		 1981 break;
1982 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1983 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 1984 break;
1985 case MSR_SYSCALL_MASK:
a2fa3e9f 1986 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 1987 break;
1988#endif
1989 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1990 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 1991 break;
1992 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1993 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 1994 break;
1995 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1996 svm->vmcb->save.sysenter_esp = data;
6aa8b732 1997 break;
a2938c80 1998 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 1999 if (!svm_has(SVM_FEATURE_LBRV)) {
2000 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2001 __func__, data);
24e09cbf
JR		 2002 break;
2003 }
2004 if (data & DEBUGCTL_RESERVED_BITS)
2005 return 1;
2006
2007 svm->vmcb->save.dbgctl = data;
2008 if (data & (1ULL<<0))
2009 svm_enable_lbrv(svm);
2010 else
2011 svm_disable_lbrv(svm);
a2938c80 2012 break;
62b9abaa
JR		 2013 case MSR_K7_EVNTSEL0:
2014 case MSR_K7_EVNTSEL1:
2015 case MSR_K7_EVNTSEL2:
2016 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2017 case MSR_K7_PERFCTR0:
2018 case MSR_K7_PERFCTR1:
2019 case MSR_K7_PERFCTR2:
2020 case MSR_K7_PERFCTR3:
62b9abaa 2021 /*
14ae51b6
CL		 2022 * Just discard all writes to the performance counters; this
2023 * should keep both older linux and windows 64-bit guests
2024 * happy
62b9abaa 2025 */
14ae51b6
CL		 2026 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2027
b286d5d8
AG		 2028 break;
2029 case MSR_VM_HSAVE_PA:
2030 svm->hsave_msr = data;
62b9abaa 2031 break;
6aa8b732 2032 default:
3bab1f5d 2033 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2034 }
2035 return 0;
2036}
2037
e756fc62 2038static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2039{
ad312c7c 2040 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2041 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2042 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2043
2044 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2045 handler);
2046
5fdbf976 2047 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2048 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2049 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2050 else
e756fc62 2051 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2052 return 1;
2053}
2054
e756fc62 2055static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2056{
e756fc62
RR		 2057 if (svm->vmcb->control.exit_info_1)
2058 return wrmsr_interception(svm, kvm_run);
6aa8b732 2059 else
e756fc62 2060 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2061}
2062
e756fc62 2063static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2064 struct kvm_run *kvm_run)
2065{
af9ca2d7
JR		 2066 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2067
f0b85051 2068 svm_clear_vintr(svm);
85f455f7 2069 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2070 /*
2071 * If the user space waits to inject interrupts, exit as soon as
2072 * possible
2073 */
2074 if (kvm_run->request_interrupt_window &&
ad312c7c 2075 !svm->vcpu.arch.irq_summary) {
e756fc62 2076 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2077 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2078 return 0;
2079 }
2080
2081 return 1;
2082}
2083
e756fc62 2084static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2085 struct kvm_run *kvm_run) = {
2086 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2087 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2088 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2089 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2090 /* for now: */
2091 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2092 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2093 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2094 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2095 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2096 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2097 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2098 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2099 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2100 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2101 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2102 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2103 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2104 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2105 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2106 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2107 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2108 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2109 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2110 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2111 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2112 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2113 [SVM_EXIT_SMI] = nop_on_interception,
2114 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2115 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2116 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2117 [SVM_EXIT_CPUID] = cpuid_interception,
cf5a94d1 2118 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2119 [SVM_EXIT_HLT] = halt_interception,
a7052897 2120 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2121 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2122 [SVM_EXIT_IOIO] = io_interception,
2123 [SVM_EXIT_MSR] = msr_interception,
2124 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2125 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2126 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2127 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2128 [SVM_EXIT_VMLOAD] = vmload_interception,
2129 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2130 [SVM_EXIT_STGI] = stgi_interception,
2131 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2132 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2133 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2134 [SVM_EXIT_MONITOR] = invalid_op_interception,
2135 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2136 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2137};
2138
04d2cc77 2139static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2140{
04d2cc77 2141 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2142 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2143
af9ca2d7
JR		 2144 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2145 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2146
cf74a78b
AG		 2147 if (is_nested(svm)) {
2148 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2149 exit_code, svm->vmcb->control.exit_info_1,
2150 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2151 if (nested_svm_exit_handled(svm, true)) {
2152 nested_svm_vmexit(svm);
2153 nsvm_printk("-> #VMEXIT\n");
2154 return 1;
2155 }
2156 }
2157
709ddebf
JR		 2158 if (npt_enabled) {
2159 int mmu_reload = 0;
2160 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2161 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2162 mmu_reload = 1;
2163 }
2164 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2165 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2166 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2167 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2168 kvm_inject_gp(vcpu, 0);
2169 return 1;
2170 }
2171 }
2172 if (mmu_reload) {
2173 kvm_mmu_reset_context(vcpu);
2174 kvm_mmu_load(vcpu);
2175 }
2176 }
2177
04d2cc77
AK		 2178 kvm_reput_irq(svm);
2179
2180 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2181 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2182 kvm_run->fail_entry.hardware_entry_failure_reason
2183 = svm->vmcb->control.exit_code;
2184 return 0;
2185 }
2186
a2fa3e9f 2187 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf
JR		 2188 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2189 exit_code != SVM_EXIT_NPF)
6aa8b732
AK		 2190 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2191 "exit_code 0x%x\n",
b8688d51 2192 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2193 exit_code);
2194
9d8f549d 2195 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2196 || !svm_exit_handlers[exit_code]) {
6aa8b732 2197 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2198 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2199 return 0;
2200 }
2201
e756fc62 2202 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2203}
2204
2205static void reload_tss(struct kvm_vcpu *vcpu)
2206{
2207 int cpu = raw_smp_processor_id();
2208
2209 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2210 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2211 load_TR_desc();
2212}
2213
e756fc62 2214static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2215{
2216 int cpu = raw_smp_processor_id();
2217
2218 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2219
a2fa3e9f 2220 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e756fc62 2221 if (svm->vcpu.cpu != cpu ||
a2fa3e9f 2222 svm->asid_generation != svm_data->asid_generation)
e756fc62 2223 new_asid(svm, svm_data);
6aa8b732
AK		 2224}
2225
2226
85f455f7 2227static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2228{
2229 struct vmcb_control_area *control;
2230
af9ca2d7
JR		 2231 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2232
fa89a817 2233 ++svm->vcpu.stat.irq_injections;
e756fc62 2234 control = &svm->vmcb->control;
85f455f7 2235 control->int_vector = irq;
6aa8b732
AK		 2236 control->int_ctl &= ~V_INTR_PRIO_MASK;
2237 control->int_ctl |= V_IRQ_MASK |
2238 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2239}
2240
2a8067f1
ED		 2241static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2242{
2243 struct vcpu_svm *svm = to_svm(vcpu);
2244
cf74a78b
AG		 2245 nested_svm_intr(svm);
2246
2a8067f1
ED		 2247 svm_inject_irq(svm, irq);
2248}
2249
aaacfc9a
JR		 2250static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2251{
2252 struct vcpu_svm *svm = to_svm(vcpu);
2253 struct vmcb *vmcb = svm->vmcb;
2254 int max_irr, tpr;
2255
2256 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2257 return;
2258
2259 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2260
2261 max_irr = kvm_lapic_find_highest_irr(vcpu);
2262 if (max_irr == -1)
2263 return;
2264
2265 tpr = kvm_lapic_get_cr8(vcpu) << 4;
2266
2267 if (tpr >= (max_irr & 0xf0))
2268 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2269}
2270
04d2cc77 2271static void svm_intr_assist(struct kvm_vcpu *vcpu)
6aa8b732 2272{
04d2cc77 2273 struct vcpu_svm *svm = to_svm(vcpu);
85f455f7
ED		 2274 struct vmcb *vmcb = svm->vmcb;
2275 int intr_vector = -1;
2276
2277 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2278 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2279 intr_vector = vmcb->control.exit_int_info &
2280 SVM_EVTINJ_VEC_MASK;
2281 vmcb->control.exit_int_info = 0;
2282 svm_inject_irq(svm, intr_vector);
aaacfc9a 2283 goto out;
85f455f7
ED		 2284 }
2285
2286 if (vmcb->control.int_ctl & V_IRQ_MASK)
aaacfc9a 2287 goto out;
85f455f7 2288
1b9778da 2289 if (!kvm_cpu_has_interrupt(vcpu))
aaacfc9a 2290 goto out;
85f455f7 2291
cf74a78b
AG		 2292 if (nested_svm_intr(svm))
2293 goto out;
2294
1371d904
AG		 2295 if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2296 goto out;
2297
85f455f7
ED		 2298 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2299 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2300 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2301 /* unable to deliver irq, set pending irq */
f0b85051 2302 svm_set_vintr(svm);
85f455f7 2303 svm_inject_irq(svm, 0x0);
aaacfc9a 2304 goto out;
85f455f7
ED		 2305 }
2306 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1b9778da 2307 intr_vector = kvm_cpu_get_interrupt(vcpu);
85f455f7 2308 svm_inject_irq(svm, intr_vector);
aaacfc9a
JR		 2309out:
2310 update_cr8_intercept(vcpu);
85f455f7
ED		 2311}
2312
2313static void kvm_reput_irq(struct vcpu_svm *svm)
2314{
e756fc62 2315 struct vmcb_control_area *control = &svm->vmcb->control;
6aa8b732 2316
7017fc3d
ED		 2317 if ((control->int_ctl & V_IRQ_MASK)
2318 && !irqchip_in_kernel(svm->vcpu.kvm)) {
6aa8b732 2319 control->int_ctl &= ~V_IRQ_MASK;
e756fc62 2320 push_irq(&svm->vcpu, control->int_vector);
6aa8b732 2321 }
c1150d8c 2322
ad312c7c 2323 svm->vcpu.arch.interrupt_window_open =
1371d904
AG		 2324 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2325 (svm->vcpu.arch.hflags & HF_GIF_MASK);
c1150d8c
DL		 2326}
2327
85f455f7
ED		 2328static void svm_do_inject_vector(struct vcpu_svm *svm)
2329{
2330 struct kvm_vcpu *vcpu = &svm->vcpu;
ad312c7c
ZX		 2331 int word_index = __ffs(vcpu->arch.irq_summary);
2332 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
85f455f7
ED		 2333 int irq = word_index * BITS_PER_LONG + bit_index;
2334
ad312c7c
ZX		 2335 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2336 if (!vcpu->arch.irq_pending[word_index])
2337 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7
ED		 2338 svm_inject_irq(svm, irq);
2339}
2340
04d2cc77 2341static void do_interrupt_requests(struct kvm_vcpu *vcpu,
c1150d8c
DL		 2342 struct kvm_run *kvm_run)
2343{
04d2cc77 2344 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2345 struct vmcb_control_area *control = &svm->vmcb->control;
c1150d8c 2346
cf74a78b
AG		 2347 if (nested_svm_intr(svm))
2348 return;
2349
ad312c7c 2350 svm->vcpu.arch.interrupt_window_open =
c1150d8c 2351 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1371d904
AG		 2352 (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2353 (svm->vcpu.arch.hflags & HF_GIF_MASK));
c1150d8c 2354
ad312c7c 2355 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
c1150d8c
DL		 2356 /*
2357 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2358 */
85f455f7 2359 svm_do_inject_vector(svm);
c1150d8c
DL		 2360
2361 /*
2362 * Interrupts blocked. Wait for unblock.
2363 */
ad312c7c
ZX		 2364 if (!svm->vcpu.arch.interrupt_window_open &&
2365 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
f0b85051
AG		 2366 svm_set_vintr(svm);
2367 else
2368 svm_clear_vintr(svm);
c1150d8c
DL		 2369}
2370
cbc94022
IE		 2371static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2372{
2373 return 0;
2374}
2375
d9e368d6
AK		 2376static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2377{
2378 force_new_asid(vcpu);
2379}
2380
04d2cc77
AK		 2381static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2382{
2383}
2384
d7bf8221
JR		 2385static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2386{
2387 struct vcpu_svm *svm = to_svm(vcpu);
2388
2389 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2390 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2391 kvm_lapic_set_tpr(vcpu, cr8);
2392 }
2393}
2394
649d6864
JR		 2395static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2396{
2397 struct vcpu_svm *svm = to_svm(vcpu);
2398 u64 cr8;
2399
2400 if (!irqchip_in_kernel(vcpu->kvm))
2401 return;
2402
2403 cr8 = kvm_get_cr8(vcpu);
2404 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2405 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2406}
2407
80e31d4f
AK		 2408#ifdef CONFIG_X86_64
2409#define R "r"
2410#else
2411#define R "e"
2412#endif
2413
04d2cc77 2414static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2415{
a2fa3e9f 2416 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2417 u16 fs_selector;
2418 u16 gs_selector;
2419 u16 ldt_selector;
d9e368d6 2420
5fdbf976
MT		 2421 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2422 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2423 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2424
e756fc62 2425 pre_svm_run(svm);
6aa8b732 2426
649d6864
JR		 2427 sync_lapic_to_cr8(vcpu);
2428
6aa8b732 2429 save_host_msrs(vcpu);
d6e88aec
AK		 2430 fs_selector = kvm_read_fs();
2431 gs_selector = kvm_read_gs();
2432 ldt_selector = kvm_read_ldt();
a2fa3e9f 2433 svm->host_cr2 = kvm_read_cr2();
3d6368ef
AG		 2434 if (!is_nested(svm))
2435 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2436 /* required for live migration with NPT */
2437 if (npt_enabled)
2438 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2439
04d2cc77
AK		 2440 clgi();
2441
2442 local_irq_enable();
36241b8c 2443
6aa8b732 2444 asm volatile (
80e31d4f
AK		 2445 "push %%"R"bp; \n\t"
2446 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2447 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2448 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2449 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2450 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2451 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2452#ifdef CONFIG_X86_64
fb3f0f51
RR		 2453 "mov %c[r8](%[svm]), %%r8 \n\t"
2454 "mov %c[r9](%[svm]), %%r9 \n\t"
2455 "mov %c[r10](%[svm]), %%r10 \n\t"
2456 "mov %c[r11](%[svm]), %%r11 \n\t"
2457 "mov %c[r12](%[svm]), %%r12 \n\t"
2458 "mov %c[r13](%[svm]), %%r13 \n\t"
2459 "mov %c[r14](%[svm]), %%r14 \n\t"
2460 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2461#endif
2462
6aa8b732 2463 /* Enter guest mode */
80e31d4f
AK		 2464 "push %%"R"ax \n\t"
2465 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2466 __ex(SVM_VMLOAD) "\n\t"
2467 __ex(SVM_VMRUN) "\n\t"
2468 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2469 "pop %%"R"ax \n\t"
6aa8b732
AK		 2470
2471 /* Save guest registers, load host registers */
80e31d4f
AK		 2472 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2473 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2474 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2475 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2476 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2477 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2478#ifdef CONFIG_X86_64
fb3f0f51
RR		 2479 "mov %%r8, %c[r8](%[svm]) \n\t"
2480 "mov %%r9, %c[r9](%[svm]) \n\t"
2481 "mov %%r10, %c[r10](%[svm]) \n\t"
2482 "mov %%r11, %c[r11](%[svm]) \n\t"
2483 "mov %%r12, %c[r12](%[svm]) \n\t"
2484 "mov %%r13, %c[r13](%[svm]) \n\t"
2485 "mov %%r14, %c[r14](%[svm]) \n\t"
2486 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2487#endif
80e31d4f 2488 "pop %%"R"bp"
6aa8b732 2489 :
fb3f0f51 2490 : [svm]"a"(svm),
6aa8b732 2491 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2492 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2493 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2494 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2495 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2496 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2497 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2498#ifdef CONFIG_X86_64
ad312c7c
ZX		 2499 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2500 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2501 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2502 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2503 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2504 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2505 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2506 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2507#endif
54a08c04 2508 : "cc", "memory"
80e31d4f 2509 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2510#ifdef CONFIG_X86_64
54a08c04
LV		 2511 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2512#endif
2513 );
6aa8b732 2514
ad312c7c 2515 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2516 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2517 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2518 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2519
a2fa3e9f 2520 kvm_write_cr2(svm->host_cr2);
6aa8b732 2521
d6e88aec
AK		 2522 kvm_load_fs(fs_selector);
2523 kvm_load_gs(gs_selector);
2524 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2525 load_host_msrs(vcpu);
2526
2527 reload_tss(vcpu);
2528
56ba47dd
AK		 2529 local_irq_disable();
2530
2531 stgi();
2532
d7bf8221
JR		 2533 sync_cr8_to_lapic(vcpu);
2534
a2fa3e9f 2535 svm->next_rip = 0;
6aa8b732
AK		 2536}
2537
80e31d4f
AK		 2538#undef R
2539
6aa8b732
AK		 2540static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2541{
a2fa3e9f
GH		 2542 struct vcpu_svm *svm = to_svm(vcpu);
2543
709ddebf
JR		 2544 if (npt_enabled) {
2545 svm->vmcb->control.nested_cr3 = root;
2546 force_new_asid(vcpu);
2547 return;
2548 }
2549
a2fa3e9f 2550 svm->vmcb->save.cr3 = root;
6aa8b732 2551 force_new_asid(vcpu);
7807fa6c
AL		 2552
2553 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2554 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2555 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2556 vcpu->fpu_active = 0;
2557 }
6aa8b732
AK		 2558}
2559
6aa8b732
AK		 2560static int is_disabled(void)
2561{
6031a61c
JR		 2562 u64 vm_cr;
2563
2564 rdmsrl(MSR_VM_CR, vm_cr);
2565 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2566 return 1;
2567
6aa8b732
AK		 2568 return 0;
2569}
2570
102d8325
IM		 2571static void
2572svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2573{
2574 /*
2575 * Patch in the VMMCALL instruction:
2576 */
2577 hypercall[0] = 0x0f;
2578 hypercall[1] = 0x01;
2579 hypercall[2] = 0xd9;
102d8325
IM		 2580}
2581
002c7f7c
YS		 2582static void svm_check_processor_compat(void *rtn)
2583{
2584 *(int *)rtn = 0;
2585}
2586
774ead3a
AK		 2587static bool svm_cpu_has_accelerated_tpr(void)
2588{
2589 return false;
2590}
2591
67253af5
SY		 2592static int get_npt_level(void)
2593{
2594#ifdef CONFIG_X86_64
2595 return PT64_ROOT_LEVEL;
2596#else
2597 return PT32E_ROOT_LEVEL;
2598#endif
2599}
2600
64d4d521
SY		 2601static int svm_get_mt_mask_shift(void)
2602{
2603 return 0;
2604}
2605
cbdd1bea 2606static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2607 .cpu_has_kvm_support = has_svm,
2608 .disabled_by_bios = is_disabled,
2609 .hardware_setup = svm_hardware_setup,
2610 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2611 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2612 .hardware_enable = svm_hardware_enable,
2613 .hardware_disable = svm_hardware_disable,
774ead3a 2614 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2615
2616 .vcpu_create = svm_create_vcpu,
2617 .vcpu_free = svm_free_vcpu,
04d2cc77 2618 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2619
04d2cc77 2620 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2621 .vcpu_load = svm_vcpu_load,
2622 .vcpu_put = svm_vcpu_put,
2623
2624 .set_guest_debug = svm_guest_debug,
2625 .get_msr = svm_get_msr,
2626 .set_msr = svm_set_msr,
2627 .get_segment_base = svm_get_segment_base,
2628 .get_segment = svm_get_segment,
2629 .set_segment = svm_set_segment,
2e4d2653 2630 .get_cpl = svm_get_cpl,
1747fb71 2631 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2632 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2633 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2634 .set_cr3 = svm_set_cr3,
2635 .set_cr4 = svm_set_cr4,
2636 .set_efer = svm_set_efer,
2637 .get_idt = svm_get_idt,
2638 .set_idt = svm_set_idt,
2639 .get_gdt = svm_get_gdt,
2640 .set_gdt = svm_set_gdt,
2641 .get_dr = svm_get_dr,
2642 .set_dr = svm_set_dr,
6aa8b732
AK		 2643 .get_rflags = svm_get_rflags,
2644 .set_rflags = svm_set_rflags,
2645
6aa8b732 2646 .tlb_flush = svm_flush_tlb,
6aa8b732 2647
6aa8b732 2648 .run = svm_vcpu_run,
04d2cc77 2649 .handle_exit = handle_exit,
6aa8b732 2650 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2651 .patch_hypercall = svm_patch_hypercall,
2a8067f1
ED		 2652 .get_irq = svm_get_irq,
2653 .set_irq = svm_set_irq,
298101da
AK		 2654 .queue_exception = svm_queue_exception,
2655 .exception_injected = svm_exception_injected,
04d2cc77
AK		 2656 .inject_pending_irq = svm_intr_assist,
2657 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2658
2659 .set_tss_addr = svm_set_tss_addr,
67253af5 2660 .get_tdp_level = get_npt_level,
64d4d521 2661 .get_mt_mask_shift = svm_get_mt_mask_shift,
6aa8b732
AK		 2662};
2663
2664static int __init svm_init(void)
2665{
cb498ea2 2666 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2667 THIS_MODULE);
6aa8b732
AK		 2668}
2669
2670static void __exit svm_exit(void)
2671{
cb498ea2 2672 kvm_exit();
6aa8b732
AK		 2673}
2674
2675module_init(svm_init)
2676module_exit(svm_exit)
Ubuntu Artful kernel mirror