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KVM: SVM: complete interrupts after handling nested exits
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
24e09cbf
JR		 50#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
c0725420
AG		 52/* Turn on to get debugging output*/
53/* #define NESTED_DEBUG */
54
55#ifdef NESTED_DEBUG
56#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57#else
58#define nsvm_printk(fmt, args...) do {} while(0)
59#endif
60
6c8166a7
AK		 61static const u32 host_save_user_msrs[] = {
62#ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65#endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67};
68
69#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71struct kvm_vcpu;
72
73struct vcpu_svm {
74 struct kvm_vcpu vcpu;
75 struct vmcb *vmcb;
76 unsigned long vmcb_pa;
77 struct svm_cpu_data *svm_data;
78 uint64_t asid_generation;
79 uint64_t sysenter_esp;
80 uint64_t sysenter_eip;
81
82 u64 next_rip;
83
84 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
85 u64 host_gs_base;
6c8166a7
AK		 86
87 u32 *msrpm;
88 struct vmcb *hsave;
89 u64 hsave_msr;
90
91 u64 nested_vmcb;
92
93 /* These are the merged vectors */
94 u32 *nested_msrpm;
95
96 /* gpa pointers to the real vectors */
97 u64 nested_vmcb_msrpm;
98};
99
709ddebf
JR		 100/* enable NPT for AMD64 and X86 with PAE */
101#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
102static bool npt_enabled = true;
103#else
e3da3acd 104static bool npt_enabled = false;
709ddebf 105#endif
6c7dac72
JR		 106static int npt = 1;
107
108module_param(npt, int, S_IRUGO);
e3da3acd 109
236de055
AG		 110static int nested = 0;
111module_param(nested, int, S_IRUGO);
112
44874f84 113static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 114static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 115
cf74a78b
AG		 116static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
117static int nested_svm_vmexit(struct vcpu_svm *svm);
118static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
119 void *arg2, void *opaque);
120static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
121 bool has_error_code, u32 error_code);
122
a2fa3e9f
GH		 123static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
124{
fb3f0f51 125 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 126}
127
3d6368ef
AG		 128static inline bool is_nested(struct vcpu_svm *svm)
129{
130 return svm->nested_vmcb;
131}
132
2af9194d
JR		 133static inline void enable_gif(struct vcpu_svm *svm)
134{
135 svm->vcpu.arch.hflags |= HF_GIF_MASK;
136}
137
138static inline void disable_gif(struct vcpu_svm *svm)
139{
140 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
141}
142
143static inline bool gif_set(struct vcpu_svm *svm)
144{
145 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
146}
147
4866d5e3 148static unsigned long iopm_base;
6aa8b732
AK		 149
150struct kvm_ldttss_desc {
151 u16 limit0;
152 u16 base0;
153 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
154 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
155 u32 base3;
156 u32 zero1;
157} __attribute__((packed));
158
159struct svm_cpu_data {
160 int cpu;
161
5008fdf5
AK		 162 u64 asid_generation;
163 u32 max_asid;
164 u32 next_asid;
6aa8b732
AK		 165 struct kvm_ldttss_desc *tss_desc;
166
167 struct page *save_area;
168};
169
170static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 171static uint32_t svm_features;
6aa8b732
AK		 172
173struct svm_init_data {
174 int cpu;
175 int r;
176};
177
178static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
179
9d8f549d 180#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 181#define MSRS_RANGE_SIZE 2048
182#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
183
184#define MAX_INST_SIZE 15
185
80b7706e
JR		 186static inline u32 svm_has(u32 feat)
187{
188 return svm_features & feat;
189}
190
6aa8b732
AK		 191static inline void clgi(void)
192{
4ecac3fd 193 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 194}
195
196static inline void stgi(void)
197{
4ecac3fd 198 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 199}
200
201static inline void invlpga(unsigned long addr, u32 asid)
202{
4ecac3fd 203 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 204}
205
6aa8b732
AK		 206static inline void force_new_asid(struct kvm_vcpu *vcpu)
207{
a2fa3e9f 208 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 209}
210
211static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
212{
213 force_new_asid(vcpu);
214}
215
216static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
217{
709ddebf 218 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 219 efer &= ~EFER_LME;
6aa8b732 220
9962d032 221 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 222 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 223}
224
298101da
AK		 225static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
226 bool has_error_code, u32 error_code)
227{
228 struct vcpu_svm *svm = to_svm(vcpu);
229
cf74a78b
AG		 230 /* If we are within a nested VM we'd better #VMEXIT and let the
231 guest handle the exception */
232 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
233 return;
234
298101da
AK		 235 svm->vmcb->control.event_inj = nr
236 | SVM_EVTINJ_VALID
237 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
238 | SVM_EVTINJ_TYPE_EXEPT;
239 svm->vmcb->control.event_inj_err = error_code;
240}
241
6aa8b732
AK		 242static int is_external_interrupt(u32 info)
243{
244 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
245 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
246}
247
2809f5d2
GC		 248static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
249{
250 struct vcpu_svm *svm = to_svm(vcpu);
251 u32 ret = 0;
252
253 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
254 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
255 return ret & mask;
256}
257
258static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
259{
260 struct vcpu_svm *svm = to_svm(vcpu);
261
262 if (mask == 0)
263 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
264 else
265 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
266
267}
268
6aa8b732
AK		 269static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
270{
a2fa3e9f
GH		 271 struct vcpu_svm *svm = to_svm(vcpu);
272
273 if (!svm->next_rip) {
f629cf84
GN		 274 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
275 EMULATE_DONE)
276 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 277 return;
278 }
5fdbf976
MT		 279 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
280 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
281 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 282
5fdbf976 283 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 284 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 285}
286
287static int has_svm(void)
288{
63d1142f 289 const char *msg;
6aa8b732 290
63d1142f 291 if (!cpu_has_svm(&msg)) {
ff81ff10 292 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 293 return 0;
294 }
295
6aa8b732
AK		 296 return 1;
297}
298
299static void svm_hardware_disable(void *garbage)
300{
2c8dceeb 301 cpu_svm_disable();
6aa8b732
AK		 302}
303
304static void svm_hardware_enable(void *garbage)
305{
306
307 struct svm_cpu_data *svm_data;
308 uint64_t efer;
b792c344 309 struct descriptor_table gdt_descr;
6aa8b732
AK		 310 struct desc_struct *gdt;
311 int me = raw_smp_processor_id();
312
313 if (!has_svm()) {
314 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
315 return;
316 }
317 svm_data = per_cpu(svm_data, me);
318
319 if (!svm_data) {
320 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
321 me);
322 return;
323 }
324
325 svm_data->asid_generation = 1;
326 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
327 svm_data->next_asid = svm_data->max_asid + 1;
328
b792c344
AM		 329 kvm_get_gdt(&gdt_descr);
330 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 331 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
332
333 rdmsrl(MSR_EFER, efer);
9962d032 334 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 335
336 wrmsrl(MSR_VM_HSAVE_PA,
337 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
338}
339
0da1db75
JR		 340static void svm_cpu_uninit(int cpu)
341{
342 struct svm_cpu_data *svm_data
343 = per_cpu(svm_data, raw_smp_processor_id());
344
345 if (!svm_data)
346 return;
347
348 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
349 __free_page(svm_data->save_area);
350 kfree(svm_data);
351}
352
6aa8b732
AK		 353static int svm_cpu_init(int cpu)
354{
355 struct svm_cpu_data *svm_data;
356 int r;
357
358 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
359 if (!svm_data)
360 return -ENOMEM;
361 svm_data->cpu = cpu;
362 svm_data->save_area = alloc_page(GFP_KERNEL);
363 r = -ENOMEM;
364 if (!svm_data->save_area)
365 goto err_1;
366
367 per_cpu(svm_data, cpu) = svm_data;
368
369 return 0;
370
371err_1:
372 kfree(svm_data);
373 return r;
374
375}
376
bfc733a7
RR		 377static void set_msr_interception(u32 *msrpm, unsigned msr,
378 int read, int write)
6aa8b732
AK		 379{
380 int i;
381
382 for (i = 0; i < NUM_MSR_MAPS; i++) {
383 if (msr >= msrpm_ranges[i] &&
384 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
385 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
386 msrpm_ranges[i]) * 2;
387
388 u32 *base = msrpm + (msr_offset / 32);
389 u32 msr_shift = msr_offset % 32;
390 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
391 *base = (*base & ~(0x3 << msr_shift)) |
392 (mask << msr_shift);
bfc733a7 393 return;
6aa8b732
AK		 394 }
395 }
bfc733a7 396 BUG();
6aa8b732
AK		 397}
398
f65c229c
JR		 399static void svm_vcpu_init_msrpm(u32 *msrpm)
400{
401 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
402
403#ifdef CONFIG_X86_64
404 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
405 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
406 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
407 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
408 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
409 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
410#endif
411 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
412 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 413}
414
24e09cbf
JR		 415static void svm_enable_lbrv(struct vcpu_svm *svm)
416{
417 u32 *msrpm = svm->msrpm;
418
419 svm->vmcb->control.lbr_ctl = 1;
420 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
421 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
422 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
423 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
424}
425
426static void svm_disable_lbrv(struct vcpu_svm *svm)
427{
428 u32 *msrpm = svm->msrpm;
429
430 svm->vmcb->control.lbr_ctl = 0;
431 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
432 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
433 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
434 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
435}
436
6aa8b732
AK		 437static __init int svm_hardware_setup(void)
438{
439 int cpu;
440 struct page *iopm_pages;
f65c229c 441 void *iopm_va;
6aa8b732
AK		 442 int r;
443
6aa8b732
AK		 444 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
445
446 if (!iopm_pages)
447 return -ENOMEM;
c8681339
AL		 448
449 iopm_va = page_address(iopm_pages);
450 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 451 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
452
50a37eb4
JR		 453 if (boot_cpu_has(X86_FEATURE_NX))
454 kvm_enable_efer_bits(EFER_NX);
455
1b2fd70c
AG		 456 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
457 kvm_enable_efer_bits(EFER_FFXSR);
458
236de055
AG		 459 if (nested) {
460 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
461 kvm_enable_efer_bits(EFER_SVME);
462 }
463
6aa8b732
AK		 464 for_each_online_cpu(cpu) {
465 r = svm_cpu_init(cpu);
466 if (r)
f65c229c 467 goto err;
6aa8b732 468 }
33bd6a0b
JR		 469
470 svm_features = cpuid_edx(SVM_CPUID_FUNC);
471
e3da3acd
JR		 472 if (!svm_has(SVM_FEATURE_NPT))
473 npt_enabled = false;
474
6c7dac72
JR		 475 if (npt_enabled && !npt) {
476 printk(KERN_INFO "kvm: Nested Paging disabled\n");
477 npt_enabled = false;
478 }
479
18552672 480 if (npt_enabled) {
e3da3acd 481 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 482 kvm_enable_tdp();
5f4cb662
JR		 483 } else
484 kvm_disable_tdp();
e3da3acd 485
6aa8b732
AK		 486 return 0;
487
f65c229c 488err:
6aa8b732
AK		 489 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
490 iopm_base = 0;
491 return r;
492}
493
494static __exit void svm_hardware_unsetup(void)
495{
0da1db75
JR		 496 int cpu;
497
498 for_each_online_cpu(cpu)
499 svm_cpu_uninit(cpu);
500
6aa8b732 501 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 502 iopm_base = 0;
6aa8b732
AK		 503}
504
505static void init_seg(struct vmcb_seg *seg)
506{
507 seg->selector = 0;
508 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
509 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
510 seg->limit = 0xffff;
511 seg->base = 0;
512}
513
514static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
515{
516 seg->selector = 0;
517 seg->attrib = SVM_SELECTOR_P_MASK | type;
518 seg->limit = 0xffff;
519 seg->base = 0;
520}
521
e6101a96 522static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 523{
e6101a96
JR		 524 struct vmcb_control_area *control = &svm->vmcb->control;
525 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 526
527 control->intercept_cr_read = INTERCEPT_CR0_MASK |
528 INTERCEPT_CR3_MASK |
649d6864 529 INTERCEPT_CR4_MASK;
6aa8b732
AK		 530
531 control->intercept_cr_write = INTERCEPT_CR0_MASK |
532 INTERCEPT_CR3_MASK |
80a8119c
AK		 533 INTERCEPT_CR4_MASK |
534 INTERCEPT_CR8_MASK;
6aa8b732
AK		 535
536 control->intercept_dr_read = INTERCEPT_DR0_MASK |
537 INTERCEPT_DR1_MASK |
538 INTERCEPT_DR2_MASK |
539 INTERCEPT_DR3_MASK;
540
541 control->intercept_dr_write = INTERCEPT_DR0_MASK |
542 INTERCEPT_DR1_MASK |
543 INTERCEPT_DR2_MASK |
544 INTERCEPT_DR3_MASK |
545 INTERCEPT_DR5_MASK |
546 INTERCEPT_DR7_MASK;
547
7aa81cc0 548 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 549 (1 << UD_VECTOR) |
550 (1 << MC_VECTOR);
6aa8b732
AK		 551
552
553 control->intercept = (1ULL << INTERCEPT_INTR) |
554 (1ULL << INTERCEPT_NMI) |
0152527b 555 (1ULL << INTERCEPT_SMI) |
6aa8b732 556 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 557 (1ULL << INTERCEPT_INVD) |
6aa8b732 558 (1ULL << INTERCEPT_HLT) |
a7052897 559 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 560 (1ULL << INTERCEPT_INVLPGA) |
561 (1ULL << INTERCEPT_IOIO_PROT) |
562 (1ULL << INTERCEPT_MSR_PROT) |
563 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 564 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 565 (1ULL << INTERCEPT_VMRUN) |
566 (1ULL << INTERCEPT_VMMCALL) |
567 (1ULL << INTERCEPT_VMLOAD) |
568 (1ULL << INTERCEPT_VMSAVE) |
569 (1ULL << INTERCEPT_STGI) |
570 (1ULL << INTERCEPT_CLGI) |
916ce236 571 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 572 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 573 (1ULL << INTERCEPT_MONITOR) |
574 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 575
576 control->iopm_base_pa = iopm_base;
f65c229c 577 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 578 control->tsc_offset = 0;
6aa8b732
AK		 579 control->int_ctl = V_INTR_MASKING_MASK;
580
581 init_seg(&save->es);
582 init_seg(&save->ss);
583 init_seg(&save->ds);
584 init_seg(&save->fs);
585 init_seg(&save->gs);
586
587 save->cs.selector = 0xf000;
588 /* Executable/Readable Code Segment */
589 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
590 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
591 save->cs.limit = 0xffff;
d92899a0
AK		 592 /*
593 * cs.base should really be 0xffff0000, but vmx can't handle that, so
594 * be consistent with it.
595 *
596 * Replace when we have real mode working for vmx.
597 */
598 save->cs.base = 0xf0000;
6aa8b732
AK		 599
600 save->gdtr.limit = 0xffff;
601 save->idtr.limit = 0xffff;
602
603 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
604 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
605
9962d032 606 save->efer = EFER_SVME;
d77c26fc 607 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 608 save->dr7 = 0x400;
609 save->rflags = 2;
610 save->rip = 0x0000fff0;
5fdbf976 611 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 612
613 /*
614 * cr0 val on cpu init should be 0x60000010, we enable cpu
615 * cache by default. the orderly way is to enable cache in bios.
616 */
707d92fa 617 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 618 save->cr4 = X86_CR4_PAE;
6aa8b732 619 /* rdx = ?? */
709ddebf
JR		 620
621 if (npt_enabled) {
622 /* Setup VMCB for Nested Paging */
623 control->nested_ctl = 1;
a7052897
MT		 624 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
625 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 626 control->intercept_exceptions &= ~(1 << PF_VECTOR);
627 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
628 INTERCEPT_CR3_MASK);
629 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
630 INTERCEPT_CR3_MASK);
631 save->g_pat = 0x0007040600070406ULL;
632 /* enable caching because the QEMU Bios doesn't enable it */
633 save->cr0 = X86_CR0_ET;
634 save->cr3 = 0;
635 save->cr4 = 0;
636 }
a79d2f18 637 force_new_asid(&svm->vcpu);
1371d904 638
3d6368ef 639 svm->nested_vmcb = 0;
2af9194d
JR		 640 svm->vcpu.arch.hflags = 0;
641
642 enable_gif(svm);
6aa8b732
AK		 643}
644
e00c8cf2 645static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 646{
647 struct vcpu_svm *svm = to_svm(vcpu);
648
e6101a96 649 init_vmcb(svm);
70433389 650
c5af89b6 651 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 652 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 653 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
654 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 655 }
5fdbf976
MT		 656 vcpu->arch.regs_avail = ~0;
657 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 658
659 return 0;
04d2cc77
AK		 660}
661
fb3f0f51 662static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 663{
a2fa3e9f 664 struct vcpu_svm *svm;
6aa8b732 665 struct page *page;
f65c229c 666 struct page *msrpm_pages;
b286d5d8 667 struct page *hsave_page;
3d6368ef 668 struct page *nested_msrpm_pages;
fb3f0f51 669 int err;
6aa8b732 670
c16f862d 671 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 672 if (!svm) {
673 err = -ENOMEM;
674 goto out;
675 }
676
677 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
678 if (err)
679 goto free_svm;
680
6aa8b732 681 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 682 if (!page) {
683 err = -ENOMEM;
684 goto uninit;
685 }
6aa8b732 686
f65c229c
JR		 687 err = -ENOMEM;
688 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
689 if (!msrpm_pages)
690 goto uninit;
3d6368ef
AG		 691
692 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
693 if (!nested_msrpm_pages)
694 goto uninit;
695
f65c229c
JR		 696 svm->msrpm = page_address(msrpm_pages);
697 svm_vcpu_init_msrpm(svm->msrpm);
698
b286d5d8
AG		 699 hsave_page = alloc_page(GFP_KERNEL);
700 if (!hsave_page)
701 goto uninit;
702 svm->hsave = page_address(hsave_page);
703
3d6368ef
AG		 704 svm->nested_msrpm = page_address(nested_msrpm_pages);
705
a2fa3e9f
GH		 706 svm->vmcb = page_address(page);
707 clear_page(svm->vmcb);
708 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
709 svm->asid_generation = 0;
e6101a96 710 init_vmcb(svm);
a2fa3e9f 711
fb3f0f51
RR		 712 fx_init(&svm->vcpu);
713 svm->vcpu.fpu_active = 1;
ad312c7c 714 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 715 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 716 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 717
fb3f0f51 718 return &svm->vcpu;
36241b8c 719
fb3f0f51
RR		 720uninit:
721 kvm_vcpu_uninit(&svm->vcpu);
722free_svm:
a4770347 723 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 724out:
725 return ERR_PTR(err);
6aa8b732
AK		 726}
727
728static void svm_free_vcpu(struct kvm_vcpu *vcpu)
729{
a2fa3e9f
GH		 730 struct vcpu_svm *svm = to_svm(vcpu);
731
fb3f0f51 732 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 733 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 734 __free_page(virt_to_page(svm->hsave));
3d6368ef 735 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 736 kvm_vcpu_uninit(vcpu);
a4770347 737 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 738}
739
15ad7146 740static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 741{
a2fa3e9f 742 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 743 int i;
0cc5064d 744
0cc5064d
AK		 745 if (unlikely(cpu != vcpu->cpu)) {
746 u64 tsc_this, delta;
747
748 /*
749 * Make sure that the guest sees a monotonically
750 * increasing TSC.
751 */
752 rdtscll(tsc_this);
ad312c7c 753 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 754 svm->vmcb->control.tsc_offset += delta;
0cc5064d 755 vcpu->cpu = cpu;
2f599714 756 kvm_migrate_timers(vcpu);
4b656b12 757 svm->asid_generation = 0;
0cc5064d 758 }
94dfbdb3
AL		 759
760 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 761 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 762}
763
764static void svm_vcpu_put(struct kvm_vcpu *vcpu)
765{
a2fa3e9f 766 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 767 int i;
768
e1beb1d3 769 ++vcpu->stat.host_state_reload;
94dfbdb3 770 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 771 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 772
ad312c7c 773 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 774}
775
6aa8b732
AK		 776static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
777{
a2fa3e9f 778 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 779}
780
781static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
782{
a2fa3e9f 783 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 784}
785
6de4f3ad
AK		 786static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
787{
788 switch (reg) {
789 case VCPU_EXREG_PDPTR:
790 BUG_ON(!npt_enabled);
791 load_pdptrs(vcpu, vcpu->arch.cr3);
792 break;
793 default:
794 BUG();
795 }
796}
797
f0b85051
AG		 798static void svm_set_vintr(struct vcpu_svm *svm)
799{
800 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
801}
802
803static void svm_clear_vintr(struct vcpu_svm *svm)
804{
805 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
806}
807
6aa8b732
AK		 808static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
809{
a2fa3e9f 810 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 811
812 switch (seg) {
813 case VCPU_SREG_CS: return &save->cs;
814 case VCPU_SREG_DS: return &save->ds;
815 case VCPU_SREG_ES: return &save->es;
816 case VCPU_SREG_FS: return &save->fs;
817 case VCPU_SREG_GS: return &save->gs;
818 case VCPU_SREG_SS: return &save->ss;
819 case VCPU_SREG_TR: return &save->tr;
820 case VCPU_SREG_LDTR: return &save->ldtr;
821 }
822 BUG();
8b6d44c7 823 return NULL;
6aa8b732
AK		 824}
825
826static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
827{
828 struct vmcb_seg *s = svm_seg(vcpu, seg);
829
830 return s->base;
831}
832
833static void svm_get_segment(struct kvm_vcpu *vcpu,
834 struct kvm_segment *var, int seg)
835{
836 struct vmcb_seg *s = svm_seg(vcpu, seg);
837
838 var->base = s->base;
839 var->limit = s->limit;
840 var->selector = s->selector;
841 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
842 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
843 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
844 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
845 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
846 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
847 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
848 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 849
19bca6ab
AP		 850 /* AMD's VMCB does not have an explicit unusable field, so emulate it
851 * for cross vendor migration purposes by "not present"
852 */
853 var->unusable = !var->present || (var->type == 0);
854
1fbdc7a5
AP		 855 switch (seg) {
856 case VCPU_SREG_CS:
857 /*
858 * SVM always stores 0 for the 'G' bit in the CS selector in
859 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
860 * Intel's VMENTRY has a check on the 'G' bit.
861 */
25022acc 862 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 863 break;
864 case VCPU_SREG_TR:
865 /*
866 * Work around a bug where the busy flag in the tr selector
867 * isn't exposed
868 */
c0d09828 869 var->type |= 0x2;
1fbdc7a5
AP		 870 break;
871 case VCPU_SREG_DS:
872 case VCPU_SREG_ES:
873 case VCPU_SREG_FS:
874 case VCPU_SREG_GS:
875 /*
876 * The accessed bit must always be set in the segment
877 * descriptor cache, although it can be cleared in the
878 * descriptor, the cached bit always remains at 1. Since
879 * Intel has a check on this, set it here to support
880 * cross-vendor migration.
881 */
882 if (!var->unusable)
883 var->type |= 0x1;
884 break;
b586eb02
AP		 885 case VCPU_SREG_SS:
886 /* On AMD CPUs sometimes the DB bit in the segment
887 * descriptor is left as 1, although the whole segment has
888 * been made unusable. Clear it here to pass an Intel VMX
889 * entry check when cross vendor migrating.
890 */
891 if (var->unusable)
892 var->db = 0;
893 break;
1fbdc7a5 894 }
6aa8b732
AK		 895}
896
2e4d2653
IE		 897static int svm_get_cpl(struct kvm_vcpu *vcpu)
898{
899 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
900
901 return save->cpl;
902}
903
6aa8b732
AK		 904static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
905{
a2fa3e9f
GH		 906 struct vcpu_svm *svm = to_svm(vcpu);
907
908 dt->limit = svm->vmcb->save.idtr.limit;
909 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 910}
911
912static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
913{
a2fa3e9f
GH		 914 struct vcpu_svm *svm = to_svm(vcpu);
915
916 svm->vmcb->save.idtr.limit = dt->limit;
917 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 918}
919
920static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
921{
a2fa3e9f
GH		 922 struct vcpu_svm *svm = to_svm(vcpu);
923
924 dt->limit = svm->vmcb->save.gdtr.limit;
925 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 926}
927
928static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
929{
a2fa3e9f
GH		 930 struct vcpu_svm *svm = to_svm(vcpu);
931
932 svm->vmcb->save.gdtr.limit = dt->limit;
933 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 934}
935
25c4c276 936static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 937{
938}
939
6aa8b732
AK		 940static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
941{
a2fa3e9f
GH		 942 struct vcpu_svm *svm = to_svm(vcpu);
943
05b3e0c2 944#ifdef CONFIG_X86_64
ad312c7c 945 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 946 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 947 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 948 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 949 }
950
d77c26fc 951 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 952 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 953 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 954 }
955 }
956#endif
709ddebf
JR		 957 if (npt_enabled)
958 goto set;
959
ad312c7c 960 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 961 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 962 vcpu->fpu_active = 1;
963 }
964
ad312c7c 965 vcpu->arch.cr0 = cr0;
707d92fa 966 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 967 if (!vcpu->fpu_active) {
968 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 969 cr0 |= X86_CR0_TS;
6b390b63 970 }
709ddebf
JR		 971set:
972 /*
973 * re-enable caching here because the QEMU bios
974 * does not do it - this results in some delay at
975 * reboot
976 */
977 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 978 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 979}
980
981static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
982{
6394b649 983 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 984 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
985
986 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
987 force_new_asid(vcpu);
6394b649 988
ec077263
JR		 989 vcpu->arch.cr4 = cr4;
990 if (!npt_enabled)
991 cr4 |= X86_CR4_PAE;
6394b649 992 cr4 |= host_cr4_mce;
ec077263 993 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 994}
995
996static void svm_set_segment(struct kvm_vcpu *vcpu,
997 struct kvm_segment *var, int seg)
998{
a2fa3e9f 999 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1000 struct vmcb_seg *s = svm_seg(vcpu, seg);
1001
1002 s->base = var->base;
1003 s->limit = var->limit;
1004 s->selector = var->selector;
1005 if (var->unusable)
1006 s->attrib = 0;
1007 else {
1008 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1009 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1010 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1011 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1012 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1013 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1014 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1015 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1016 }
1017 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1018 svm->vmcb->save.cpl
1019 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1020 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1021
1022}
1023
44c11430 1024static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1025{
d0bfb940
JK		 1026 struct vcpu_svm *svm = to_svm(vcpu);
1027
d0bfb940
JK		 1028 svm->vmcb->control.intercept_exceptions &=
1029 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1030
1031 if (vcpu->arch.singlestep)
1032 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1033
d0bfb940
JK		 1034 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1035 if (vcpu->guest_debug &
1036 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1037 svm->vmcb->control.intercept_exceptions |=
1038 1 << DB_VECTOR;
1039 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1040 svm->vmcb->control.intercept_exceptions |=
1041 1 << BP_VECTOR;
1042 } else
1043 vcpu->guest_debug = 0;
44c11430
GN		 1044}
1045
1046static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1047{
1048 int old_debug = vcpu->guest_debug;
1049 struct vcpu_svm *svm = to_svm(vcpu);
1050
1051 vcpu->guest_debug = dbg->control;
1052
1053 update_db_intercept(vcpu);
d0bfb940 1054
ae675ef0
JK		 1055 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1056 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1057 else
1058 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1059
d0bfb940
JK		 1060 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1061 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1062 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1063 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1064
1065 return 0;
6aa8b732
AK		 1066}
1067
1068static void load_host_msrs(struct kvm_vcpu *vcpu)
1069{
94dfbdb3 1070#ifdef CONFIG_X86_64
a2fa3e9f 1071 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1072#endif
6aa8b732
AK		 1073}
1074
1075static void save_host_msrs(struct kvm_vcpu *vcpu)
1076{
94dfbdb3 1077#ifdef CONFIG_X86_64
a2fa3e9f 1078 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1079#endif
6aa8b732
AK		 1080}
1081
e756fc62 1082static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1083{
1084 if (svm_data->next_asid > svm_data->max_asid) {
1085 ++svm_data->asid_generation;
1086 svm_data->next_asid = 1;
a2fa3e9f 1087 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1088 }
1089
a2fa3e9f
GH		 1090 svm->asid_generation = svm_data->asid_generation;
1091 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1092}
1093
6aa8b732
AK		 1094static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1095{
42dbaa5a
JK		 1096 struct vcpu_svm *svm = to_svm(vcpu);
1097 unsigned long val;
1098
1099 switch (dr) {
1100 case 0 ... 3:
1101 val = vcpu->arch.db[dr];
1102 break;
1103 case 6:
1104 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1105 val = vcpu->arch.dr6;
1106 else
1107 val = svm->vmcb->save.dr6;
1108 break;
1109 case 7:
1110 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1111 val = vcpu->arch.dr7;
1112 else
1113 val = svm->vmcb->save.dr7;
1114 break;
1115 default:
1116 val = 0;
1117 }
1118
af9ca2d7 1119 return val;
6aa8b732
AK		 1120}
1121
1122static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1123 int *exception)
1124{
a2fa3e9f
GH		 1125 struct vcpu_svm *svm = to_svm(vcpu);
1126
42dbaa5a 1127 *exception = 0;
6aa8b732
AK		 1128
1129 switch (dr) {
1130 case 0 ... 3:
42dbaa5a
JK		 1131 vcpu->arch.db[dr] = value;
1132 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1133 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1134 return;
1135 case 4 ... 5:
42dbaa5a 1136 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1137 *exception = UD_VECTOR;
42dbaa5a
JK		 1138 return;
1139 case 6:
1140 if (value & 0xffffffff00000000ULL) {
1141 *exception = GP_VECTOR;
6aa8b732
AK		 1142 return;
1143 }
42dbaa5a
JK		 1144 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1145 return;
1146 case 7:
1147 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1148 *exception = GP_VECTOR;
1149 return;
1150 }
42dbaa5a
JK		 1151 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1152 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1153 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1154 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1155 }
6aa8b732 1156 return;
6aa8b732 1157 default:
42dbaa5a 1158 /* FIXME: Possible case? */
6aa8b732 1159 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1160 __func__, dr);
6aa8b732
AK		 1161 *exception = UD_VECTOR;
1162 return;
1163 }
1164}
1165
e756fc62 1166static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1167{
6aa8b732
AK		 1168 u64 fault_address;
1169 u32 error_code;
6aa8b732 1170
a2fa3e9f
GH		 1171 fault_address = svm->vmcb->control.exit_info_2;
1172 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1173
229456fc 1174 trace_kvm_page_fault(fault_address, error_code);
44874f84
JR		 1175 /*
1176 * FIXME: Tis shouldn't be necessary here, but there is a flush
1177 * missing in the MMU code. Until we find this bug, flush the
1178 * complete TLB here on an NPF
1179 */
1180 if (npt_enabled)
1181 svm_flush_tlb(&svm->vcpu);
9222be18 1182 else {
3298b75c 1183 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1184 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1185 }
3067714c 1186 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1187}
1188
d0bfb940
JK		 1189static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1190{
1191 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1192 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1193 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1194 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1195 return 1;
1196 }
44c11430
GN		 1197
1198 if (svm->vcpu.arch.singlestep) {
1199 svm->vcpu.arch.singlestep = false;
1200 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1201 svm->vmcb->save.rflags &=
1202 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1203 update_db_intercept(&svm->vcpu);
1204 }
1205
1206 if (svm->vcpu.guest_debug &
1207 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1208 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1209 kvm_run->debug.arch.pc =
1210 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1211 kvm_run->debug.arch.exception = DB_VECTOR;
1212 return 0;
1213 }
1214
1215 return 1;
d0bfb940
JK		 1216}
1217
1218static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1219{
1220 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1221 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1222 kvm_run->debug.arch.exception = BP_VECTOR;
1223 return 0;
1224}
1225
7aa81cc0
AL		 1226static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1227{
1228 int er;
1229
571008da 1230 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1231 if (er != EMULATE_DONE)
7ee5d940 1232 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1233 return 1;
1234}
1235
e756fc62 1236static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1237{
a2fa3e9f 1238 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1239 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1240 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1241 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1242
1243 return 1;
7807fa6c
AL		 1244}
1245
53371b50
JR		 1246static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1247{
1248 /*
1249 * On an #MC intercept the MCE handler is not called automatically in
1250 * the host. So do it by hand here.
1251 */
1252 asm volatile (
1253 "int $0x12\n");
1254 /* not sure if we ever come back to this point */
1255
1256 return 1;
1257}
1258
e756fc62 1259static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1260{
1261 /*
1262 * VMCB is undefined after a SHUTDOWN intercept
1263 * so reinitialize it.
1264 */
a2fa3e9f 1265 clear_page(svm->vmcb);
e6101a96 1266 init_vmcb(svm);
46fe4ddd
JR		 1267
1268 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1269 return 0;
1270}
1271
e756fc62 1272static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1273{
d77c26fc 1274 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1275 int size, in, string;
039576c0 1276 unsigned port;
6aa8b732 1277
e756fc62 1278 ++svm->vcpu.stat.io_exits;
6aa8b732 1279
a2fa3e9f 1280 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1281
e70669ab
LV		 1282 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1283
1284 if (string) {
3427318f
LV		 1285 if (emulate_instruction(&svm->vcpu,
1286 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1287 return 0;
1288 return 1;
1289 }
1290
039576c0
AK		 1291 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1292 port = io_info >> 16;
1293 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1294
e93f36bc 1295 skip_emulated_instruction(&svm->vcpu);
3090dd73 1296 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1297}
1298
c47f098d
JR		 1299static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1300{
1301 return 1;
1302}
1303
a0698055
JR		 1304static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1305{
1306 ++svm->vcpu.stat.irq_exits;
1307 return 1;
1308}
1309
e756fc62 1310static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1311{
1312 return 1;
1313}
1314
e756fc62 1315static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1316{
5fdbf976 1317 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1318 skip_emulated_instruction(&svm->vcpu);
1319 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1320}
1321
e756fc62 1322static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1323{
5fdbf976 1324 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1325 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1326 kvm_emulate_hypercall(&svm->vcpu);
1327 return 1;
02e235bc
AK		 1328}
1329
c0725420
AG		 1330static int nested_svm_check_permissions(struct vcpu_svm *svm)
1331{
1332 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1333 || !is_paging(&svm->vcpu)) {
1334 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1335 return 1;
1336 }
1337
1338 if (svm->vmcb->save.cpl) {
1339 kvm_inject_gp(&svm->vcpu, 0);
1340 return 1;
1341 }
1342
1343 return 0;
1344}
1345
cf74a78b
AG		 1346static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1347 bool has_error_code, u32 error_code)
1348{
1349 if (is_nested(svm)) {
1350 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1351 svm->vmcb->control.exit_code_hi = 0;
1352 svm->vmcb->control.exit_info_1 = error_code;
1353 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1354 if (nested_svm_exit_handled(svm, false)) {
1355 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1356
1357 nested_svm_vmexit(svm);
1358 return 1;
1359 }
1360 }
1361
1362 return 0;
1363}
1364
1365static inline int nested_svm_intr(struct vcpu_svm *svm)
1366{
1367 if (is_nested(svm)) {
1368 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1369 return 0;
1370
1371 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1372 return 0;
1373
1374 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1375
1376 if (nested_svm_exit_handled(svm, false)) {
1377 nsvm_printk("VMexit -> INTR\n");
1378 nested_svm_vmexit(svm);
1379 return 1;
1380 }
1381 }
1382
1383 return 0;
1384}
1385
c0725420
AG		 1386static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1387{
1388 struct page *page;
1389
1390 down_read(&current->mm->mmap_sem);
1391 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1392 up_read(&current->mm->mmap_sem);
1393
1394 if (is_error_page(page)) {
1395 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1396 __func__, gpa);
1397 kvm_release_page_clean(page);
1398 kvm_inject_gp(&svm->vcpu, 0);
1399 return NULL;
1400 }
1401 return page;
1402}
1403
1404static int nested_svm_do(struct vcpu_svm *svm,
1405 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1406 int (*handler)(struct vcpu_svm *svm,
1407 void *arg1,
1408 void *arg2,
1409 void *opaque))
1410{
1411 struct page *arg1_page;
1412 struct page *arg2_page = NULL;
1413 void *arg1;
1414 void *arg2 = NULL;
1415 int retval;
1416
1417 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1418 if(arg1_page == NULL)
1419 return 1;
1420
1421 if (arg2_gpa) {
1422 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1423 if(arg2_page == NULL) {
1424 kvm_release_page_clean(arg1_page);
1425 return 1;
1426 }
1427 }
1428
1429 arg1 = kmap_atomic(arg1_page, KM_USER0);
1430 if (arg2_gpa)
1431 arg2 = kmap_atomic(arg2_page, KM_USER1);
1432
1433 retval = handler(svm, arg1, arg2, opaque);
1434
1435 kunmap_atomic(arg1, KM_USER0);
1436 if (arg2_gpa)
1437 kunmap_atomic(arg2, KM_USER1);
1438
1439 kvm_release_page_dirty(arg1_page);
1440 if (arg2_gpa)
1441 kvm_release_page_dirty(arg2_page);
1442
1443 return retval;
1444}
1445
cf74a78b
AG		 1446static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1447 void *arg1,
1448 void *arg2,
1449 void *opaque)
1450{
1451 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1452 bool kvm_overrides = *(bool *)opaque;
1453 u32 exit_code = svm->vmcb->control.exit_code;
1454
1455 if (kvm_overrides) {
1456 switch (exit_code) {
1457 case SVM_EXIT_INTR:
1458 case SVM_EXIT_NMI:
1459 return 0;
1460 /* For now we are always handling NPFs when using them */
1461 case SVM_EXIT_NPF:
1462 if (npt_enabled)
1463 return 0;
1464 break;
1465 /* When we're shadowing, trap PFs */
1466 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1467 if (!npt_enabled)
1468 return 0;
1469 break;
1470 default:
1471 break;
1472 }
1473 }
1474
1475 switch (exit_code) {
1476 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1477 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1478 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1479 return 1;
1480 break;
1481 }
1482 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1483 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1484 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1485 return 1;
1486 break;
1487 }
1488 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1489 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1490 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1491 return 1;
1492 break;
1493 }
1494 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1495 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1496 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1497 return 1;
1498 break;
1499 }
1500 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1501 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1502 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1503 return 1;
1504 break;
1505 }
1506 default: {
1507 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1508 nsvm_printk("exit code: 0x%x\n", exit_code);
1509 if (nested_vmcb->control.intercept & exit_bits)
1510 return 1;
1511 }
1512 }
1513
1514 return 0;
1515}
1516
1517static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1518 void *arg1, void *arg2,
1519 void *opaque)
1520{
1521 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1522 u8 *msrpm = (u8 *)arg2;
1523 u32 t0, t1;
1524 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1525 u32 param = svm->vmcb->control.exit_info_1 & 1;
1526
1527 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1528 return 0;
1529
1530 switch(msr) {
1531 case 0 ... 0x1fff:
1532 t0 = (msr * 2) % 8;
1533 t1 = msr / 8;
1534 break;
1535 case 0xc0000000 ... 0xc0001fff:
1536 t0 = (8192 + msr - 0xc0000000) * 2;
1537 t1 = (t0 / 8);
1538 t0 %= 8;
1539 break;
1540 case 0xc0010000 ... 0xc0011fff:
1541 t0 = (16384 + msr - 0xc0010000) * 2;
1542 t1 = (t0 / 8);
1543 t0 %= 8;
1544 break;
1545 default:
1546 return 1;
1547 break;
1548 }
1549 if (msrpm[t1] & ((1 << param) << t0))
1550 return 1;
1551
1552 return 0;
1553}
1554
1555static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1556{
1557 bool k = kvm_override;
1558
1559 switch (svm->vmcb->control.exit_code) {
1560 case SVM_EXIT_MSR:
1561 return nested_svm_do(svm, svm->nested_vmcb,
1562 svm->nested_vmcb_msrpm, NULL,
1563 nested_svm_exit_handled_msr);
1564 default: break;
1565 }
1566
1567 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1568 nested_svm_exit_handled_real);
1569}
1570
0460a979
JR		 1571static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1572{
1573 struct vmcb_control_area *dst = &dst_vmcb->control;
1574 struct vmcb_control_area *from = &from_vmcb->control;
1575
1576 dst->intercept_cr_read = from->intercept_cr_read;
1577 dst->intercept_cr_write = from->intercept_cr_write;
1578 dst->intercept_dr_read = from->intercept_dr_read;
1579 dst->intercept_dr_write = from->intercept_dr_write;
1580 dst->intercept_exceptions = from->intercept_exceptions;
1581 dst->intercept = from->intercept;
1582 dst->iopm_base_pa = from->iopm_base_pa;
1583 dst->msrpm_base_pa = from->msrpm_base_pa;
1584 dst->tsc_offset = from->tsc_offset;
1585 dst->asid = from->asid;
1586 dst->tlb_ctl = from->tlb_ctl;
1587 dst->int_ctl = from->int_ctl;
1588 dst->int_vector = from->int_vector;
1589 dst->int_state = from->int_state;
1590 dst->exit_code = from->exit_code;
1591 dst->exit_code_hi = from->exit_code_hi;
1592 dst->exit_info_1 = from->exit_info_1;
1593 dst->exit_info_2 = from->exit_info_2;
1594 dst->exit_int_info = from->exit_int_info;
1595 dst->exit_int_info_err = from->exit_int_info_err;
1596 dst->nested_ctl = from->nested_ctl;
1597 dst->event_inj = from->event_inj;
1598 dst->event_inj_err = from->event_inj_err;
1599 dst->nested_cr3 = from->nested_cr3;
1600 dst->lbr_ctl = from->lbr_ctl;
1601}
1602
cf74a78b
AG		 1603static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1604 void *arg2, void *opaque)
1605{
1606 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1607 struct vmcb *hsave = svm->hsave;
33740e40 1608 struct vmcb *vmcb = svm->vmcb;
cf74a78b
AG		 1609
1610 /* Give the current vmcb to the guest */
33740e40
JR		 1611 disable_gif(svm);
1612
1613 nested_vmcb->save.es = vmcb->save.es;
1614 nested_vmcb->save.cs = vmcb->save.cs;
1615 nested_vmcb->save.ss = vmcb->save.ss;
1616 nested_vmcb->save.ds = vmcb->save.ds;
1617 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1618 nested_vmcb->save.idtr = vmcb->save.idtr;
1619 if (npt_enabled)
1620 nested_vmcb->save.cr3 = vmcb->save.cr3;
1621 nested_vmcb->save.cr2 = vmcb->save.cr2;
1622 nested_vmcb->save.rflags = vmcb->save.rflags;
1623 nested_vmcb->save.rip = vmcb->save.rip;
1624 nested_vmcb->save.rsp = vmcb->save.rsp;
1625 nested_vmcb->save.rax = vmcb->save.rax;
1626 nested_vmcb->save.dr7 = vmcb->save.dr7;
1627 nested_vmcb->save.dr6 = vmcb->save.dr6;
1628 nested_vmcb->save.cpl = vmcb->save.cpl;
1629
1630 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1631 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1632 nested_vmcb->control.int_state = vmcb->control.int_state;
1633 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1634 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1635 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1636 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1637 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1638 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1639 nested_vmcb->control.tlb_ctl = 0;
1640 nested_vmcb->control.event_inj = 0;
1641 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1642
1643 /* We always set V_INTR_MASKING and remember the old value in hflags */
1644 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1645 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1646
cf74a78b 1647 /* Restore the original control entries */
0460a979 1648 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1649
1650 /* Kill any pending exceptions */
1651 if (svm->vcpu.arch.exception.pending == true)
1652 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1653
219b65dc
AG		 1654 kvm_clear_exception_queue(&svm->vcpu);
1655 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1656
1657 /* Restore selected save entries */
1658 svm->vmcb->save.es = hsave->save.es;
1659 svm->vmcb->save.cs = hsave->save.cs;
1660 svm->vmcb->save.ss = hsave->save.ss;
1661 svm->vmcb->save.ds = hsave->save.ds;
1662 svm->vmcb->save.gdtr = hsave->save.gdtr;
1663 svm->vmcb->save.idtr = hsave->save.idtr;
1664 svm->vmcb->save.rflags = hsave->save.rflags;
1665 svm_set_efer(&svm->vcpu, hsave->save.efer);
1666 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1667 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1668 if (npt_enabled) {
1669 svm->vmcb->save.cr3 = hsave->save.cr3;
1670 svm->vcpu.arch.cr3 = hsave->save.cr3;
1671 } else {
1672 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1673 }
1674 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1675 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1676 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1677 svm->vmcb->save.dr7 = 0;
1678 svm->vmcb->save.cpl = 0;
1679 svm->vmcb->control.exit_int_info = 0;
1680
cf74a78b
AG		 1681 /* Exit nested SVM mode */
1682 svm->nested_vmcb = 0;
1683
1684 return 0;
1685}
1686
1687static int nested_svm_vmexit(struct vcpu_svm *svm)
1688{
1689 nsvm_printk("VMexit\n");
1690 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1691 NULL, nested_svm_vmexit_real))
1692 return 1;
1693
1694 kvm_mmu_reset_context(&svm->vcpu);
1695 kvm_mmu_load(&svm->vcpu);
1696
1697 return 0;
1698}
3d6368ef
AG		 1699
1700static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1701 void *arg2, void *opaque)
1702{
1703 int i;
1704 u32 *nested_msrpm = (u32*)arg1;
1705 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1706 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1707 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1708
1709 return 0;
1710}
1711
1712static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1713 void *arg2, void *opaque)
1714{
1715 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1716 struct vmcb *hsave = svm->hsave;
defbba56 1717 struct vmcb *vmcb = svm->vmcb;
3d6368ef
AG		 1718
1719 /* nested_vmcb is our indicator if nested SVM is activated */
1720 svm->nested_vmcb = svm->vmcb->save.rax;
1721
1722 /* Clear internal status */
219b65dc
AG		 1723 kvm_clear_exception_queue(&svm->vcpu);
1724 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1725
1726 /* Save the old vmcb, so we don't need to pick what we save, but
1727 can restore everything when a VMEXIT occurs */
defbba56
JR		 1728 hsave->save.es = vmcb->save.es;
1729 hsave->save.cs = vmcb->save.cs;
1730 hsave->save.ss = vmcb->save.ss;
1731 hsave->save.ds = vmcb->save.ds;
1732 hsave->save.gdtr = vmcb->save.gdtr;
1733 hsave->save.idtr = vmcb->save.idtr;
1734 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1735 hsave->save.cr0 = svm->vcpu.arch.cr0;
1736 hsave->save.cr4 = svm->vcpu.arch.cr4;
1737 hsave->save.rflags = vmcb->save.rflags;
1738 hsave->save.rip = svm->next_rip;
1739 hsave->save.rsp = vmcb->save.rsp;
1740 hsave->save.rax = vmcb->save.rax;
1741 if (npt_enabled)
1742 hsave->save.cr3 = vmcb->save.cr3;
1743 else
1744 hsave->save.cr3 = svm->vcpu.arch.cr3;
1745
0460a979 1746 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1747
1748 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1749 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1750 else
1751 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1752
1753 /* Load the nested guest state */
1754 svm->vmcb->save.es = nested_vmcb->save.es;
1755 svm->vmcb->save.cs = nested_vmcb->save.cs;
1756 svm->vmcb->save.ss = nested_vmcb->save.ss;
1757 svm->vmcb->save.ds = nested_vmcb->save.ds;
1758 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1759 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1760 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1761 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1762 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1763 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1764 if (npt_enabled) {
1765 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1766 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1767 } else {
1768 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1769 kvm_mmu_reset_context(&svm->vcpu);
1770 }
defbba56 1771 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1772 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1773 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1774 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1775 /* In case we don't even reach vcpu_run, the fields are not updated */
1776 svm->vmcb->save.rax = nested_vmcb->save.rax;
1777 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1778 svm->vmcb->save.rip = nested_vmcb->save.rip;
1779 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1780 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1781 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1782
1783 /* We don't want a nested guest to be more powerful than the guest,
1784 so all intercepts are ORed */
1785 svm->vmcb->control.intercept_cr_read |=
1786 nested_vmcb->control.intercept_cr_read;
1787 svm->vmcb->control.intercept_cr_write |=
1788 nested_vmcb->control.intercept_cr_write;
1789 svm->vmcb->control.intercept_dr_read |=
1790 nested_vmcb->control.intercept_dr_read;
1791 svm->vmcb->control.intercept_dr_write |=
1792 nested_vmcb->control.intercept_dr_write;
1793 svm->vmcb->control.intercept_exceptions |=
1794 nested_vmcb->control.intercept_exceptions;
1795
1796 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1797
1798 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1799
1800 force_new_asid(&svm->vcpu);
1801 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1802 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1803 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1804 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1805 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1806 nested_vmcb->control.int_ctl);
1807 }
1808 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1809 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1810 else
1811 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1812
1813 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1814 nested_vmcb->control.exit_int_info,
1815 nested_vmcb->control.int_state);
1816
1817 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1818 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1819 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1820 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1821 nsvm_printk("Injecting Event: 0x%x\n",
1822 nested_vmcb->control.event_inj);
1823 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1824 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1825
2af9194d 1826 enable_gif(svm);
3d6368ef
AG		 1827
1828 return 0;
1829}
1830
5542675b
AG		 1831static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1832{
1833 to_vmcb->save.fs = from_vmcb->save.fs;
1834 to_vmcb->save.gs = from_vmcb->save.gs;
1835 to_vmcb->save.tr = from_vmcb->save.tr;
1836 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1837 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1838 to_vmcb->save.star = from_vmcb->save.star;
1839 to_vmcb->save.lstar = from_vmcb->save.lstar;
1840 to_vmcb->save.cstar = from_vmcb->save.cstar;
1841 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1842 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1843 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1844 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1845
1846 return 1;
1847}
1848
1849static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1850 void *arg2, void *opaque)
1851{
1852 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1853}
1854
1855static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1856 void *arg2, void *opaque)
1857{
1858 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1859}
1860
1861static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1862{
1863 if (nested_svm_check_permissions(svm))
1864 return 1;
1865
1866 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1867 skip_emulated_instruction(&svm->vcpu);
1868
1869 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1870
1871 return 1;
1872}
1873
1874static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1875{
1876 if (nested_svm_check_permissions(svm))
1877 return 1;
1878
1879 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1880 skip_emulated_instruction(&svm->vcpu);
1881
1882 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1883
1884 return 1;
1885}
1886
3d6368ef
AG		 1887static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1888{
1889 nsvm_printk("VMrun\n");
1890 if (nested_svm_check_permissions(svm))
1891 return 1;
1892
1893 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1894 skip_emulated_instruction(&svm->vcpu);
1895
1896 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1897 NULL, nested_svm_vmrun))
1898 return 1;
1899
1900 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1901 NULL, nested_svm_vmrun_msrpm))
1902 return 1;
1903
1904 return 1;
1905}
1906
1371d904
AG		 1907static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1908{
1909 if (nested_svm_check_permissions(svm))
1910 return 1;
1911
1912 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1913 skip_emulated_instruction(&svm->vcpu);
1914
2af9194d 1915 enable_gif(svm);
1371d904
AG		 1916
1917 return 1;
1918}
1919
1920static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1921{
1922 if (nested_svm_check_permissions(svm))
1923 return 1;
1924
1925 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1926 skip_emulated_instruction(&svm->vcpu);
1927
2af9194d 1928 disable_gif(svm);
1371d904
AG		 1929
1930 /* After a CLGI no interrupts should come */
1931 svm_clear_vintr(svm);
1932 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1933
1934 return 1;
1935}
1936
ff092385
AG		 1937static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1938{
1939 struct kvm_vcpu *vcpu = &svm->vcpu;
1940 nsvm_printk("INVLPGA\n");
1941
1942 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1943 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1944
1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946 skip_emulated_instruction(&svm->vcpu);
1947 return 1;
1948}
1949
e756fc62
RR		 1950static int invalid_op_interception(struct vcpu_svm *svm,
1951 struct kvm_run *kvm_run)
6aa8b732 1952{
7ee5d940 1953 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1954 return 1;
1955}
1956
e756fc62
RR		 1957static int task_switch_interception(struct vcpu_svm *svm,
1958 struct kvm_run *kvm_run)
6aa8b732 1959{
37817f29 1960 u16 tss_selector;
64a7ec06
GN		 1961 int reason;
1962 int int_type = svm->vmcb->control.exit_int_info &
1963 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1964 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1965 uint32_t type =
1966 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1967 uint32_t idt_v =
1968 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1969
1970 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1971
37817f29
IE		 1972 if (svm->vmcb->control.exit_info_2 &
1973 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1974 reason = TASK_SWITCH_IRET;
1975 else if (svm->vmcb->control.exit_info_2 &
1976 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1977 reason = TASK_SWITCH_JMP;
fe8e7f83 1978 else if (idt_v)
64a7ec06
GN		 1979 reason = TASK_SWITCH_GATE;
1980 else
1981 reason = TASK_SWITCH_CALL;
1982
fe8e7f83
GN		 1983 if (reason == TASK_SWITCH_GATE) {
1984 switch (type) {
1985 case SVM_EXITINTINFO_TYPE_NMI:
1986 svm->vcpu.arch.nmi_injected = false;
1987 break;
1988 case SVM_EXITINTINFO_TYPE_EXEPT:
1989 kvm_clear_exception_queue(&svm->vcpu);
1990 break;
1991 case SVM_EXITINTINFO_TYPE_INTR:
1992 kvm_clear_interrupt_queue(&svm->vcpu);
1993 break;
1994 default:
1995 break;
1996 }
1997 }
64a7ec06 1998
8317c298
GN		 1999 if (reason != TASK_SWITCH_GATE ||
2000 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2001 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2002 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2003 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2004
2005 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2006}
2007
e756fc62 2008static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2009{
5fdbf976 2010 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2011 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2012 return 1;
6aa8b732
AK		 2013}
2014
95ba8273
GN		 2015static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2016{
2017 ++svm->vcpu.stat.nmi_window_exits;
2018 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2019 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2020 return 1;
2021}
2022
a7052897
MT		 2023static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2024{
2025 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2026 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2027 return 1;
2028}
2029
e756fc62
RR		 2030static int emulate_on_interception(struct vcpu_svm *svm,
2031 struct kvm_run *kvm_run)
6aa8b732 2032{
3427318f 2033 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 2034 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2035 return 1;
2036}
2037
1d075434
JR		 2038static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2039{
0a5fff19
GN		 2040 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2041 /* instruction emulation calls kvm_set_cr8() */
1d075434 2042 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 2043 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2044 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2045 return 1;
95ba8273 2046 }
0a5fff19
GN		 2047 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2048 return 1;
1d075434
JR		 2049 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2050 return 0;
2051}
2052
6aa8b732
AK		 2053static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2054{
a2fa3e9f
GH		 2055 struct vcpu_svm *svm = to_svm(vcpu);
2056
6aa8b732 2057 switch (ecx) {
af24a4e4 2058 case MSR_IA32_TSC: {
6aa8b732
AK		 2059 u64 tsc;
2060
2061 rdtscll(tsc);
a2fa3e9f 2062 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2063 break;
2064 }
0e859cac 2065 case MSR_K6_STAR:
a2fa3e9f 2066 *data = svm->vmcb->save.star;
6aa8b732 2067 break;
0e859cac 2068#ifdef CONFIG_X86_64
6aa8b732 2069 case MSR_LSTAR:
a2fa3e9f 2070 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2071 break;
2072 case MSR_CSTAR:
a2fa3e9f 2073 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2074 break;
2075 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2076 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2077 break;
2078 case MSR_SYSCALL_MASK:
a2fa3e9f 2079 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2080 break;
2081#endif
2082 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2083 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2084 break;
2085 case MSR_IA32_SYSENTER_EIP:
017cb99e 2086 *data = svm->sysenter_eip;
6aa8b732
AK		 2087 break;
2088 case MSR_IA32_SYSENTER_ESP:
017cb99e 2089 *data = svm->sysenter_esp;
6aa8b732 2090 break;
a2938c80
JR		 2091 /* Nobody will change the following 5 values in the VMCB so
2092 we can safely return them on rdmsr. They will always be 0
2093 until LBRV is implemented. */
2094 case MSR_IA32_DEBUGCTLMSR:
2095 *data = svm->vmcb->save.dbgctl;
2096 break;
2097 case MSR_IA32_LASTBRANCHFROMIP:
2098 *data = svm->vmcb->save.br_from;
2099 break;
2100 case MSR_IA32_LASTBRANCHTOIP:
2101 *data = svm->vmcb->save.br_to;
2102 break;
2103 case MSR_IA32_LASTINTFROMIP:
2104 *data = svm->vmcb->save.last_excp_from;
2105 break;
2106 case MSR_IA32_LASTINTTOIP:
2107 *data = svm->vmcb->save.last_excp_to;
2108 break;
b286d5d8
AG		 2109 case MSR_VM_HSAVE_PA:
2110 *data = svm->hsave_msr;
2111 break;
eb6f302e
JR		 2112 case MSR_VM_CR:
2113 *data = 0;
2114 break;
c8a73f18
AG		 2115 case MSR_IA32_UCODE_REV:
2116 *data = 0x01000065;
2117 break;
6aa8b732 2118 default:
3bab1f5d 2119 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2120 }
2121 return 0;
2122}
2123
e756fc62 2124static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2125{
ad312c7c 2126 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2127 u64 data;
2128
e756fc62 2129 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2130 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2131 else {
229456fc 2132 trace_kvm_msr_read(ecx, data);
af9ca2d7 2133
5fdbf976 2134 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2135 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2136 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2137 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2138 }
2139 return 1;
2140}
2141
2142static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2143{
a2fa3e9f
GH		 2144 struct vcpu_svm *svm = to_svm(vcpu);
2145
6aa8b732 2146 switch (ecx) {
af24a4e4 2147 case MSR_IA32_TSC: {
6aa8b732
AK		 2148 u64 tsc;
2149
2150 rdtscll(tsc);
a2fa3e9f 2151 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2152 break;
2153 }
0e859cac 2154 case MSR_K6_STAR:
a2fa3e9f 2155 svm->vmcb->save.star = data;
6aa8b732 2156 break;
49b14f24 2157#ifdef CONFIG_X86_64
6aa8b732 2158 case MSR_LSTAR:
a2fa3e9f 2159 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2160 break;
2161 case MSR_CSTAR:
a2fa3e9f 2162 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2163 break;
2164 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2165 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2166 break;
2167 case MSR_SYSCALL_MASK:
a2fa3e9f 2168 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2169 break;
2170#endif
2171 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2172 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2173 break;
2174 case MSR_IA32_SYSENTER_EIP:
017cb99e 2175 svm->sysenter_eip = data;
a2fa3e9f 2176 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2177 break;
2178 case MSR_IA32_SYSENTER_ESP:
017cb99e 2179 svm->sysenter_esp = data;
a2fa3e9f 2180 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2181 break;
a2938c80 2182 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2183 if (!svm_has(SVM_FEATURE_LBRV)) {
2184 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2185 __func__, data);
24e09cbf
JR		 2186 break;
2187 }
2188 if (data & DEBUGCTL_RESERVED_BITS)
2189 return 1;
2190
2191 svm->vmcb->save.dbgctl = data;
2192 if (data & (1ULL<<0))
2193 svm_enable_lbrv(svm);
2194 else
2195 svm_disable_lbrv(svm);
a2938c80 2196 break;
b286d5d8
AG		 2197 case MSR_VM_HSAVE_PA:
2198 svm->hsave_msr = data;
62b9abaa 2199 break;
3c5d0a44
AG		 2200 case MSR_VM_CR:
2201 case MSR_VM_IGNNE:
3c5d0a44
AG		 2202 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2203 break;
6aa8b732 2204 default:
3bab1f5d 2205 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2206 }
2207 return 0;
2208}
2209
e756fc62 2210static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2211{
ad312c7c 2212 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2213 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2214 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2215
229456fc 2216 trace_kvm_msr_write(ecx, data);
af9ca2d7 2217
5fdbf976 2218 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2219 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2220 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2221 else
e756fc62 2222 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2223 return 1;
2224}
2225
e756fc62 2226static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2227{
e756fc62
RR		 2228 if (svm->vmcb->control.exit_info_1)
2229 return wrmsr_interception(svm, kvm_run);
6aa8b732 2230 else
e756fc62 2231 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2232}
2233
e756fc62 2234static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2235 struct kvm_run *kvm_run)
2236{
f0b85051 2237 svm_clear_vintr(svm);
85f455f7 2238 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2239 /*
2240 * If the user space waits to inject interrupts, exit as soon as
2241 * possible
2242 */
8061823a
GN		 2243 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2244 kvm_run->request_interrupt_window &&
2245 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2246 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2247 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2248 return 0;
2249 }
2250
2251 return 1;
2252}
2253
e756fc62 2254static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2255 struct kvm_run *kvm_run) = {
2256 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2257 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2258 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2259 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2260 /* for now: */
2261 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2262 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2263 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2264 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2265 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2266 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2267 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2268 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2269 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2270 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2271 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2272 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2273 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2274 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2275 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2276 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2277 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2278 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2279 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2280 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2281 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2282 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2283 [SVM_EXIT_SMI] = nop_on_interception,
2284 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2285 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2286 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2287 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2288 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2289 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2290 [SVM_EXIT_HLT] = halt_interception,
a7052897 2291 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2292 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2293 [SVM_EXIT_IOIO] = io_interception,
2294 [SVM_EXIT_MSR] = msr_interception,
2295 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2296 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2297 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2298 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2299 [SVM_EXIT_VMLOAD] = vmload_interception,
2300 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2301 [SVM_EXIT_STGI] = stgi_interception,
2302 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2303 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2304 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2305 [SVM_EXIT_MONITOR] = invalid_op_interception,
2306 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2307 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2308};
2309
04d2cc77 2310static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2311{
04d2cc77 2312 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2313 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2314
229456fc 2315 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2316
cf74a78b
AG		 2317 if (is_nested(svm)) {
2318 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2319 exit_code, svm->vmcb->control.exit_info_1,
2320 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2321 if (nested_svm_exit_handled(svm, true)) {
2322 nested_svm_vmexit(svm);
2323 nsvm_printk("-> #VMEXIT\n");
2324 return 1;
2325 }
2326 }
2327
a5c3832d
JR		 2328 svm_complete_interrupts(svm);
2329
709ddebf
JR		 2330 if (npt_enabled) {
2331 int mmu_reload = 0;
2332 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2333 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2334 mmu_reload = 1;
2335 }
2336 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2337 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2338 if (mmu_reload) {
2339 kvm_mmu_reset_context(vcpu);
2340 kvm_mmu_load(vcpu);
2341 }
2342 }
2343
04d2cc77
AK		 2344
2345 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2346 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2347 kvm_run->fail_entry.hardware_entry_failure_reason
2348 = svm->vmcb->control.exit_code;
2349 return 0;
2350 }
2351
a2fa3e9f 2352 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2353 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2354 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2355 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2356 "exit_code 0x%x\n",
b8688d51 2357 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2358 exit_code);
2359
9d8f549d 2360 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2361 || !svm_exit_handlers[exit_code]) {
6aa8b732 2362 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2363 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2364 return 0;
2365 }
2366
e756fc62 2367 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2368}
2369
2370static void reload_tss(struct kvm_vcpu *vcpu)
2371{
2372 int cpu = raw_smp_processor_id();
2373
2374 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2375 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2376 load_TR_desc();
2377}
2378
e756fc62 2379static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2380{
2381 int cpu = raw_smp_processor_id();
2382
2383 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2384
a2fa3e9f 2385 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2386 /* FIXME: handle wraparound of asid_generation */
2387 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2388 new_asid(svm, svm_data);
6aa8b732
AK		 2389}
2390
95ba8273
GN		 2391static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2392{
2393 struct vcpu_svm *svm = to_svm(vcpu);
2394
2395 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2396 vcpu->arch.hflags |= HF_NMI_MASK;
2397 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2398 ++vcpu->stat.nmi_injections;
2399}
6aa8b732 2400
85f455f7 2401static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2402{
2403 struct vmcb_control_area *control;
2404
229456fc 2405 trace_kvm_inj_virq(irq);
af9ca2d7 2406
fa89a817 2407 ++svm->vcpu.stat.irq_injections;
e756fc62 2408 control = &svm->vmcb->control;
85f455f7 2409 control->int_vector = irq;
6aa8b732
AK		 2410 control->int_ctl &= ~V_INTR_PRIO_MASK;
2411 control->int_ctl |= V_IRQ_MASK |
2412 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2413}
2414
66fd3f7f 2415static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2416{
2417 struct vcpu_svm *svm = to_svm(vcpu);
2418
2af9194d 2419 BUG_ON(!(gif_set(svm)));
cf74a78b 2420
219b65dc
AG		 2421 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2422 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2423}
2424
95ba8273 2425static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2426{
2427 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2428
95ba8273 2429 if (irr == -1)
aaacfc9a
JR		 2430 return;
2431
95ba8273
GN		 2432 if (tpr >= irr)
2433 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2434}
aaacfc9a 2435
95ba8273
GN		 2436static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2437{
2438 struct vcpu_svm *svm = to_svm(vcpu);
2439 struct vmcb *vmcb = svm->vmcb;
2440 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2441 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2442}
2443
78646121
GN		 2444static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2445{
2446 struct vcpu_svm *svm = to_svm(vcpu);
2447 struct vmcb *vmcb = svm->vmcb;
2448 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2449 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2450 gif_set(svm) &&
219b65dc 2451 !is_nested(svm);
78646121
GN		 2452}
2453
9222be18 2454static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2455{
219b65dc
AG		 2456 struct vcpu_svm *svm = to_svm(vcpu);
2457 nsvm_printk("Trying to open IRQ window\n");
2458
2459 nested_svm_intr(svm);
2460
2461 /* In case GIF=0 we can't rely on the CPU to tell us when
2462 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2463 * The next time we get that intercept, this function will be
2464 * called again though and we'll get the vintr intercept. */
2af9194d 2465 if (gif_set(svm)) {
219b65dc
AG		 2466 svm_set_vintr(svm);
2467 svm_inject_irq(svm, 0x0);
2468 }
85f455f7
ED		 2469}
2470
95ba8273 2471static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2472{
04d2cc77 2473 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2474
44c11430
GN		 2475 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2476 == HF_NMI_MASK)
2477 return; /* IRET will cause a vm exit */
2478
2479 /* Something prevents NMI from been injected. Single step over
2480 possible problem (IRET or exception injection or interrupt
2481 shadow) */
2482 vcpu->arch.singlestep = true;
2483 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2484 update_db_intercept(vcpu);
c1150d8c
DL		 2485}
2486
cbc94022
IE		 2487static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2488{
2489 return 0;
2490}
2491
d9e368d6
AK		 2492static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2493{
2494 force_new_asid(vcpu);
2495}
2496
04d2cc77
AK		 2497static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2498{
2499}
2500
d7bf8221
JR		 2501static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2502{
2503 struct vcpu_svm *svm = to_svm(vcpu);
2504
2505 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2506 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2507 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2508 }
2509}
2510
649d6864
JR		 2511static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2512{
2513 struct vcpu_svm *svm = to_svm(vcpu);
2514 u64 cr8;
2515
649d6864
JR		 2516 cr8 = kvm_get_cr8(vcpu);
2517 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2518 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2519}
2520
9222be18
GN		 2521static void svm_complete_interrupts(struct vcpu_svm *svm)
2522{
2523 u8 vector;
2524 int type;
2525 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2526
44c11430
GN		 2527 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2528 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2529
9222be18
GN		 2530 svm->vcpu.arch.nmi_injected = false;
2531 kvm_clear_exception_queue(&svm->vcpu);
2532 kvm_clear_interrupt_queue(&svm->vcpu);
2533
2534 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2535 return;
2536
2537 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2538 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2539
2540 switch (type) {
2541 case SVM_EXITINTINFO_TYPE_NMI:
2542 svm->vcpu.arch.nmi_injected = true;
2543 break;
2544 case SVM_EXITINTINFO_TYPE_EXEPT:
2545 /* In case of software exception do not reinject an exception
2546 vector, but re-execute and instruction instead */
219b65dc
AG		 2547 if (is_nested(svm))
2548 break;
66fd3f7f 2549 if (kvm_exception_is_soft(vector))
9222be18
GN		 2550 break;
2551 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2552 u32 err = svm->vmcb->control.exit_int_info_err;
2553 kvm_queue_exception_e(&svm->vcpu, vector, err);
2554
2555 } else
2556 kvm_queue_exception(&svm->vcpu, vector);
2557 break;
2558 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2559 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2560 break;
2561 default:
2562 break;
2563 }
2564}
2565
80e31d4f
AK		 2566#ifdef CONFIG_X86_64
2567#define R "r"
2568#else
2569#define R "e"
2570#endif
2571
04d2cc77 2572static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2573{
a2fa3e9f 2574 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2575 u16 fs_selector;
2576 u16 gs_selector;
2577 u16 ldt_selector;
d9e368d6 2578
5fdbf976
MT		 2579 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2580 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2581 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2582
e756fc62 2583 pre_svm_run(svm);
6aa8b732 2584
649d6864
JR		 2585 sync_lapic_to_cr8(vcpu);
2586
6aa8b732 2587 save_host_msrs(vcpu);
d6e88aec
AK		 2588 fs_selector = kvm_read_fs();
2589 gs_selector = kvm_read_gs();
2590 ldt_selector = kvm_read_ldt();
3d6368ef
AG		 2591 if (!is_nested(svm))
2592 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2593 /* required for live migration with NPT */
2594 if (npt_enabled)
2595 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2596
04d2cc77
AK		 2597 clgi();
2598
2599 local_irq_enable();
36241b8c 2600
6aa8b732 2601 asm volatile (
80e31d4f
AK		 2602 "push %%"R"bp; \n\t"
2603 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2604 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2605 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2606 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2607 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2608 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2609#ifdef CONFIG_X86_64
fb3f0f51
RR		 2610 "mov %c[r8](%[svm]), %%r8 \n\t"
2611 "mov %c[r9](%[svm]), %%r9 \n\t"
2612 "mov %c[r10](%[svm]), %%r10 \n\t"
2613 "mov %c[r11](%[svm]), %%r11 \n\t"
2614 "mov %c[r12](%[svm]), %%r12 \n\t"
2615 "mov %c[r13](%[svm]), %%r13 \n\t"
2616 "mov %c[r14](%[svm]), %%r14 \n\t"
2617 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2618#endif
2619
6aa8b732 2620 /* Enter guest mode */
80e31d4f
AK		 2621 "push %%"R"ax \n\t"
2622 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2623 __ex(SVM_VMLOAD) "\n\t"
2624 __ex(SVM_VMRUN) "\n\t"
2625 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2626 "pop %%"R"ax \n\t"
6aa8b732
AK		 2627
2628 /* Save guest registers, load host registers */
80e31d4f
AK		 2629 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2630 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2631 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2632 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2633 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2634 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2635#ifdef CONFIG_X86_64
fb3f0f51
RR		 2636 "mov %%r8, %c[r8](%[svm]) \n\t"
2637 "mov %%r9, %c[r9](%[svm]) \n\t"
2638 "mov %%r10, %c[r10](%[svm]) \n\t"
2639 "mov %%r11, %c[r11](%[svm]) \n\t"
2640 "mov %%r12, %c[r12](%[svm]) \n\t"
2641 "mov %%r13, %c[r13](%[svm]) \n\t"
2642 "mov %%r14, %c[r14](%[svm]) \n\t"
2643 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2644#endif
80e31d4f 2645 "pop %%"R"bp"
6aa8b732 2646 :
fb3f0f51 2647 : [svm]"a"(svm),
6aa8b732 2648 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2649 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2650 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2651 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2652 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2653 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2654 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2655#ifdef CONFIG_X86_64
ad312c7c
ZX		 2656 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2657 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2658 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2659 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2660 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2661 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2662 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2663 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2664#endif
54a08c04 2665 : "cc", "memory"
80e31d4f 2666 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2667#ifdef CONFIG_X86_64
54a08c04
LV		 2668 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2669#endif
2670 );
6aa8b732 2671
ad312c7c 2672 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2673 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2674 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2675 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2676
d6e88aec
AK		 2677 kvm_load_fs(fs_selector);
2678 kvm_load_gs(gs_selector);
2679 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2680 load_host_msrs(vcpu);
2681
2682 reload_tss(vcpu);
2683
56ba47dd
AK		 2684 local_irq_disable();
2685
2686 stgi();
2687
d7bf8221
JR		 2688 sync_cr8_to_lapic(vcpu);
2689
a2fa3e9f 2690 svm->next_rip = 0;
9222be18 2691
6de4f3ad
AK		 2692 if (npt_enabled) {
2693 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2694 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2695 }
6aa8b732
AK		 2696}
2697
80e31d4f
AK		 2698#undef R
2699
6aa8b732
AK		 2700static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2701{
a2fa3e9f
GH		 2702 struct vcpu_svm *svm = to_svm(vcpu);
2703
709ddebf
JR		 2704 if (npt_enabled) {
2705 svm->vmcb->control.nested_cr3 = root;
2706 force_new_asid(vcpu);
2707 return;
2708 }
2709
a2fa3e9f 2710 svm->vmcb->save.cr3 = root;
6aa8b732 2711 force_new_asid(vcpu);
7807fa6c
AL		 2712
2713 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2714 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2715 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2716 vcpu->fpu_active = 0;
2717 }
6aa8b732
AK		 2718}
2719
6aa8b732
AK		 2720static int is_disabled(void)
2721{
6031a61c
JR		 2722 u64 vm_cr;
2723
2724 rdmsrl(MSR_VM_CR, vm_cr);
2725 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2726 return 1;
2727
6aa8b732
AK		 2728 return 0;
2729}
2730
102d8325
IM		 2731static void
2732svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2733{
2734 /*
2735 * Patch in the VMMCALL instruction:
2736 */
2737 hypercall[0] = 0x0f;
2738 hypercall[1] = 0x01;
2739 hypercall[2] = 0xd9;
102d8325
IM		 2740}
2741
002c7f7c
YS		 2742static void svm_check_processor_compat(void *rtn)
2743{
2744 *(int *)rtn = 0;
2745}
2746
774ead3a
AK		 2747static bool svm_cpu_has_accelerated_tpr(void)
2748{
2749 return false;
2750}
2751
67253af5
SY		 2752static int get_npt_level(void)
2753{
2754#ifdef CONFIG_X86_64
2755 return PT64_ROOT_LEVEL;
2756#else
2757 return PT32E_ROOT_LEVEL;
2758#endif
2759}
2760
4b12f0de 2761static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2762{
2763 return 0;
2764}
2765
229456fc
MT		 2766static const struct trace_print_flags svm_exit_reasons_str[] = {
2767 { SVM_EXIT_READ_CR0, "read_cr0" },
2768 { SVM_EXIT_READ_CR3, "read_cr3" },
2769 { SVM_EXIT_READ_CR4, "read_cr4" },
2770 { SVM_EXIT_READ_CR8, "read_cr8" },
2771 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2772 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2773 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2774 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2775 { SVM_EXIT_READ_DR0, "read_dr0" },
2776 { SVM_EXIT_READ_DR1, "read_dr1" },
2777 { SVM_EXIT_READ_DR2, "read_dr2" },
2778 { SVM_EXIT_READ_DR3, "read_dr3" },
2779 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2780 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2781 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2782 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2783 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2784 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2785 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2786 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2787 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2788 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2789 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2790 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2791 { SVM_EXIT_INTR, "interrupt" },
2792 { SVM_EXIT_NMI, "nmi" },
2793 { SVM_EXIT_SMI, "smi" },
2794 { SVM_EXIT_INIT, "init" },
2795 { SVM_EXIT_VINTR, "vintr" },
2796 { SVM_EXIT_CPUID, "cpuid" },
2797 { SVM_EXIT_INVD, "invd" },
2798 { SVM_EXIT_HLT, "hlt" },
2799 { SVM_EXIT_INVLPG, "invlpg" },
2800 { SVM_EXIT_INVLPGA, "invlpga" },
2801 { SVM_EXIT_IOIO, "io" },
2802 { SVM_EXIT_MSR, "msr" },
2803 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2804 { SVM_EXIT_SHUTDOWN, "shutdown" },
2805 { SVM_EXIT_VMRUN, "vmrun" },
2806 { SVM_EXIT_VMMCALL, "hypercall" },
2807 { SVM_EXIT_VMLOAD, "vmload" },
2808 { SVM_EXIT_VMSAVE, "vmsave" },
2809 { SVM_EXIT_STGI, "stgi" },
2810 { SVM_EXIT_CLGI, "clgi" },
2811 { SVM_EXIT_SKINIT, "skinit" },
2812 { SVM_EXIT_WBINVD, "wbinvd" },
2813 { SVM_EXIT_MONITOR, "monitor" },
2814 { SVM_EXIT_MWAIT, "mwait" },
2815 { SVM_EXIT_NPF, "npf" },
2816 { -1, NULL }
2817};
2818
344f414f
JR		 2819static bool svm_gb_page_enable(void)
2820{
2821 return true;
2822}
2823
cbdd1bea 2824static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2825 .cpu_has_kvm_support = has_svm,
2826 .disabled_by_bios = is_disabled,
2827 .hardware_setup = svm_hardware_setup,
2828 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2829 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2830 .hardware_enable = svm_hardware_enable,
2831 .hardware_disable = svm_hardware_disable,
774ead3a 2832 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2833
2834 .vcpu_create = svm_create_vcpu,
2835 .vcpu_free = svm_free_vcpu,
04d2cc77 2836 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2837
04d2cc77 2838 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2839 .vcpu_load = svm_vcpu_load,
2840 .vcpu_put = svm_vcpu_put,
2841
2842 .set_guest_debug = svm_guest_debug,
2843 .get_msr = svm_get_msr,
2844 .set_msr = svm_set_msr,
2845 .get_segment_base = svm_get_segment_base,
2846 .get_segment = svm_get_segment,
2847 .set_segment = svm_set_segment,
2e4d2653 2848 .get_cpl = svm_get_cpl,
1747fb71 2849 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2850 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2851 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2852 .set_cr3 = svm_set_cr3,
2853 .set_cr4 = svm_set_cr4,
2854 .set_efer = svm_set_efer,
2855 .get_idt = svm_get_idt,
2856 .set_idt = svm_set_idt,
2857 .get_gdt = svm_get_gdt,
2858 .set_gdt = svm_set_gdt,
2859 .get_dr = svm_get_dr,
2860 .set_dr = svm_set_dr,
6de4f3ad 2861 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2862 .get_rflags = svm_get_rflags,
2863 .set_rflags = svm_set_rflags,
2864
6aa8b732 2865 .tlb_flush = svm_flush_tlb,
6aa8b732 2866
6aa8b732 2867 .run = svm_vcpu_run,
04d2cc77 2868 .handle_exit = handle_exit,
6aa8b732 2869 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2870 .set_interrupt_shadow = svm_set_interrupt_shadow,
2871 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2872 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2873 .set_irq = svm_set_irq,
95ba8273 2874 .set_nmi = svm_inject_nmi,
298101da 2875 .queue_exception = svm_queue_exception,
78646121 2876 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2877 .nmi_allowed = svm_nmi_allowed,
2878 .enable_nmi_window = enable_nmi_window,
2879 .enable_irq_window = enable_irq_window,
2880 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2881
2882 .set_tss_addr = svm_set_tss_addr,
67253af5 2883 .get_tdp_level = get_npt_level,
4b12f0de 2884 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2885
2886 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2887 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2888};
2889
2890static int __init svm_init(void)
2891{
cb498ea2 2892 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2893 THIS_MODULE);
6aa8b732
AK		 2894}
2895
2896static void __exit svm_exit(void)
2897{
cb498ea2 2898 kvm_exit();
6aa8b732
AK		 2899}
2900
2901module_init(svm_init)
2902module_exit(svm_exit)
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