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KVM: SVM: cache nested intercepts
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
24e09cbf
JR		 50#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
c0725420
AG		 52/* Turn on to get debugging output*/
53/* #define NESTED_DEBUG */
54
55#ifdef NESTED_DEBUG
56#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57#else
58#define nsvm_printk(fmt, args...) do {} while(0)
59#endif
60
6c8166a7
AK		 61static const u32 host_save_user_msrs[] = {
62#ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65#endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67};
68
69#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71struct kvm_vcpu;
72
e6aa9abd
JR		 73struct nested_state {
74 struct vmcb *hsave;
75 u64 hsave_msr;
76 u64 vmcb;
77
78 /* These are the merged vectors */
79 u32 *msrpm;
80
81 /* gpa pointers to the real vectors */
82 u64 vmcb_msrpm;
aad42c64
JR		 83
84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
90 u64 intercept;
91
e6aa9abd
JR		 92};
93
6c8166a7
AK		 94struct vcpu_svm {
95 struct kvm_vcpu vcpu;
96 struct vmcb *vmcb;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
102
103 u64 next_rip;
104
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
106 u64 host_gs_base;
6c8166a7
AK		 107
108 u32 *msrpm;
6c8166a7 109
e6aa9abd 110 struct nested_state nested;
6c8166a7
AK		 111};
112
709ddebf
JR		 113/* enable NPT for AMD64 and X86 with PAE */
114#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
115static bool npt_enabled = true;
116#else
e3da3acd 117static bool npt_enabled = false;
709ddebf 118#endif
6c7dac72
JR		 119static int npt = 1;
120
121module_param(npt, int, S_IRUGO);
e3da3acd 122
236de055
AG		 123static int nested = 0;
124module_param(nested, int, S_IRUGO);
125
44874f84 126static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 127static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 128
cf74a78b
AG		 129static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
130static int nested_svm_vmexit(struct vcpu_svm *svm);
131static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
132 void *arg2, void *opaque);
133static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
134 bool has_error_code, u32 error_code);
135
a2fa3e9f
GH		 136static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
137{
fb3f0f51 138 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 139}
140
3d6368ef
AG		 141static inline bool is_nested(struct vcpu_svm *svm)
142{
e6aa9abd 143 return svm->nested.vmcb;
3d6368ef
AG		 144}
145
2af9194d
JR		 146static inline void enable_gif(struct vcpu_svm *svm)
147{
148 svm->vcpu.arch.hflags |= HF_GIF_MASK;
149}
150
151static inline void disable_gif(struct vcpu_svm *svm)
152{
153 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
154}
155
156static inline bool gif_set(struct vcpu_svm *svm)
157{
158 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
159}
160
4866d5e3 161static unsigned long iopm_base;
6aa8b732
AK		 162
163struct kvm_ldttss_desc {
164 u16 limit0;
165 u16 base0;
166 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
167 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
168 u32 base3;
169 u32 zero1;
170} __attribute__((packed));
171
172struct svm_cpu_data {
173 int cpu;
174
5008fdf5
AK		 175 u64 asid_generation;
176 u32 max_asid;
177 u32 next_asid;
6aa8b732
AK		 178 struct kvm_ldttss_desc *tss_desc;
179
180 struct page *save_area;
181};
182
183static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 184static uint32_t svm_features;
6aa8b732
AK		 185
186struct svm_init_data {
187 int cpu;
188 int r;
189};
190
191static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
192
9d8f549d 193#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 194#define MSRS_RANGE_SIZE 2048
195#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
196
197#define MAX_INST_SIZE 15
198
80b7706e
JR		 199static inline u32 svm_has(u32 feat)
200{
201 return svm_features & feat;
202}
203
6aa8b732
AK		 204static inline void clgi(void)
205{
4ecac3fd 206 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 207}
208
209static inline void stgi(void)
210{
4ecac3fd 211 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 212}
213
214static inline void invlpga(unsigned long addr, u32 asid)
215{
4ecac3fd 216 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 217}
218
6aa8b732
AK		 219static inline void force_new_asid(struct kvm_vcpu *vcpu)
220{
a2fa3e9f 221 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 222}
223
224static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
225{
226 force_new_asid(vcpu);
227}
228
229static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
230{
709ddebf 231 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 232 efer &= ~EFER_LME;
6aa8b732 233
9962d032 234 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 235 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 236}
237
298101da
AK		 238static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
239 bool has_error_code, u32 error_code)
240{
241 struct vcpu_svm *svm = to_svm(vcpu);
242
cf74a78b
AG		 243 /* If we are within a nested VM we'd better #VMEXIT and let the
244 guest handle the exception */
245 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
246 return;
247
298101da
AK		 248 svm->vmcb->control.event_inj = nr
249 | SVM_EVTINJ_VALID
250 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
251 | SVM_EVTINJ_TYPE_EXEPT;
252 svm->vmcb->control.event_inj_err = error_code;
253}
254
6aa8b732
AK		 255static int is_external_interrupt(u32 info)
256{
257 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
258 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
259}
260
2809f5d2
GC		 261static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
262{
263 struct vcpu_svm *svm = to_svm(vcpu);
264 u32 ret = 0;
265
266 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
267 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
268 return ret & mask;
269}
270
271static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
272{
273 struct vcpu_svm *svm = to_svm(vcpu);
274
275 if (mask == 0)
276 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
277 else
278 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
279
280}
281
6aa8b732
AK		 282static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
283{
a2fa3e9f
GH		 284 struct vcpu_svm *svm = to_svm(vcpu);
285
286 if (!svm->next_rip) {
f629cf84
GN		 287 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
288 EMULATE_DONE)
289 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 290 return;
291 }
5fdbf976
MT		 292 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
293 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
294 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 295
5fdbf976 296 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 297 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 298}
299
300static int has_svm(void)
301{
63d1142f 302 const char *msg;
6aa8b732 303
63d1142f 304 if (!cpu_has_svm(&msg)) {
ff81ff10 305 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 306 return 0;
307 }
308
6aa8b732
AK		 309 return 1;
310}
311
312static void svm_hardware_disable(void *garbage)
313{
2c8dceeb 314 cpu_svm_disable();
6aa8b732
AK		 315}
316
317static void svm_hardware_enable(void *garbage)
318{
319
320 struct svm_cpu_data *svm_data;
321 uint64_t efer;
b792c344 322 struct descriptor_table gdt_descr;
6aa8b732
AK		 323 struct desc_struct *gdt;
324 int me = raw_smp_processor_id();
325
326 if (!has_svm()) {
327 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
328 return;
329 }
330 svm_data = per_cpu(svm_data, me);
331
332 if (!svm_data) {
333 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
334 me);
335 return;
336 }
337
338 svm_data->asid_generation = 1;
339 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
340 svm_data->next_asid = svm_data->max_asid + 1;
341
b792c344
AM		 342 kvm_get_gdt(&gdt_descr);
343 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 344 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
345
346 rdmsrl(MSR_EFER, efer);
9962d032 347 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 348
349 wrmsrl(MSR_VM_HSAVE_PA,
350 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
351}
352
0da1db75
JR		 353static void svm_cpu_uninit(int cpu)
354{
355 struct svm_cpu_data *svm_data
356 = per_cpu(svm_data, raw_smp_processor_id());
357
358 if (!svm_data)
359 return;
360
361 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
362 __free_page(svm_data->save_area);
363 kfree(svm_data);
364}
365
6aa8b732
AK		 366static int svm_cpu_init(int cpu)
367{
368 struct svm_cpu_data *svm_data;
369 int r;
370
371 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
372 if (!svm_data)
373 return -ENOMEM;
374 svm_data->cpu = cpu;
375 svm_data->save_area = alloc_page(GFP_KERNEL);
376 r = -ENOMEM;
377 if (!svm_data->save_area)
378 goto err_1;
379
380 per_cpu(svm_data, cpu) = svm_data;
381
382 return 0;
383
384err_1:
385 kfree(svm_data);
386 return r;
387
388}
389
bfc733a7
RR		 390static void set_msr_interception(u32 *msrpm, unsigned msr,
391 int read, int write)
6aa8b732
AK		 392{
393 int i;
394
395 for (i = 0; i < NUM_MSR_MAPS; i++) {
396 if (msr >= msrpm_ranges[i] &&
397 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
398 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
399 msrpm_ranges[i]) * 2;
400
401 u32 *base = msrpm + (msr_offset / 32);
402 u32 msr_shift = msr_offset % 32;
403 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
404 *base = (*base & ~(0x3 << msr_shift)) |
405 (mask << msr_shift);
bfc733a7 406 return;
6aa8b732
AK		 407 }
408 }
bfc733a7 409 BUG();
6aa8b732
AK		 410}
411
f65c229c
JR		 412static void svm_vcpu_init_msrpm(u32 *msrpm)
413{
414 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
415
416#ifdef CONFIG_X86_64
417 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
418 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
419 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
420 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
421 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
422 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
423#endif
424 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
425 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 426}
427
24e09cbf
JR		 428static void svm_enable_lbrv(struct vcpu_svm *svm)
429{
430 u32 *msrpm = svm->msrpm;
431
432 svm->vmcb->control.lbr_ctl = 1;
433 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
434 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
435 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
437}
438
439static void svm_disable_lbrv(struct vcpu_svm *svm)
440{
441 u32 *msrpm = svm->msrpm;
442
443 svm->vmcb->control.lbr_ctl = 0;
444 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
445 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
446 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
447 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
448}
449
6aa8b732
AK		 450static __init int svm_hardware_setup(void)
451{
452 int cpu;
453 struct page *iopm_pages;
f65c229c 454 void *iopm_va;
6aa8b732
AK		 455 int r;
456
6aa8b732
AK		 457 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
458
459 if (!iopm_pages)
460 return -ENOMEM;
c8681339
AL		 461
462 iopm_va = page_address(iopm_pages);
463 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 464 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
465
50a37eb4
JR		 466 if (boot_cpu_has(X86_FEATURE_NX))
467 kvm_enable_efer_bits(EFER_NX);
468
1b2fd70c
AG		 469 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
470 kvm_enable_efer_bits(EFER_FFXSR);
471
236de055
AG		 472 if (nested) {
473 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
474 kvm_enable_efer_bits(EFER_SVME);
475 }
476
6aa8b732
AK		 477 for_each_online_cpu(cpu) {
478 r = svm_cpu_init(cpu);
479 if (r)
f65c229c 480 goto err;
6aa8b732 481 }
33bd6a0b
JR		 482
483 svm_features = cpuid_edx(SVM_CPUID_FUNC);
484
e3da3acd
JR		 485 if (!svm_has(SVM_FEATURE_NPT))
486 npt_enabled = false;
487
6c7dac72
JR		 488 if (npt_enabled && !npt) {
489 printk(KERN_INFO "kvm: Nested Paging disabled\n");
490 npt_enabled = false;
491 }
492
18552672 493 if (npt_enabled) {
e3da3acd 494 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 495 kvm_enable_tdp();
5f4cb662
JR		 496 } else
497 kvm_disable_tdp();
e3da3acd 498
6aa8b732
AK		 499 return 0;
500
f65c229c 501err:
6aa8b732
AK		 502 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
503 iopm_base = 0;
504 return r;
505}
506
507static __exit void svm_hardware_unsetup(void)
508{
0da1db75
JR		 509 int cpu;
510
511 for_each_online_cpu(cpu)
512 svm_cpu_uninit(cpu);
513
6aa8b732 514 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 515 iopm_base = 0;
6aa8b732
AK		 516}
517
518static void init_seg(struct vmcb_seg *seg)
519{
520 seg->selector = 0;
521 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
522 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
523 seg->limit = 0xffff;
524 seg->base = 0;
525}
526
527static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
528{
529 seg->selector = 0;
530 seg->attrib = SVM_SELECTOR_P_MASK | type;
531 seg->limit = 0xffff;
532 seg->base = 0;
533}
534
e6101a96 535static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 536{
e6101a96
JR		 537 struct vmcb_control_area *control = &svm->vmcb->control;
538 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 539
540 control->intercept_cr_read = INTERCEPT_CR0_MASK |
541 INTERCEPT_CR3_MASK |
649d6864 542 INTERCEPT_CR4_MASK;
6aa8b732
AK		 543
544 control->intercept_cr_write = INTERCEPT_CR0_MASK |
545 INTERCEPT_CR3_MASK |
80a8119c
AK		 546 INTERCEPT_CR4_MASK |
547 INTERCEPT_CR8_MASK;
6aa8b732
AK		 548
549 control->intercept_dr_read = INTERCEPT_DR0_MASK |
550 INTERCEPT_DR1_MASK |
551 INTERCEPT_DR2_MASK |
552 INTERCEPT_DR3_MASK;
553
554 control->intercept_dr_write = INTERCEPT_DR0_MASK |
555 INTERCEPT_DR1_MASK |
556 INTERCEPT_DR2_MASK |
557 INTERCEPT_DR3_MASK |
558 INTERCEPT_DR5_MASK |
559 INTERCEPT_DR7_MASK;
560
7aa81cc0 561 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 562 (1 << UD_VECTOR) |
563 (1 << MC_VECTOR);
6aa8b732
AK		 564
565
566 control->intercept = (1ULL << INTERCEPT_INTR) |
567 (1ULL << INTERCEPT_NMI) |
0152527b 568 (1ULL << INTERCEPT_SMI) |
6aa8b732 569 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 570 (1ULL << INTERCEPT_INVD) |
6aa8b732 571 (1ULL << INTERCEPT_HLT) |
a7052897 572 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 573 (1ULL << INTERCEPT_INVLPGA) |
574 (1ULL << INTERCEPT_IOIO_PROT) |
575 (1ULL << INTERCEPT_MSR_PROT) |
576 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 577 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 578 (1ULL << INTERCEPT_VMRUN) |
579 (1ULL << INTERCEPT_VMMCALL) |
580 (1ULL << INTERCEPT_VMLOAD) |
581 (1ULL << INTERCEPT_VMSAVE) |
582 (1ULL << INTERCEPT_STGI) |
583 (1ULL << INTERCEPT_CLGI) |
916ce236 584 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 585 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 586 (1ULL << INTERCEPT_MONITOR) |
587 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 588
589 control->iopm_base_pa = iopm_base;
f65c229c 590 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 591 control->tsc_offset = 0;
6aa8b732
AK		 592 control->int_ctl = V_INTR_MASKING_MASK;
593
594 init_seg(&save->es);
595 init_seg(&save->ss);
596 init_seg(&save->ds);
597 init_seg(&save->fs);
598 init_seg(&save->gs);
599
600 save->cs.selector = 0xf000;
601 /* Executable/Readable Code Segment */
602 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
603 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
604 save->cs.limit = 0xffff;
d92899a0
AK		 605 /*
606 * cs.base should really be 0xffff0000, but vmx can't handle that, so
607 * be consistent with it.
608 *
609 * Replace when we have real mode working for vmx.
610 */
611 save->cs.base = 0xf0000;
6aa8b732
AK		 612
613 save->gdtr.limit = 0xffff;
614 save->idtr.limit = 0xffff;
615
616 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
617 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
618
9962d032 619 save->efer = EFER_SVME;
d77c26fc 620 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 621 save->dr7 = 0x400;
622 save->rflags = 2;
623 save->rip = 0x0000fff0;
5fdbf976 624 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 625
626 /*
627 * cr0 val on cpu init should be 0x60000010, we enable cpu
628 * cache by default. the orderly way is to enable cache in bios.
629 */
707d92fa 630 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 631 save->cr4 = X86_CR4_PAE;
6aa8b732 632 /* rdx = ?? */
709ddebf
JR		 633
634 if (npt_enabled) {
635 /* Setup VMCB for Nested Paging */
636 control->nested_ctl = 1;
a7052897
MT		 637 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
638 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 639 control->intercept_exceptions &= ~(1 << PF_VECTOR);
640 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
641 INTERCEPT_CR3_MASK);
642 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
643 INTERCEPT_CR3_MASK);
644 save->g_pat = 0x0007040600070406ULL;
645 /* enable caching because the QEMU Bios doesn't enable it */
646 save->cr0 = X86_CR0_ET;
647 save->cr3 = 0;
648 save->cr4 = 0;
649 }
a79d2f18 650 force_new_asid(&svm->vcpu);
1371d904 651
e6aa9abd 652 svm->nested.vmcb = 0;
2af9194d
JR		 653 svm->vcpu.arch.hflags = 0;
654
655 enable_gif(svm);
6aa8b732
AK		 656}
657
e00c8cf2 658static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 659{
660 struct vcpu_svm *svm = to_svm(vcpu);
661
e6101a96 662 init_vmcb(svm);
70433389 663
c5af89b6 664 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 665 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 666 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
667 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 668 }
5fdbf976
MT		 669 vcpu->arch.regs_avail = ~0;
670 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 671
672 return 0;
04d2cc77
AK		 673}
674
fb3f0f51 675static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 676{
a2fa3e9f 677 struct vcpu_svm *svm;
6aa8b732 678 struct page *page;
f65c229c 679 struct page *msrpm_pages;
b286d5d8 680 struct page *hsave_page;
3d6368ef 681 struct page *nested_msrpm_pages;
fb3f0f51 682 int err;
6aa8b732 683
c16f862d 684 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 685 if (!svm) {
686 err = -ENOMEM;
687 goto out;
688 }
689
690 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
691 if (err)
692 goto free_svm;
693
6aa8b732 694 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 695 if (!page) {
696 err = -ENOMEM;
697 goto uninit;
698 }
6aa8b732 699
f65c229c
JR		 700 err = -ENOMEM;
701 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
702 if (!msrpm_pages)
703 goto uninit;
3d6368ef
AG		 704
705 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
706 if (!nested_msrpm_pages)
707 goto uninit;
708
f65c229c
JR		 709 svm->msrpm = page_address(msrpm_pages);
710 svm_vcpu_init_msrpm(svm->msrpm);
711
b286d5d8
AG		 712 hsave_page = alloc_page(GFP_KERNEL);
713 if (!hsave_page)
714 goto uninit;
e6aa9abd 715 svm->nested.hsave = page_address(hsave_page);
b286d5d8 716
e6aa9abd 717 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 718
a2fa3e9f
GH		 719 svm->vmcb = page_address(page);
720 clear_page(svm->vmcb);
721 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
722 svm->asid_generation = 0;
e6101a96 723 init_vmcb(svm);
a2fa3e9f 724
fb3f0f51
RR		 725 fx_init(&svm->vcpu);
726 svm->vcpu.fpu_active = 1;
ad312c7c 727 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 728 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 729 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 730
fb3f0f51 731 return &svm->vcpu;
36241b8c 732
fb3f0f51
RR		 733uninit:
734 kvm_vcpu_uninit(&svm->vcpu);
735free_svm:
a4770347 736 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 737out:
738 return ERR_PTR(err);
6aa8b732
AK		 739}
740
741static void svm_free_vcpu(struct kvm_vcpu *vcpu)
742{
a2fa3e9f
GH		 743 struct vcpu_svm *svm = to_svm(vcpu);
744
fb3f0f51 745 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 746 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 747 __free_page(virt_to_page(svm->nested.hsave));
748 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 749 kvm_vcpu_uninit(vcpu);
a4770347 750 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 751}
752
15ad7146 753static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 754{
a2fa3e9f 755 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 756 int i;
0cc5064d 757
0cc5064d
AK		 758 if (unlikely(cpu != vcpu->cpu)) {
759 u64 tsc_this, delta;
760
761 /*
762 * Make sure that the guest sees a monotonically
763 * increasing TSC.
764 */
765 rdtscll(tsc_this);
ad312c7c 766 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 767 svm->vmcb->control.tsc_offset += delta;
0cc5064d 768 vcpu->cpu = cpu;
2f599714 769 kvm_migrate_timers(vcpu);
4b656b12 770 svm->asid_generation = 0;
0cc5064d 771 }
94dfbdb3
AL		 772
773 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 774 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 775}
776
777static void svm_vcpu_put(struct kvm_vcpu *vcpu)
778{
a2fa3e9f 779 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 780 int i;
781
e1beb1d3 782 ++vcpu->stat.host_state_reload;
94dfbdb3 783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 784 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 785
ad312c7c 786 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 787}
788
6aa8b732
AK		 789static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
790{
a2fa3e9f 791 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 792}
793
794static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
795{
a2fa3e9f 796 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 797}
798
6de4f3ad
AK		 799static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
800{
801 switch (reg) {
802 case VCPU_EXREG_PDPTR:
803 BUG_ON(!npt_enabled);
804 load_pdptrs(vcpu, vcpu->arch.cr3);
805 break;
806 default:
807 BUG();
808 }
809}
810
f0b85051
AG		 811static void svm_set_vintr(struct vcpu_svm *svm)
812{
813 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
814}
815
816static void svm_clear_vintr(struct vcpu_svm *svm)
817{
818 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
819}
820
6aa8b732
AK		 821static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
822{
a2fa3e9f 823 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 824
825 switch (seg) {
826 case VCPU_SREG_CS: return &save->cs;
827 case VCPU_SREG_DS: return &save->ds;
828 case VCPU_SREG_ES: return &save->es;
829 case VCPU_SREG_FS: return &save->fs;
830 case VCPU_SREG_GS: return &save->gs;
831 case VCPU_SREG_SS: return &save->ss;
832 case VCPU_SREG_TR: return &save->tr;
833 case VCPU_SREG_LDTR: return &save->ldtr;
834 }
835 BUG();
8b6d44c7 836 return NULL;
6aa8b732
AK		 837}
838
839static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
840{
841 struct vmcb_seg *s = svm_seg(vcpu, seg);
842
843 return s->base;
844}
845
846static void svm_get_segment(struct kvm_vcpu *vcpu,
847 struct kvm_segment *var, int seg)
848{
849 struct vmcb_seg *s = svm_seg(vcpu, seg);
850
851 var->base = s->base;
852 var->limit = s->limit;
853 var->selector = s->selector;
854 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
855 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
856 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
857 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
858 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
859 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
860 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
861 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 862
19bca6ab
AP		 863 /* AMD's VMCB does not have an explicit unusable field, so emulate it
864 * for cross vendor migration purposes by "not present"
865 */
866 var->unusable = !var->present || (var->type == 0);
867
1fbdc7a5
AP		 868 switch (seg) {
869 case VCPU_SREG_CS:
870 /*
871 * SVM always stores 0 for the 'G' bit in the CS selector in
872 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
873 * Intel's VMENTRY has a check on the 'G' bit.
874 */
25022acc 875 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 876 break;
877 case VCPU_SREG_TR:
878 /*
879 * Work around a bug where the busy flag in the tr selector
880 * isn't exposed
881 */
c0d09828 882 var->type |= 0x2;
1fbdc7a5
AP		 883 break;
884 case VCPU_SREG_DS:
885 case VCPU_SREG_ES:
886 case VCPU_SREG_FS:
887 case VCPU_SREG_GS:
888 /*
889 * The accessed bit must always be set in the segment
890 * descriptor cache, although it can be cleared in the
891 * descriptor, the cached bit always remains at 1. Since
892 * Intel has a check on this, set it here to support
893 * cross-vendor migration.
894 */
895 if (!var->unusable)
896 var->type |= 0x1;
897 break;
b586eb02
AP		 898 case VCPU_SREG_SS:
899 /* On AMD CPUs sometimes the DB bit in the segment
900 * descriptor is left as 1, although the whole segment has
901 * been made unusable. Clear it here to pass an Intel VMX
902 * entry check when cross vendor migrating.
903 */
904 if (var->unusable)
905 var->db = 0;
906 break;
1fbdc7a5 907 }
6aa8b732
AK		 908}
909
2e4d2653
IE		 910static int svm_get_cpl(struct kvm_vcpu *vcpu)
911{
912 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
913
914 return save->cpl;
915}
916
6aa8b732
AK		 917static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
918{
a2fa3e9f
GH		 919 struct vcpu_svm *svm = to_svm(vcpu);
920
921 dt->limit = svm->vmcb->save.idtr.limit;
922 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 923}
924
925static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
926{
a2fa3e9f
GH		 927 struct vcpu_svm *svm = to_svm(vcpu);
928
929 svm->vmcb->save.idtr.limit = dt->limit;
930 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 931}
932
933static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
934{
a2fa3e9f
GH		 935 struct vcpu_svm *svm = to_svm(vcpu);
936
937 dt->limit = svm->vmcb->save.gdtr.limit;
938 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 939}
940
941static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
942{
a2fa3e9f
GH		 943 struct vcpu_svm *svm = to_svm(vcpu);
944
945 svm->vmcb->save.gdtr.limit = dt->limit;
946 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 947}
948
25c4c276 949static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 950{
951}
952
6aa8b732
AK		 953static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
954{
a2fa3e9f
GH		 955 struct vcpu_svm *svm = to_svm(vcpu);
956
05b3e0c2 957#ifdef CONFIG_X86_64
ad312c7c 958 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 959 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 960 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 961 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 962 }
963
d77c26fc 964 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 965 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 966 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 967 }
968 }
969#endif
709ddebf
JR		 970 if (npt_enabled)
971 goto set;
972
ad312c7c 973 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 974 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 975 vcpu->fpu_active = 1;
976 }
977
ad312c7c 978 vcpu->arch.cr0 = cr0;
707d92fa 979 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 980 if (!vcpu->fpu_active) {
981 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 982 cr0 |= X86_CR0_TS;
6b390b63 983 }
709ddebf
JR		 984set:
985 /*
986 * re-enable caching here because the QEMU bios
987 * does not do it - this results in some delay at
988 * reboot
989 */
990 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 991 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 992}
993
994static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
995{
6394b649 996 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 997 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
998
999 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1000 force_new_asid(vcpu);
6394b649 1001
ec077263
JR		 1002 vcpu->arch.cr4 = cr4;
1003 if (!npt_enabled)
1004 cr4 |= X86_CR4_PAE;
6394b649 1005 cr4 |= host_cr4_mce;
ec077263 1006 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1007}
1008
1009static void svm_set_segment(struct kvm_vcpu *vcpu,
1010 struct kvm_segment *var, int seg)
1011{
a2fa3e9f 1012 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1013 struct vmcb_seg *s = svm_seg(vcpu, seg);
1014
1015 s->base = var->base;
1016 s->limit = var->limit;
1017 s->selector = var->selector;
1018 if (var->unusable)
1019 s->attrib = 0;
1020 else {
1021 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1022 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1023 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1024 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1025 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1026 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1027 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1028 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1029 }
1030 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1031 svm->vmcb->save.cpl
1032 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1033 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1034
1035}
1036
44c11430 1037static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1038{
d0bfb940
JK		 1039 struct vcpu_svm *svm = to_svm(vcpu);
1040
d0bfb940
JK		 1041 svm->vmcb->control.intercept_exceptions &=
1042 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1043
1044 if (vcpu->arch.singlestep)
1045 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1046
d0bfb940
JK		 1047 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1048 if (vcpu->guest_debug &
1049 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1050 svm->vmcb->control.intercept_exceptions |=
1051 1 << DB_VECTOR;
1052 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1053 svm->vmcb->control.intercept_exceptions |=
1054 1 << BP_VECTOR;
1055 } else
1056 vcpu->guest_debug = 0;
44c11430
GN		 1057}
1058
1059static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1060{
1061 int old_debug = vcpu->guest_debug;
1062 struct vcpu_svm *svm = to_svm(vcpu);
1063
1064 vcpu->guest_debug = dbg->control;
1065
1066 update_db_intercept(vcpu);
d0bfb940 1067
ae675ef0
JK		 1068 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1069 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1070 else
1071 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1072
d0bfb940
JK		 1073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1074 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1075 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1076 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1077
1078 return 0;
6aa8b732
AK		 1079}
1080
1081static void load_host_msrs(struct kvm_vcpu *vcpu)
1082{
94dfbdb3 1083#ifdef CONFIG_X86_64
a2fa3e9f 1084 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1085#endif
6aa8b732
AK		 1086}
1087
1088static void save_host_msrs(struct kvm_vcpu *vcpu)
1089{
94dfbdb3 1090#ifdef CONFIG_X86_64
a2fa3e9f 1091 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1092#endif
6aa8b732
AK		 1093}
1094
e756fc62 1095static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1096{
1097 if (svm_data->next_asid > svm_data->max_asid) {
1098 ++svm_data->asid_generation;
1099 svm_data->next_asid = 1;
a2fa3e9f 1100 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1101 }
1102
a2fa3e9f
GH		 1103 svm->asid_generation = svm_data->asid_generation;
1104 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1105}
1106
6aa8b732
AK		 1107static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1108{
42dbaa5a
JK		 1109 struct vcpu_svm *svm = to_svm(vcpu);
1110 unsigned long val;
1111
1112 switch (dr) {
1113 case 0 ... 3:
1114 val = vcpu->arch.db[dr];
1115 break;
1116 case 6:
1117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1118 val = vcpu->arch.dr6;
1119 else
1120 val = svm->vmcb->save.dr6;
1121 break;
1122 case 7:
1123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1124 val = vcpu->arch.dr7;
1125 else
1126 val = svm->vmcb->save.dr7;
1127 break;
1128 default:
1129 val = 0;
1130 }
1131
af9ca2d7 1132 return val;
6aa8b732
AK		 1133}
1134
1135static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1136 int *exception)
1137{
a2fa3e9f
GH		 1138 struct vcpu_svm *svm = to_svm(vcpu);
1139
42dbaa5a 1140 *exception = 0;
6aa8b732
AK		 1141
1142 switch (dr) {
1143 case 0 ... 3:
42dbaa5a
JK		 1144 vcpu->arch.db[dr] = value;
1145 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1146 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1147 return;
1148 case 4 ... 5:
42dbaa5a 1149 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1150 *exception = UD_VECTOR;
42dbaa5a
JK		 1151 return;
1152 case 6:
1153 if (value & 0xffffffff00000000ULL) {
1154 *exception = GP_VECTOR;
6aa8b732
AK		 1155 return;
1156 }
42dbaa5a
JK		 1157 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1158 return;
1159 case 7:
1160 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1161 *exception = GP_VECTOR;
1162 return;
1163 }
42dbaa5a
JK		 1164 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1165 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1166 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1167 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1168 }
6aa8b732 1169 return;
6aa8b732 1170 default:
42dbaa5a 1171 /* FIXME: Possible case? */
6aa8b732 1172 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1173 __func__, dr);
6aa8b732
AK		 1174 *exception = UD_VECTOR;
1175 return;
1176 }
1177}
1178
e756fc62 1179static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1180{
6aa8b732
AK		 1181 u64 fault_address;
1182 u32 error_code;
6aa8b732 1183
a2fa3e9f
GH		 1184 fault_address = svm->vmcb->control.exit_info_2;
1185 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1186
229456fc 1187 trace_kvm_page_fault(fault_address, error_code);
44874f84
JR		 1188 /*
1189 * FIXME: Tis shouldn't be necessary here, but there is a flush
1190 * missing in the MMU code. Until we find this bug, flush the
1191 * complete TLB here on an NPF
1192 */
1193 if (npt_enabled)
1194 svm_flush_tlb(&svm->vcpu);
9222be18 1195 else {
3298b75c 1196 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1197 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1198 }
3067714c 1199 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1200}
1201
d0bfb940
JK		 1202static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1203{
1204 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1205 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1206 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1207 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1208 return 1;
1209 }
44c11430
GN		 1210
1211 if (svm->vcpu.arch.singlestep) {
1212 svm->vcpu.arch.singlestep = false;
1213 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1214 svm->vmcb->save.rflags &=
1215 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1216 update_db_intercept(&svm->vcpu);
1217 }
1218
1219 if (svm->vcpu.guest_debug &
1220 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1221 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1222 kvm_run->debug.arch.pc =
1223 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1224 kvm_run->debug.arch.exception = DB_VECTOR;
1225 return 0;
1226 }
1227
1228 return 1;
d0bfb940
JK		 1229}
1230
1231static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1232{
1233 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1234 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235 kvm_run->debug.arch.exception = BP_VECTOR;
1236 return 0;
1237}
1238
7aa81cc0
AL		 1239static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1240{
1241 int er;
1242
571008da 1243 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1244 if (er != EMULATE_DONE)
7ee5d940 1245 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1246 return 1;
1247}
1248
e756fc62 1249static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1250{
a2fa3e9f 1251 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1252 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1253 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1254 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1255
1256 return 1;
7807fa6c
AL		 1257}
1258
53371b50
JR		 1259static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1260{
1261 /*
1262 * On an #MC intercept the MCE handler is not called automatically in
1263 * the host. So do it by hand here.
1264 */
1265 asm volatile (
1266 "int $0x12\n");
1267 /* not sure if we ever come back to this point */
1268
1269 return 1;
1270}
1271
e756fc62 1272static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1273{
1274 /*
1275 * VMCB is undefined after a SHUTDOWN intercept
1276 * so reinitialize it.
1277 */
a2fa3e9f 1278 clear_page(svm->vmcb);
e6101a96 1279 init_vmcb(svm);
46fe4ddd
JR		 1280
1281 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1282 return 0;
1283}
1284
e756fc62 1285static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1286{
d77c26fc 1287 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1288 int size, in, string;
039576c0 1289 unsigned port;
6aa8b732 1290
e756fc62 1291 ++svm->vcpu.stat.io_exits;
6aa8b732 1292
a2fa3e9f 1293 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1294
e70669ab
LV		 1295 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1296
1297 if (string) {
3427318f
LV		 1298 if (emulate_instruction(&svm->vcpu,
1299 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1300 return 0;
1301 return 1;
1302 }
1303
039576c0
AK		 1304 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1305 port = io_info >> 16;
1306 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1307
e93f36bc 1308 skip_emulated_instruction(&svm->vcpu);
3090dd73 1309 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1310}
1311
c47f098d
JR		 1312static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1313{
1314 return 1;
1315}
1316
a0698055
JR		 1317static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1318{
1319 ++svm->vcpu.stat.irq_exits;
1320 return 1;
1321}
1322
e756fc62 1323static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1324{
1325 return 1;
1326}
1327
e756fc62 1328static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1329{
5fdbf976 1330 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1331 skip_emulated_instruction(&svm->vcpu);
1332 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1333}
1334
e756fc62 1335static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1336{
5fdbf976 1337 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1338 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1339 kvm_emulate_hypercall(&svm->vcpu);
1340 return 1;
02e235bc
AK		 1341}
1342
c0725420
AG		 1343static int nested_svm_check_permissions(struct vcpu_svm *svm)
1344{
1345 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1346 || !is_paging(&svm->vcpu)) {
1347 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1348 return 1;
1349 }
1350
1351 if (svm->vmcb->save.cpl) {
1352 kvm_inject_gp(&svm->vcpu, 0);
1353 return 1;
1354 }
1355
1356 return 0;
1357}
1358
cf74a78b
AG		 1359static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1360 bool has_error_code, u32 error_code)
1361{
1362 if (is_nested(svm)) {
1363 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1364 svm->vmcb->control.exit_code_hi = 0;
1365 svm->vmcb->control.exit_info_1 = error_code;
1366 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1367 if (nested_svm_exit_handled(svm, false)) {
1368 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1369
1370 nested_svm_vmexit(svm);
1371 return 1;
1372 }
1373 }
1374
1375 return 0;
1376}
1377
1378static inline int nested_svm_intr(struct vcpu_svm *svm)
1379{
1380 if (is_nested(svm)) {
1381 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1382 return 0;
1383
1384 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1385 return 0;
1386
1387 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1388
1389 if (nested_svm_exit_handled(svm, false)) {
1390 nsvm_printk("VMexit -> INTR\n");
1391 nested_svm_vmexit(svm);
1392 return 1;
1393 }
1394 }
1395
1396 return 0;
1397}
1398
c0725420
AG		 1399static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1400{
1401 struct page *page;
1402
1403 down_read(&current->mm->mmap_sem);
1404 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1405 up_read(&current->mm->mmap_sem);
1406
1407 if (is_error_page(page)) {
1408 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1409 __func__, gpa);
1410 kvm_release_page_clean(page);
1411 kvm_inject_gp(&svm->vcpu, 0);
1412 return NULL;
1413 }
1414 return page;
1415}
1416
1417static int nested_svm_do(struct vcpu_svm *svm,
1418 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1419 int (*handler)(struct vcpu_svm *svm,
1420 void *arg1,
1421 void *arg2,
1422 void *opaque))
1423{
1424 struct page *arg1_page;
1425 struct page *arg2_page = NULL;
1426 void *arg1;
1427 void *arg2 = NULL;
1428 int retval;
1429
1430 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1431 if(arg1_page == NULL)
1432 return 1;
1433
1434 if (arg2_gpa) {
1435 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1436 if(arg2_page == NULL) {
1437 kvm_release_page_clean(arg1_page);
1438 return 1;
1439 }
1440 }
1441
1442 arg1 = kmap_atomic(arg1_page, KM_USER0);
1443 if (arg2_gpa)
1444 arg2 = kmap_atomic(arg2_page, KM_USER1);
1445
1446 retval = handler(svm, arg1, arg2, opaque);
1447
1448 kunmap_atomic(arg1, KM_USER0);
1449 if (arg2_gpa)
1450 kunmap_atomic(arg2, KM_USER1);
1451
1452 kvm_release_page_dirty(arg1_page);
1453 if (arg2_gpa)
1454 kvm_release_page_dirty(arg2_page);
1455
1456 return retval;
1457}
1458
cf74a78b
AG		 1459static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1460 void *arg1,
1461 void *arg2,
1462 void *opaque)
1463{
cf74a78b
AG		 1464 bool kvm_overrides = *(bool *)opaque;
1465 u32 exit_code = svm->vmcb->control.exit_code;
1466
1467 if (kvm_overrides) {
1468 switch (exit_code) {
1469 case SVM_EXIT_INTR:
1470 case SVM_EXIT_NMI:
1471 return 0;
1472 /* For now we are always handling NPFs when using them */
1473 case SVM_EXIT_NPF:
1474 if (npt_enabled)
1475 return 0;
1476 break;
1477 /* When we're shadowing, trap PFs */
1478 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1479 if (!npt_enabled)
1480 return 0;
1481 break;
1482 default:
1483 break;
1484 }
1485 }
1486
1487 switch (exit_code) {
1488 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1489 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1490 if (svm->nested.intercept_cr_read & cr_bits)
cf74a78b
AG		 1491 return 1;
1492 break;
1493 }
1494 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1495 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1496 if (svm->nested.intercept_cr_write & cr_bits)
cf74a78b
AG		 1497 return 1;
1498 break;
1499 }
1500 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1501 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1502 if (svm->nested.intercept_dr_read & dr_bits)
cf74a78b
AG		 1503 return 1;
1504 break;
1505 }
1506 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1507 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1508 if (svm->nested.intercept_dr_write & dr_bits)
cf74a78b
AG		 1509 return 1;
1510 break;
1511 }
1512 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1513 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1514 if (svm->nested.intercept_exceptions & excp_bits)
cf74a78b
AG		 1515 return 1;
1516 break;
1517 }
1518 default: {
1519 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1520 nsvm_printk("exit code: 0x%x\n", exit_code);
aad42c64 1521 if (svm->nested.intercept & exit_bits)
cf74a78b
AG		 1522 return 1;
1523 }
1524 }
1525
1526 return 0;
1527}
1528
1529static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1530 void *arg1, void *arg2,
1531 void *opaque)
1532{
1533 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1534 u8 *msrpm = (u8 *)arg2;
1535 u32 t0, t1;
1536 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1537 u32 param = svm->vmcb->control.exit_info_1 & 1;
1538
1539 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1540 return 0;
1541
1542 switch(msr) {
1543 case 0 ... 0x1fff:
1544 t0 = (msr * 2) % 8;
1545 t1 = msr / 8;
1546 break;
1547 case 0xc0000000 ... 0xc0001fff:
1548 t0 = (8192 + msr - 0xc0000000) * 2;
1549 t1 = (t0 / 8);
1550 t0 %= 8;
1551 break;
1552 case 0xc0010000 ... 0xc0011fff:
1553 t0 = (16384 + msr - 0xc0010000) * 2;
1554 t1 = (t0 / 8);
1555 t0 %= 8;
1556 break;
1557 default:
1558 return 1;
1559 break;
1560 }
1561 if (msrpm[t1] & ((1 << param) << t0))
1562 return 1;
1563
1564 return 0;
1565}
1566
1567static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1568{
1569 bool k = kvm_override;
1570
1571 switch (svm->vmcb->control.exit_code) {
1572 case SVM_EXIT_MSR:
e6aa9abd
JR		 1573 return nested_svm_do(svm, svm->nested.vmcb,
1574 svm->nested.vmcb_msrpm, NULL,
cf74a78b
AG		 1575 nested_svm_exit_handled_msr);
1576 default: break;
1577 }
1578
e6aa9abd 1579 return nested_svm_do(svm, svm->nested.vmcb, 0, &k,
cf74a78b
AG		 1580 nested_svm_exit_handled_real);
1581}
1582
0460a979
JR		 1583static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1584{
1585 struct vmcb_control_area *dst = &dst_vmcb->control;
1586 struct vmcb_control_area *from = &from_vmcb->control;
1587
1588 dst->intercept_cr_read = from->intercept_cr_read;
1589 dst->intercept_cr_write = from->intercept_cr_write;
1590 dst->intercept_dr_read = from->intercept_dr_read;
1591 dst->intercept_dr_write = from->intercept_dr_write;
1592 dst->intercept_exceptions = from->intercept_exceptions;
1593 dst->intercept = from->intercept;
1594 dst->iopm_base_pa = from->iopm_base_pa;
1595 dst->msrpm_base_pa = from->msrpm_base_pa;
1596 dst->tsc_offset = from->tsc_offset;
1597 dst->asid = from->asid;
1598 dst->tlb_ctl = from->tlb_ctl;
1599 dst->int_ctl = from->int_ctl;
1600 dst->int_vector = from->int_vector;
1601 dst->int_state = from->int_state;
1602 dst->exit_code = from->exit_code;
1603 dst->exit_code_hi = from->exit_code_hi;
1604 dst->exit_info_1 = from->exit_info_1;
1605 dst->exit_info_2 = from->exit_info_2;
1606 dst->exit_int_info = from->exit_int_info;
1607 dst->exit_int_info_err = from->exit_int_info_err;
1608 dst->nested_ctl = from->nested_ctl;
1609 dst->event_inj = from->event_inj;
1610 dst->event_inj_err = from->event_inj_err;
1611 dst->nested_cr3 = from->nested_cr3;
1612 dst->lbr_ctl = from->lbr_ctl;
1613}
1614
cf74a78b
AG		 1615static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1616 void *arg2, void *opaque)
1617{
1618 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
e6aa9abd 1619 struct vmcb *hsave = svm->nested.hsave;
33740e40 1620 struct vmcb *vmcb = svm->vmcb;
cf74a78b
AG		 1621
1622 /* Give the current vmcb to the guest */
33740e40
JR		 1623 disable_gif(svm);
1624
1625 nested_vmcb->save.es = vmcb->save.es;
1626 nested_vmcb->save.cs = vmcb->save.cs;
1627 nested_vmcb->save.ss = vmcb->save.ss;
1628 nested_vmcb->save.ds = vmcb->save.ds;
1629 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1630 nested_vmcb->save.idtr = vmcb->save.idtr;
1631 if (npt_enabled)
1632 nested_vmcb->save.cr3 = vmcb->save.cr3;
1633 nested_vmcb->save.cr2 = vmcb->save.cr2;
1634 nested_vmcb->save.rflags = vmcb->save.rflags;
1635 nested_vmcb->save.rip = vmcb->save.rip;
1636 nested_vmcb->save.rsp = vmcb->save.rsp;
1637 nested_vmcb->save.rax = vmcb->save.rax;
1638 nested_vmcb->save.dr7 = vmcb->save.dr7;
1639 nested_vmcb->save.dr6 = vmcb->save.dr6;
1640 nested_vmcb->save.cpl = vmcb->save.cpl;
1641
1642 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1643 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1644 nested_vmcb->control.int_state = vmcb->control.int_state;
1645 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1646 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1647 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1648 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1649 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1650 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1651 nested_vmcb->control.tlb_ctl = 0;
1652 nested_vmcb->control.event_inj = 0;
1653 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1654
1655 /* We always set V_INTR_MASKING and remember the old value in hflags */
1656 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1657 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1658
cf74a78b 1659 /* Restore the original control entries */
0460a979 1660 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1661
1662 /* Kill any pending exceptions */
1663 if (svm->vcpu.arch.exception.pending == true)
1664 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1665
219b65dc
AG		 1666 kvm_clear_exception_queue(&svm->vcpu);
1667 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1668
1669 /* Restore selected save entries */
1670 svm->vmcb->save.es = hsave->save.es;
1671 svm->vmcb->save.cs = hsave->save.cs;
1672 svm->vmcb->save.ss = hsave->save.ss;
1673 svm->vmcb->save.ds = hsave->save.ds;
1674 svm->vmcb->save.gdtr = hsave->save.gdtr;
1675 svm->vmcb->save.idtr = hsave->save.idtr;
1676 svm->vmcb->save.rflags = hsave->save.rflags;
1677 svm_set_efer(&svm->vcpu, hsave->save.efer);
1678 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1679 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1680 if (npt_enabled) {
1681 svm->vmcb->save.cr3 = hsave->save.cr3;
1682 svm->vcpu.arch.cr3 = hsave->save.cr3;
1683 } else {
1684 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1685 }
1686 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1687 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1688 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1689 svm->vmcb->save.dr7 = 0;
1690 svm->vmcb->save.cpl = 0;
1691 svm->vmcb->control.exit_int_info = 0;
1692
cf74a78b 1693 /* Exit nested SVM mode */
e6aa9abd 1694 svm->nested.vmcb = 0;
cf74a78b
AG		 1695
1696 return 0;
1697}
1698
1699static int nested_svm_vmexit(struct vcpu_svm *svm)
1700{
1701 nsvm_printk("VMexit\n");
e6aa9abd 1702 if (nested_svm_do(svm, svm->nested.vmcb, 0,
cf74a78b
AG		 1703 NULL, nested_svm_vmexit_real))
1704 return 1;
1705
1706 kvm_mmu_reset_context(&svm->vcpu);
1707 kvm_mmu_load(&svm->vcpu);
1708
1709 return 0;
1710}
3d6368ef
AG		 1711
1712static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1713 void *arg2, void *opaque)
1714{
1715 int i;
1716 u32 *nested_msrpm = (u32*)arg1;
1717 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd
JR		 1718 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1719 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef
AG		 1720
1721 return 0;
1722}
1723
1724static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1725 void *arg2, void *opaque)
1726{
1727 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
e6aa9abd 1728 struct vmcb *hsave = svm->nested.hsave;
defbba56 1729 struct vmcb *vmcb = svm->vmcb;
3d6368ef
AG		 1730
1731 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1732 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef
AG		 1733
1734 /* Clear internal status */
219b65dc
AG		 1735 kvm_clear_exception_queue(&svm->vcpu);
1736 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1737
1738 /* Save the old vmcb, so we don't need to pick what we save, but
1739 can restore everything when a VMEXIT occurs */
defbba56
JR		 1740 hsave->save.es = vmcb->save.es;
1741 hsave->save.cs = vmcb->save.cs;
1742 hsave->save.ss = vmcb->save.ss;
1743 hsave->save.ds = vmcb->save.ds;
1744 hsave->save.gdtr = vmcb->save.gdtr;
1745 hsave->save.idtr = vmcb->save.idtr;
1746 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1747 hsave->save.cr0 = svm->vcpu.arch.cr0;
1748 hsave->save.cr4 = svm->vcpu.arch.cr4;
1749 hsave->save.rflags = vmcb->save.rflags;
1750 hsave->save.rip = svm->next_rip;
1751 hsave->save.rsp = vmcb->save.rsp;
1752 hsave->save.rax = vmcb->save.rax;
1753 if (npt_enabled)
1754 hsave->save.cr3 = vmcb->save.cr3;
1755 else
1756 hsave->save.cr3 = svm->vcpu.arch.cr3;
1757
0460a979 1758 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1759
1760 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1761 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1762 else
1763 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1764
1765 /* Load the nested guest state */
1766 svm->vmcb->save.es = nested_vmcb->save.es;
1767 svm->vmcb->save.cs = nested_vmcb->save.cs;
1768 svm->vmcb->save.ss = nested_vmcb->save.ss;
1769 svm->vmcb->save.ds = nested_vmcb->save.ds;
1770 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1771 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1772 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1773 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1774 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1775 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1776 if (npt_enabled) {
1777 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1778 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1779 } else {
1780 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1781 kvm_mmu_reset_context(&svm->vcpu);
1782 }
defbba56 1783 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1784 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1785 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1786 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1787 /* In case we don't even reach vcpu_run, the fields are not updated */
1788 svm->vmcb->save.rax = nested_vmcb->save.rax;
1789 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1790 svm->vmcb->save.rip = nested_vmcb->save.rip;
1791 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1792 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1793 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1794
1795 /* We don't want a nested guest to be more powerful than the guest,
1796 so all intercepts are ORed */
1797 svm->vmcb->control.intercept_cr_read |=
1798 nested_vmcb->control.intercept_cr_read;
1799 svm->vmcb->control.intercept_cr_write |=
1800 nested_vmcb->control.intercept_cr_write;
1801 svm->vmcb->control.intercept_dr_read |=
1802 nested_vmcb->control.intercept_dr_read;
1803 svm->vmcb->control.intercept_dr_write |=
1804 nested_vmcb->control.intercept_dr_write;
1805 svm->vmcb->control.intercept_exceptions |=
1806 nested_vmcb->control.intercept_exceptions;
1807
1808 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1809
e6aa9abd 1810 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1811
aad42c64
JR		 1812 /* cache intercepts */
1813 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1814 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1815 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1816 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1817 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1818 svm->nested.intercept = nested_vmcb->control.intercept;
1819
3d6368ef
AG		 1820 force_new_asid(&svm->vcpu);
1821 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1822 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1823 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1824 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1825 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1826 nested_vmcb->control.int_ctl);
1827 }
1828 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1829 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1830 else
1831 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1832
1833 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1834 nested_vmcb->control.exit_int_info,
1835 nested_vmcb->control.int_state);
1836
1837 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1838 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1839 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1840 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1841 nsvm_printk("Injecting Event: 0x%x\n",
1842 nested_vmcb->control.event_inj);
1843 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1844 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1845
2af9194d 1846 enable_gif(svm);
3d6368ef
AG		 1847
1848 return 0;
1849}
1850
5542675b
AG		 1851static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1852{
1853 to_vmcb->save.fs = from_vmcb->save.fs;
1854 to_vmcb->save.gs = from_vmcb->save.gs;
1855 to_vmcb->save.tr = from_vmcb->save.tr;
1856 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1857 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1858 to_vmcb->save.star = from_vmcb->save.star;
1859 to_vmcb->save.lstar = from_vmcb->save.lstar;
1860 to_vmcb->save.cstar = from_vmcb->save.cstar;
1861 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1862 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1863 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1864 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1865
1866 return 1;
1867}
1868
1869static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1870 void *arg2, void *opaque)
1871{
1872 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1873}
1874
1875static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1876 void *arg2, void *opaque)
1877{
1878 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1879}
1880
1881static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1882{
1883 if (nested_svm_check_permissions(svm))
1884 return 1;
1885
1886 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1887 skip_emulated_instruction(&svm->vcpu);
1888
1889 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1890
1891 return 1;
1892}
1893
1894static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1895{
1896 if (nested_svm_check_permissions(svm))
1897 return 1;
1898
1899 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900 skip_emulated_instruction(&svm->vcpu);
1901
1902 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1903
1904 return 1;
1905}
1906
3d6368ef
AG		 1907static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1908{
1909 nsvm_printk("VMrun\n");
1910 if (nested_svm_check_permissions(svm))
1911 return 1;
1912
1913 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1914 skip_emulated_instruction(&svm->vcpu);
1915
1916 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1917 NULL, nested_svm_vmrun))
1918 return 1;
1919
e6aa9abd 1920 if (nested_svm_do(svm, svm->nested.vmcb_msrpm, 0,
3d6368ef
AG		 1921 NULL, nested_svm_vmrun_msrpm))
1922 return 1;
1923
1924 return 1;
1925}
1926
1371d904
AG		 1927static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1928{
1929 if (nested_svm_check_permissions(svm))
1930 return 1;
1931
1932 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1933 skip_emulated_instruction(&svm->vcpu);
1934
2af9194d 1935 enable_gif(svm);
1371d904
AG		 1936
1937 return 1;
1938}
1939
1940static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1941{
1942 if (nested_svm_check_permissions(svm))
1943 return 1;
1944
1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946 skip_emulated_instruction(&svm->vcpu);
1947
2af9194d 1948 disable_gif(svm);
1371d904
AG		 1949
1950 /* After a CLGI no interrupts should come */
1951 svm_clear_vintr(svm);
1952 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1953
1954 return 1;
1955}
1956
ff092385
AG		 1957static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1958{
1959 struct kvm_vcpu *vcpu = &svm->vcpu;
1960 nsvm_printk("INVLPGA\n");
1961
1962 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1963 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1964
1965 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1966 skip_emulated_instruction(&svm->vcpu);
1967 return 1;
1968}
1969
e756fc62
RR		 1970static int invalid_op_interception(struct vcpu_svm *svm,
1971 struct kvm_run *kvm_run)
6aa8b732 1972{
7ee5d940 1973 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1974 return 1;
1975}
1976
e756fc62
RR		 1977static int task_switch_interception(struct vcpu_svm *svm,
1978 struct kvm_run *kvm_run)
6aa8b732 1979{
37817f29 1980 u16 tss_selector;
64a7ec06
GN		 1981 int reason;
1982 int int_type = svm->vmcb->control.exit_int_info &
1983 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1984 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1985 uint32_t type =
1986 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1987 uint32_t idt_v =
1988 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1989
1990 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1991
37817f29
IE		 1992 if (svm->vmcb->control.exit_info_2 &
1993 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1994 reason = TASK_SWITCH_IRET;
1995 else if (svm->vmcb->control.exit_info_2 &
1996 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1997 reason = TASK_SWITCH_JMP;
fe8e7f83 1998 else if (idt_v)
64a7ec06
GN		 1999 reason = TASK_SWITCH_GATE;
2000 else
2001 reason = TASK_SWITCH_CALL;
2002
fe8e7f83
GN		 2003 if (reason == TASK_SWITCH_GATE) {
2004 switch (type) {
2005 case SVM_EXITINTINFO_TYPE_NMI:
2006 svm->vcpu.arch.nmi_injected = false;
2007 break;
2008 case SVM_EXITINTINFO_TYPE_EXEPT:
2009 kvm_clear_exception_queue(&svm->vcpu);
2010 break;
2011 case SVM_EXITINTINFO_TYPE_INTR:
2012 kvm_clear_interrupt_queue(&svm->vcpu);
2013 break;
2014 default:
2015 break;
2016 }
2017 }
64a7ec06 2018
8317c298
GN		 2019 if (reason != TASK_SWITCH_GATE ||
2020 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2021 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2022 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2023 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2024
2025 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2026}
2027
e756fc62 2028static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2029{
5fdbf976 2030 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2031 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2032 return 1;
6aa8b732
AK		 2033}
2034
95ba8273
GN		 2035static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2036{
2037 ++svm->vcpu.stat.nmi_window_exits;
2038 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2039 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2040 return 1;
2041}
2042
a7052897
MT		 2043static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2044{
2045 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2046 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2047 return 1;
2048}
2049
e756fc62
RR		 2050static int emulate_on_interception(struct vcpu_svm *svm,
2051 struct kvm_run *kvm_run)
6aa8b732 2052{
3427318f 2053 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 2054 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2055 return 1;
2056}
2057
1d075434
JR		 2058static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2059{
0a5fff19
GN		 2060 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2061 /* instruction emulation calls kvm_set_cr8() */
1d075434 2062 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 2063 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2064 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2065 return 1;
95ba8273 2066 }
0a5fff19
GN		 2067 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2068 return 1;
1d075434
JR		 2069 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2070 return 0;
2071}
2072
6aa8b732
AK		 2073static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2074{
a2fa3e9f
GH		 2075 struct vcpu_svm *svm = to_svm(vcpu);
2076
6aa8b732 2077 switch (ecx) {
af24a4e4 2078 case MSR_IA32_TSC: {
6aa8b732
AK		 2079 u64 tsc;
2080
2081 rdtscll(tsc);
a2fa3e9f 2082 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2083 break;
2084 }
0e859cac 2085 case MSR_K6_STAR:
a2fa3e9f 2086 *data = svm->vmcb->save.star;
6aa8b732 2087 break;
0e859cac 2088#ifdef CONFIG_X86_64
6aa8b732 2089 case MSR_LSTAR:
a2fa3e9f 2090 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2091 break;
2092 case MSR_CSTAR:
a2fa3e9f 2093 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2094 break;
2095 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2096 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2097 break;
2098 case MSR_SYSCALL_MASK:
a2fa3e9f 2099 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2100 break;
2101#endif
2102 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2103 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2104 break;
2105 case MSR_IA32_SYSENTER_EIP:
017cb99e 2106 *data = svm->sysenter_eip;
6aa8b732
AK		 2107 break;
2108 case MSR_IA32_SYSENTER_ESP:
017cb99e 2109 *data = svm->sysenter_esp;
6aa8b732 2110 break;
a2938c80
JR		 2111 /* Nobody will change the following 5 values in the VMCB so
2112 we can safely return them on rdmsr. They will always be 0
2113 until LBRV is implemented. */
2114 case MSR_IA32_DEBUGCTLMSR:
2115 *data = svm->vmcb->save.dbgctl;
2116 break;
2117 case MSR_IA32_LASTBRANCHFROMIP:
2118 *data = svm->vmcb->save.br_from;
2119 break;
2120 case MSR_IA32_LASTBRANCHTOIP:
2121 *data = svm->vmcb->save.br_to;
2122 break;
2123 case MSR_IA32_LASTINTFROMIP:
2124 *data = svm->vmcb->save.last_excp_from;
2125 break;
2126 case MSR_IA32_LASTINTTOIP:
2127 *data = svm->vmcb->save.last_excp_to;
2128 break;
b286d5d8 2129 case MSR_VM_HSAVE_PA:
e6aa9abd 2130 *data = svm->nested.hsave_msr;
b286d5d8 2131 break;
eb6f302e
JR		 2132 case MSR_VM_CR:
2133 *data = 0;
2134 break;
c8a73f18
AG		 2135 case MSR_IA32_UCODE_REV:
2136 *data = 0x01000065;
2137 break;
6aa8b732 2138 default:
3bab1f5d 2139 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2140 }
2141 return 0;
2142}
2143
e756fc62 2144static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2145{
ad312c7c 2146 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2147 u64 data;
2148
e756fc62 2149 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2150 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2151 else {
229456fc 2152 trace_kvm_msr_read(ecx, data);
af9ca2d7 2153
5fdbf976 2154 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2155 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2156 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2157 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2158 }
2159 return 1;
2160}
2161
2162static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2163{
a2fa3e9f
GH		 2164 struct vcpu_svm *svm = to_svm(vcpu);
2165
6aa8b732 2166 switch (ecx) {
af24a4e4 2167 case MSR_IA32_TSC: {
6aa8b732
AK		 2168 u64 tsc;
2169
2170 rdtscll(tsc);
a2fa3e9f 2171 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2172 break;
2173 }
0e859cac 2174 case MSR_K6_STAR:
a2fa3e9f 2175 svm->vmcb->save.star = data;
6aa8b732 2176 break;
49b14f24 2177#ifdef CONFIG_X86_64
6aa8b732 2178 case MSR_LSTAR:
a2fa3e9f 2179 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2180 break;
2181 case MSR_CSTAR:
a2fa3e9f 2182 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2183 break;
2184 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2185 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2186 break;
2187 case MSR_SYSCALL_MASK:
a2fa3e9f 2188 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2189 break;
2190#endif
2191 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2192 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2193 break;
2194 case MSR_IA32_SYSENTER_EIP:
017cb99e 2195 svm->sysenter_eip = data;
a2fa3e9f 2196 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2197 break;
2198 case MSR_IA32_SYSENTER_ESP:
017cb99e 2199 svm->sysenter_esp = data;
a2fa3e9f 2200 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2201 break;
a2938c80 2202 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2203 if (!svm_has(SVM_FEATURE_LBRV)) {
2204 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2205 __func__, data);
24e09cbf
JR		 2206 break;
2207 }
2208 if (data & DEBUGCTL_RESERVED_BITS)
2209 return 1;
2210
2211 svm->vmcb->save.dbgctl = data;
2212 if (data & (1ULL<<0))
2213 svm_enable_lbrv(svm);
2214 else
2215 svm_disable_lbrv(svm);
a2938c80 2216 break;
b286d5d8 2217 case MSR_VM_HSAVE_PA:
e6aa9abd 2218 svm->nested.hsave_msr = data;
62b9abaa 2219 break;
3c5d0a44
AG		 2220 case MSR_VM_CR:
2221 case MSR_VM_IGNNE:
3c5d0a44
AG		 2222 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2223 break;
6aa8b732 2224 default:
3bab1f5d 2225 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2226 }
2227 return 0;
2228}
2229
e756fc62 2230static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2231{
ad312c7c 2232 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2233 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2234 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2235
229456fc 2236 trace_kvm_msr_write(ecx, data);
af9ca2d7 2237
5fdbf976 2238 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2239 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2240 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2241 else
e756fc62 2242 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2243 return 1;
2244}
2245
e756fc62 2246static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2247{
e756fc62
RR		 2248 if (svm->vmcb->control.exit_info_1)
2249 return wrmsr_interception(svm, kvm_run);
6aa8b732 2250 else
e756fc62 2251 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2252}
2253
e756fc62 2254static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2255 struct kvm_run *kvm_run)
2256{
f0b85051 2257 svm_clear_vintr(svm);
85f455f7 2258 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2259 /*
2260 * If the user space waits to inject interrupts, exit as soon as
2261 * possible
2262 */
8061823a
GN		 2263 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2264 kvm_run->request_interrupt_window &&
2265 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2266 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2267 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2268 return 0;
2269 }
2270
2271 return 1;
2272}
2273
e756fc62 2274static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2275 struct kvm_run *kvm_run) = {
2276 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2277 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2278 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2279 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2280 /* for now: */
2281 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2282 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2283 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2284 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2285 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2286 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2287 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2288 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2289 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2290 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2291 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2292 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2293 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2294 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2295 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2296 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2297 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2298 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2299 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2300 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2301 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2302 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2303 [SVM_EXIT_SMI] = nop_on_interception,
2304 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2305 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2306 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2307 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2308 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2309 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2310 [SVM_EXIT_HLT] = halt_interception,
a7052897 2311 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2312 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2313 [SVM_EXIT_IOIO] = io_interception,
2314 [SVM_EXIT_MSR] = msr_interception,
2315 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2316 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2317 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2318 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2319 [SVM_EXIT_VMLOAD] = vmload_interception,
2320 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2321 [SVM_EXIT_STGI] = stgi_interception,
2322 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2323 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2324 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2325 [SVM_EXIT_MONITOR] = invalid_op_interception,
2326 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2327 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2328};
2329
04d2cc77 2330static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2331{
04d2cc77 2332 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2333 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2334
229456fc 2335 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2336
cf74a78b
AG		 2337 if (is_nested(svm)) {
2338 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2339 exit_code, svm->vmcb->control.exit_info_1,
2340 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2341 if (nested_svm_exit_handled(svm, true)) {
2342 nested_svm_vmexit(svm);
2343 nsvm_printk("-> #VMEXIT\n");
2344 return 1;
2345 }
2346 }
2347
a5c3832d
JR		 2348 svm_complete_interrupts(svm);
2349
709ddebf
JR		 2350 if (npt_enabled) {
2351 int mmu_reload = 0;
2352 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2353 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2354 mmu_reload = 1;
2355 }
2356 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2357 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2358 if (mmu_reload) {
2359 kvm_mmu_reset_context(vcpu);
2360 kvm_mmu_load(vcpu);
2361 }
2362 }
2363
04d2cc77
AK		 2364
2365 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2366 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2367 kvm_run->fail_entry.hardware_entry_failure_reason
2368 = svm->vmcb->control.exit_code;
2369 return 0;
2370 }
2371
a2fa3e9f 2372 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2373 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2374 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2375 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2376 "exit_code 0x%x\n",
b8688d51 2377 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2378 exit_code);
2379
9d8f549d 2380 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2381 || !svm_exit_handlers[exit_code]) {
6aa8b732 2382 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2383 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2384 return 0;
2385 }
2386
e756fc62 2387 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2388}
2389
2390static void reload_tss(struct kvm_vcpu *vcpu)
2391{
2392 int cpu = raw_smp_processor_id();
2393
2394 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2395 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2396 load_TR_desc();
2397}
2398
e756fc62 2399static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2400{
2401 int cpu = raw_smp_processor_id();
2402
2403 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2404
a2fa3e9f 2405 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2406 /* FIXME: handle wraparound of asid_generation */
2407 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2408 new_asid(svm, svm_data);
6aa8b732
AK		 2409}
2410
95ba8273
GN		 2411static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2412{
2413 struct vcpu_svm *svm = to_svm(vcpu);
2414
2415 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2416 vcpu->arch.hflags |= HF_NMI_MASK;
2417 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2418 ++vcpu->stat.nmi_injections;
2419}
6aa8b732 2420
85f455f7 2421static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2422{
2423 struct vmcb_control_area *control;
2424
229456fc 2425 trace_kvm_inj_virq(irq);
af9ca2d7 2426
fa89a817 2427 ++svm->vcpu.stat.irq_injections;
e756fc62 2428 control = &svm->vmcb->control;
85f455f7 2429 control->int_vector = irq;
6aa8b732
AK		 2430 control->int_ctl &= ~V_INTR_PRIO_MASK;
2431 control->int_ctl |= V_IRQ_MASK |
2432 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2433}
2434
66fd3f7f 2435static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2436{
2437 struct vcpu_svm *svm = to_svm(vcpu);
2438
2af9194d 2439 BUG_ON(!(gif_set(svm)));
cf74a78b 2440
219b65dc
AG		 2441 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2442 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2443}
2444
95ba8273 2445static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2446{
2447 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2448
95ba8273 2449 if (irr == -1)
aaacfc9a
JR		 2450 return;
2451
95ba8273
GN		 2452 if (tpr >= irr)
2453 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2454}
aaacfc9a 2455
95ba8273
GN		 2456static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2457{
2458 struct vcpu_svm *svm = to_svm(vcpu);
2459 struct vmcb *vmcb = svm->vmcb;
2460 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2461 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2462}
2463
78646121
GN		 2464static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2465{
2466 struct vcpu_svm *svm = to_svm(vcpu);
2467 struct vmcb *vmcb = svm->vmcb;
2468 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2469 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2470 gif_set(svm) &&
219b65dc 2471 !is_nested(svm);
78646121
GN		 2472}
2473
9222be18 2474static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2475{
219b65dc
AG		 2476 struct vcpu_svm *svm = to_svm(vcpu);
2477 nsvm_printk("Trying to open IRQ window\n");
2478
2479 nested_svm_intr(svm);
2480
2481 /* In case GIF=0 we can't rely on the CPU to tell us when
2482 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2483 * The next time we get that intercept, this function will be
2484 * called again though and we'll get the vintr intercept. */
2af9194d 2485 if (gif_set(svm)) {
219b65dc
AG		 2486 svm_set_vintr(svm);
2487 svm_inject_irq(svm, 0x0);
2488 }
85f455f7
ED		 2489}
2490
95ba8273 2491static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2492{
04d2cc77 2493 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2494
44c11430
GN		 2495 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2496 == HF_NMI_MASK)
2497 return; /* IRET will cause a vm exit */
2498
2499 /* Something prevents NMI from been injected. Single step over
2500 possible problem (IRET or exception injection or interrupt
2501 shadow) */
2502 vcpu->arch.singlestep = true;
2503 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2504 update_db_intercept(vcpu);
c1150d8c
DL		 2505}
2506
cbc94022
IE		 2507static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2508{
2509 return 0;
2510}
2511
d9e368d6
AK		 2512static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2513{
2514 force_new_asid(vcpu);
2515}
2516
04d2cc77
AK		 2517static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2518{
2519}
2520
d7bf8221
JR		 2521static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2522{
2523 struct vcpu_svm *svm = to_svm(vcpu);
2524
2525 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2526 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2527 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2528 }
2529}
2530
649d6864
JR		 2531static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2532{
2533 struct vcpu_svm *svm = to_svm(vcpu);
2534 u64 cr8;
2535
649d6864
JR		 2536 cr8 = kvm_get_cr8(vcpu);
2537 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2538 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2539}
2540
9222be18
GN		 2541static void svm_complete_interrupts(struct vcpu_svm *svm)
2542{
2543 u8 vector;
2544 int type;
2545 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2546
44c11430
GN		 2547 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2548 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2549
9222be18
GN		 2550 svm->vcpu.arch.nmi_injected = false;
2551 kvm_clear_exception_queue(&svm->vcpu);
2552 kvm_clear_interrupt_queue(&svm->vcpu);
2553
2554 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2555 return;
2556
2557 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2558 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2559
2560 switch (type) {
2561 case SVM_EXITINTINFO_TYPE_NMI:
2562 svm->vcpu.arch.nmi_injected = true;
2563 break;
2564 case SVM_EXITINTINFO_TYPE_EXEPT:
2565 /* In case of software exception do not reinject an exception
2566 vector, but re-execute and instruction instead */
219b65dc
AG		 2567 if (is_nested(svm))
2568 break;
66fd3f7f 2569 if (kvm_exception_is_soft(vector))
9222be18
GN		 2570 break;
2571 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2572 u32 err = svm->vmcb->control.exit_int_info_err;
2573 kvm_queue_exception_e(&svm->vcpu, vector, err);
2574
2575 } else
2576 kvm_queue_exception(&svm->vcpu, vector);
2577 break;
2578 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2579 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2580 break;
2581 default:
2582 break;
2583 }
2584}
2585
80e31d4f
AK		 2586#ifdef CONFIG_X86_64
2587#define R "r"
2588#else
2589#define R "e"
2590#endif
2591
04d2cc77 2592static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2593{
a2fa3e9f 2594 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2595 u16 fs_selector;
2596 u16 gs_selector;
2597 u16 ldt_selector;
d9e368d6 2598
5fdbf976
MT		 2599 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2600 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2601 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2602
e756fc62 2603 pre_svm_run(svm);
6aa8b732 2604
649d6864
JR		 2605 sync_lapic_to_cr8(vcpu);
2606
6aa8b732 2607 save_host_msrs(vcpu);
d6e88aec
AK		 2608 fs_selector = kvm_read_fs();
2609 gs_selector = kvm_read_gs();
2610 ldt_selector = kvm_read_ldt();
3d6368ef
AG		 2611 if (!is_nested(svm))
2612 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2613 /* required for live migration with NPT */
2614 if (npt_enabled)
2615 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2616
04d2cc77
AK		 2617 clgi();
2618
2619 local_irq_enable();
36241b8c 2620
6aa8b732 2621 asm volatile (
80e31d4f
AK		 2622 "push %%"R"bp; \n\t"
2623 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2624 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2625 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2626 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2627 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2628 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2629#ifdef CONFIG_X86_64
fb3f0f51
RR		 2630 "mov %c[r8](%[svm]), %%r8 \n\t"
2631 "mov %c[r9](%[svm]), %%r9 \n\t"
2632 "mov %c[r10](%[svm]), %%r10 \n\t"
2633 "mov %c[r11](%[svm]), %%r11 \n\t"
2634 "mov %c[r12](%[svm]), %%r12 \n\t"
2635 "mov %c[r13](%[svm]), %%r13 \n\t"
2636 "mov %c[r14](%[svm]), %%r14 \n\t"
2637 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2638#endif
2639
6aa8b732 2640 /* Enter guest mode */
80e31d4f
AK		 2641 "push %%"R"ax \n\t"
2642 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2643 __ex(SVM_VMLOAD) "\n\t"
2644 __ex(SVM_VMRUN) "\n\t"
2645 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2646 "pop %%"R"ax \n\t"
6aa8b732
AK		 2647
2648 /* Save guest registers, load host registers */
80e31d4f
AK		 2649 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2650 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2651 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2652 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2653 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2654 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2655#ifdef CONFIG_X86_64
fb3f0f51
RR		 2656 "mov %%r8, %c[r8](%[svm]) \n\t"
2657 "mov %%r9, %c[r9](%[svm]) \n\t"
2658 "mov %%r10, %c[r10](%[svm]) \n\t"
2659 "mov %%r11, %c[r11](%[svm]) \n\t"
2660 "mov %%r12, %c[r12](%[svm]) \n\t"
2661 "mov %%r13, %c[r13](%[svm]) \n\t"
2662 "mov %%r14, %c[r14](%[svm]) \n\t"
2663 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2664#endif
80e31d4f 2665 "pop %%"R"bp"
6aa8b732 2666 :
fb3f0f51 2667 : [svm]"a"(svm),
6aa8b732 2668 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2669 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2670 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2671 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2672 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2673 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2674 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2675#ifdef CONFIG_X86_64
ad312c7c
ZX		 2676 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2677 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2678 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2679 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2680 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2681 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2682 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2683 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2684#endif
54a08c04 2685 : "cc", "memory"
80e31d4f 2686 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2687#ifdef CONFIG_X86_64
54a08c04
LV		 2688 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2689#endif
2690 );
6aa8b732 2691
ad312c7c 2692 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2693 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2694 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2695 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2696
d6e88aec
AK		 2697 kvm_load_fs(fs_selector);
2698 kvm_load_gs(gs_selector);
2699 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2700 load_host_msrs(vcpu);
2701
2702 reload_tss(vcpu);
2703
56ba47dd
AK		 2704 local_irq_disable();
2705
2706 stgi();
2707
d7bf8221
JR		 2708 sync_cr8_to_lapic(vcpu);
2709
a2fa3e9f 2710 svm->next_rip = 0;
9222be18 2711
6de4f3ad
AK		 2712 if (npt_enabled) {
2713 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2714 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2715 }
6aa8b732
AK		 2716}
2717
80e31d4f
AK		 2718#undef R
2719
6aa8b732
AK		 2720static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2721{
a2fa3e9f
GH		 2722 struct vcpu_svm *svm = to_svm(vcpu);
2723
709ddebf
JR		 2724 if (npt_enabled) {
2725 svm->vmcb->control.nested_cr3 = root;
2726 force_new_asid(vcpu);
2727 return;
2728 }
2729
a2fa3e9f 2730 svm->vmcb->save.cr3 = root;
6aa8b732 2731 force_new_asid(vcpu);
7807fa6c
AL		 2732
2733 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2734 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2735 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2736 vcpu->fpu_active = 0;
2737 }
6aa8b732
AK		 2738}
2739
6aa8b732
AK		 2740static int is_disabled(void)
2741{
6031a61c
JR		 2742 u64 vm_cr;
2743
2744 rdmsrl(MSR_VM_CR, vm_cr);
2745 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2746 return 1;
2747
6aa8b732
AK		 2748 return 0;
2749}
2750
102d8325
IM		 2751static void
2752svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2753{
2754 /*
2755 * Patch in the VMMCALL instruction:
2756 */
2757 hypercall[0] = 0x0f;
2758 hypercall[1] = 0x01;
2759 hypercall[2] = 0xd9;
102d8325
IM		 2760}
2761
002c7f7c
YS		 2762static void svm_check_processor_compat(void *rtn)
2763{
2764 *(int *)rtn = 0;
2765}
2766
774ead3a
AK		 2767static bool svm_cpu_has_accelerated_tpr(void)
2768{
2769 return false;
2770}
2771
67253af5
SY		 2772static int get_npt_level(void)
2773{
2774#ifdef CONFIG_X86_64
2775 return PT64_ROOT_LEVEL;
2776#else
2777 return PT32E_ROOT_LEVEL;
2778#endif
2779}
2780
4b12f0de 2781static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2782{
2783 return 0;
2784}
2785
229456fc
MT		 2786static const struct trace_print_flags svm_exit_reasons_str[] = {
2787 { SVM_EXIT_READ_CR0, "read_cr0" },
2788 { SVM_EXIT_READ_CR3, "read_cr3" },
2789 { SVM_EXIT_READ_CR4, "read_cr4" },
2790 { SVM_EXIT_READ_CR8, "read_cr8" },
2791 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2792 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2793 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2794 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2795 { SVM_EXIT_READ_DR0, "read_dr0" },
2796 { SVM_EXIT_READ_DR1, "read_dr1" },
2797 { SVM_EXIT_READ_DR2, "read_dr2" },
2798 { SVM_EXIT_READ_DR3, "read_dr3" },
2799 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2800 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2801 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2802 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2803 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2804 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2805 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2806 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2807 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2808 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2809 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2810 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2811 { SVM_EXIT_INTR, "interrupt" },
2812 { SVM_EXIT_NMI, "nmi" },
2813 { SVM_EXIT_SMI, "smi" },
2814 { SVM_EXIT_INIT, "init" },
2815 { SVM_EXIT_VINTR, "vintr" },
2816 { SVM_EXIT_CPUID, "cpuid" },
2817 { SVM_EXIT_INVD, "invd" },
2818 { SVM_EXIT_HLT, "hlt" },
2819 { SVM_EXIT_INVLPG, "invlpg" },
2820 { SVM_EXIT_INVLPGA, "invlpga" },
2821 { SVM_EXIT_IOIO, "io" },
2822 { SVM_EXIT_MSR, "msr" },
2823 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2824 { SVM_EXIT_SHUTDOWN, "shutdown" },
2825 { SVM_EXIT_VMRUN, "vmrun" },
2826 { SVM_EXIT_VMMCALL, "hypercall" },
2827 { SVM_EXIT_VMLOAD, "vmload" },
2828 { SVM_EXIT_VMSAVE, "vmsave" },
2829 { SVM_EXIT_STGI, "stgi" },
2830 { SVM_EXIT_CLGI, "clgi" },
2831 { SVM_EXIT_SKINIT, "skinit" },
2832 { SVM_EXIT_WBINVD, "wbinvd" },
2833 { SVM_EXIT_MONITOR, "monitor" },
2834 { SVM_EXIT_MWAIT, "mwait" },
2835 { SVM_EXIT_NPF, "npf" },
2836 { -1, NULL }
2837};
2838
344f414f
JR		 2839static bool svm_gb_page_enable(void)
2840{
2841 return true;
2842}
2843
cbdd1bea 2844static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2845 .cpu_has_kvm_support = has_svm,
2846 .disabled_by_bios = is_disabled,
2847 .hardware_setup = svm_hardware_setup,
2848 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2849 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2850 .hardware_enable = svm_hardware_enable,
2851 .hardware_disable = svm_hardware_disable,
774ead3a 2852 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2853
2854 .vcpu_create = svm_create_vcpu,
2855 .vcpu_free = svm_free_vcpu,
04d2cc77 2856 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2857
04d2cc77 2858 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2859 .vcpu_load = svm_vcpu_load,
2860 .vcpu_put = svm_vcpu_put,
2861
2862 .set_guest_debug = svm_guest_debug,
2863 .get_msr = svm_get_msr,
2864 .set_msr = svm_set_msr,
2865 .get_segment_base = svm_get_segment_base,
2866 .get_segment = svm_get_segment,
2867 .set_segment = svm_set_segment,
2e4d2653 2868 .get_cpl = svm_get_cpl,
1747fb71 2869 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2870 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2871 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2872 .set_cr3 = svm_set_cr3,
2873 .set_cr4 = svm_set_cr4,
2874 .set_efer = svm_set_efer,
2875 .get_idt = svm_get_idt,
2876 .set_idt = svm_set_idt,
2877 .get_gdt = svm_get_gdt,
2878 .set_gdt = svm_set_gdt,
2879 .get_dr = svm_get_dr,
2880 .set_dr = svm_set_dr,
6de4f3ad 2881 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2882 .get_rflags = svm_get_rflags,
2883 .set_rflags = svm_set_rflags,
2884
6aa8b732 2885 .tlb_flush = svm_flush_tlb,
6aa8b732 2886
6aa8b732 2887 .run = svm_vcpu_run,
04d2cc77 2888 .handle_exit = handle_exit,
6aa8b732 2889 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2890 .set_interrupt_shadow = svm_set_interrupt_shadow,
2891 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2892 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2893 .set_irq = svm_set_irq,
95ba8273 2894 .set_nmi = svm_inject_nmi,
298101da 2895 .queue_exception = svm_queue_exception,
78646121 2896 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2897 .nmi_allowed = svm_nmi_allowed,
2898 .enable_nmi_window = enable_nmi_window,
2899 .enable_irq_window = enable_irq_window,
2900 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2901
2902 .set_tss_addr = svm_set_tss_addr,
67253af5 2903 .get_tdp_level = get_npt_level,
4b12f0de 2904 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2905
2906 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2907 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2908};
2909
2910static int __init svm_init(void)
2911{
cb498ea2 2912 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2913 THIS_MODULE);
6aa8b732
AK		 2914}
2915
2916static void __exit svm_exit(void)
2917{
cb498ea2 2918 kvm_exit();
6aa8b732
AK		 2919}
2920
2921module_init(svm_init)
2922module_exit(svm_exit)
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