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KVM: SVM: clean up nestec vmload/vmsave paths
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
24e09cbf
JR		 50#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
c0725420
AG		 52/* Turn on to get debugging output*/
53/* #define NESTED_DEBUG */
54
55#ifdef NESTED_DEBUG
56#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57#else
58#define nsvm_printk(fmt, args...) do {} while(0)
59#endif
60
6c8166a7
AK		 61static const u32 host_save_user_msrs[] = {
62#ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65#endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67};
68
69#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71struct kvm_vcpu;
72
e6aa9abd
JR		 73struct nested_state {
74 struct vmcb *hsave;
75 u64 hsave_msr;
76 u64 vmcb;
77
78 /* These are the merged vectors */
79 u32 *msrpm;
80
81 /* gpa pointers to the real vectors */
82 u64 vmcb_msrpm;
aad42c64
JR		 83
84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
90 u64 intercept;
91
e6aa9abd
JR		 92};
93
6c8166a7
AK		 94struct vcpu_svm {
95 struct kvm_vcpu vcpu;
96 struct vmcb *vmcb;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
102
103 u64 next_rip;
104
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
106 u64 host_gs_base;
6c8166a7
AK		 107
108 u32 *msrpm;
6c8166a7 109
e6aa9abd 110 struct nested_state nested;
6c8166a7
AK		 111};
112
709ddebf
JR		 113/* enable NPT for AMD64 and X86 with PAE */
114#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
115static bool npt_enabled = true;
116#else
e3da3acd 117static bool npt_enabled = false;
709ddebf 118#endif
6c7dac72
JR		 119static int npt = 1;
120
121module_param(npt, int, S_IRUGO);
e3da3acd 122
236de055
AG		 123static int nested = 0;
124module_param(nested, int, S_IRUGO);
125
44874f84 126static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 127static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 128
cf74a78b
AG		 129static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
130static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 131static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
132 bool has_error_code, u32 error_code);
133
a2fa3e9f
GH		 134static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
135{
fb3f0f51 136 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 137}
138
3d6368ef
AG		 139static inline bool is_nested(struct vcpu_svm *svm)
140{
e6aa9abd 141 return svm->nested.vmcb;
3d6368ef
AG		 142}
143
2af9194d
JR		 144static inline void enable_gif(struct vcpu_svm *svm)
145{
146 svm->vcpu.arch.hflags |= HF_GIF_MASK;
147}
148
149static inline void disable_gif(struct vcpu_svm *svm)
150{
151 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
152}
153
154static inline bool gif_set(struct vcpu_svm *svm)
155{
156 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
157}
158
4866d5e3 159static unsigned long iopm_base;
6aa8b732
AK		 160
161struct kvm_ldttss_desc {
162 u16 limit0;
163 u16 base0;
164 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
165 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
166 u32 base3;
167 u32 zero1;
168} __attribute__((packed));
169
170struct svm_cpu_data {
171 int cpu;
172
5008fdf5
AK		 173 u64 asid_generation;
174 u32 max_asid;
175 u32 next_asid;
6aa8b732
AK		 176 struct kvm_ldttss_desc *tss_desc;
177
178 struct page *save_area;
179};
180
181static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 182static uint32_t svm_features;
6aa8b732
AK		 183
184struct svm_init_data {
185 int cpu;
186 int r;
187};
188
189static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
190
9d8f549d 191#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 192#define MSRS_RANGE_SIZE 2048
193#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
194
195#define MAX_INST_SIZE 15
196
80b7706e
JR		 197static inline u32 svm_has(u32 feat)
198{
199 return svm_features & feat;
200}
201
6aa8b732
AK		 202static inline void clgi(void)
203{
4ecac3fd 204 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 205}
206
207static inline void stgi(void)
208{
4ecac3fd 209 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 210}
211
212static inline void invlpga(unsigned long addr, u32 asid)
213{
4ecac3fd 214 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 215}
216
6aa8b732
AK		 217static inline void force_new_asid(struct kvm_vcpu *vcpu)
218{
a2fa3e9f 219 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 220}
221
222static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
223{
224 force_new_asid(vcpu);
225}
226
227static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
228{
709ddebf 229 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 230 efer &= ~EFER_LME;
6aa8b732 231
9962d032 232 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 233 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 234}
235
298101da
AK		 236static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
237 bool has_error_code, u32 error_code)
238{
239 struct vcpu_svm *svm = to_svm(vcpu);
240
cf74a78b
AG		 241 /* If we are within a nested VM we'd better #VMEXIT and let the
242 guest handle the exception */
243 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
244 return;
245
298101da
AK		 246 svm->vmcb->control.event_inj = nr
247 | SVM_EVTINJ_VALID
248 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
249 | SVM_EVTINJ_TYPE_EXEPT;
250 svm->vmcb->control.event_inj_err = error_code;
251}
252
6aa8b732
AK		 253static int is_external_interrupt(u32 info)
254{
255 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
256 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
257}
258
2809f5d2
GC		 259static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
260{
261 struct vcpu_svm *svm = to_svm(vcpu);
262 u32 ret = 0;
263
264 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
265 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
266 return ret & mask;
267}
268
269static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
270{
271 struct vcpu_svm *svm = to_svm(vcpu);
272
273 if (mask == 0)
274 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
275 else
276 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
277
278}
279
6aa8b732
AK		 280static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
281{
a2fa3e9f
GH		 282 struct vcpu_svm *svm = to_svm(vcpu);
283
284 if (!svm->next_rip) {
f629cf84
GN		 285 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
286 EMULATE_DONE)
287 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 288 return;
289 }
5fdbf976
MT		 290 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
291 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
292 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 293
5fdbf976 294 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 295 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 296}
297
298static int has_svm(void)
299{
63d1142f 300 const char *msg;
6aa8b732 301
63d1142f 302 if (!cpu_has_svm(&msg)) {
ff81ff10 303 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 304 return 0;
305 }
306
6aa8b732
AK		 307 return 1;
308}
309
310static void svm_hardware_disable(void *garbage)
311{
2c8dceeb 312 cpu_svm_disable();
6aa8b732
AK		 313}
314
315static void svm_hardware_enable(void *garbage)
316{
317
318 struct svm_cpu_data *svm_data;
319 uint64_t efer;
b792c344 320 struct descriptor_table gdt_descr;
6aa8b732
AK		 321 struct desc_struct *gdt;
322 int me = raw_smp_processor_id();
323
324 if (!has_svm()) {
325 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
326 return;
327 }
328 svm_data = per_cpu(svm_data, me);
329
330 if (!svm_data) {
331 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
332 me);
333 return;
334 }
335
336 svm_data->asid_generation = 1;
337 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
338 svm_data->next_asid = svm_data->max_asid + 1;
339
b792c344
AM		 340 kvm_get_gdt(&gdt_descr);
341 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 342 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
343
344 rdmsrl(MSR_EFER, efer);
9962d032 345 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 346
347 wrmsrl(MSR_VM_HSAVE_PA,
348 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
349}
350
0da1db75
JR		 351static void svm_cpu_uninit(int cpu)
352{
353 struct svm_cpu_data *svm_data
354 = per_cpu(svm_data, raw_smp_processor_id());
355
356 if (!svm_data)
357 return;
358
359 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
360 __free_page(svm_data->save_area);
361 kfree(svm_data);
362}
363
6aa8b732
AK		 364static int svm_cpu_init(int cpu)
365{
366 struct svm_cpu_data *svm_data;
367 int r;
368
369 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
370 if (!svm_data)
371 return -ENOMEM;
372 svm_data->cpu = cpu;
373 svm_data->save_area = alloc_page(GFP_KERNEL);
374 r = -ENOMEM;
375 if (!svm_data->save_area)
376 goto err_1;
377
378 per_cpu(svm_data, cpu) = svm_data;
379
380 return 0;
381
382err_1:
383 kfree(svm_data);
384 return r;
385
386}
387
bfc733a7
RR		 388static void set_msr_interception(u32 *msrpm, unsigned msr,
389 int read, int write)
6aa8b732
AK		 390{
391 int i;
392
393 for (i = 0; i < NUM_MSR_MAPS; i++) {
394 if (msr >= msrpm_ranges[i] &&
395 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
396 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
397 msrpm_ranges[i]) * 2;
398
399 u32 *base = msrpm + (msr_offset / 32);
400 u32 msr_shift = msr_offset % 32;
401 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
402 *base = (*base & ~(0x3 << msr_shift)) |
403 (mask << msr_shift);
bfc733a7 404 return;
6aa8b732
AK		 405 }
406 }
bfc733a7 407 BUG();
6aa8b732
AK		 408}
409
f65c229c
JR		 410static void svm_vcpu_init_msrpm(u32 *msrpm)
411{
412 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
413
414#ifdef CONFIG_X86_64
415 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
416 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
417 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
418 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
419 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
420 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
421#endif
422 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
423 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 424}
425
24e09cbf
JR		 426static void svm_enable_lbrv(struct vcpu_svm *svm)
427{
428 u32 *msrpm = svm->msrpm;
429
430 svm->vmcb->control.lbr_ctl = 1;
431 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
432 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
433 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
434 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
435}
436
437static void svm_disable_lbrv(struct vcpu_svm *svm)
438{
439 u32 *msrpm = svm->msrpm;
440
441 svm->vmcb->control.lbr_ctl = 0;
442 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
443 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
444 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
445 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
446}
447
6aa8b732
AK		 448static __init int svm_hardware_setup(void)
449{
450 int cpu;
451 struct page *iopm_pages;
f65c229c 452 void *iopm_va;
6aa8b732
AK		 453 int r;
454
6aa8b732
AK		 455 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
456
457 if (!iopm_pages)
458 return -ENOMEM;
c8681339
AL		 459
460 iopm_va = page_address(iopm_pages);
461 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 462 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
463
50a37eb4
JR		 464 if (boot_cpu_has(X86_FEATURE_NX))
465 kvm_enable_efer_bits(EFER_NX);
466
1b2fd70c
AG		 467 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
468 kvm_enable_efer_bits(EFER_FFXSR);
469
236de055
AG		 470 if (nested) {
471 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
472 kvm_enable_efer_bits(EFER_SVME);
473 }
474
6aa8b732
AK		 475 for_each_online_cpu(cpu) {
476 r = svm_cpu_init(cpu);
477 if (r)
f65c229c 478 goto err;
6aa8b732 479 }
33bd6a0b
JR		 480
481 svm_features = cpuid_edx(SVM_CPUID_FUNC);
482
e3da3acd
JR		 483 if (!svm_has(SVM_FEATURE_NPT))
484 npt_enabled = false;
485
6c7dac72
JR		 486 if (npt_enabled && !npt) {
487 printk(KERN_INFO "kvm: Nested Paging disabled\n");
488 npt_enabled = false;
489 }
490
18552672 491 if (npt_enabled) {
e3da3acd 492 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 493 kvm_enable_tdp();
5f4cb662
JR		 494 } else
495 kvm_disable_tdp();
e3da3acd 496
6aa8b732
AK		 497 return 0;
498
f65c229c 499err:
6aa8b732
AK		 500 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
501 iopm_base = 0;
502 return r;
503}
504
505static __exit void svm_hardware_unsetup(void)
506{
0da1db75
JR		 507 int cpu;
508
509 for_each_online_cpu(cpu)
510 svm_cpu_uninit(cpu);
511
6aa8b732 512 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 513 iopm_base = 0;
6aa8b732
AK		 514}
515
516static void init_seg(struct vmcb_seg *seg)
517{
518 seg->selector = 0;
519 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
520 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
521 seg->limit = 0xffff;
522 seg->base = 0;
523}
524
525static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
526{
527 seg->selector = 0;
528 seg->attrib = SVM_SELECTOR_P_MASK | type;
529 seg->limit = 0xffff;
530 seg->base = 0;
531}
532
e6101a96 533static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 534{
e6101a96
JR		 535 struct vmcb_control_area *control = &svm->vmcb->control;
536 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 537
538 control->intercept_cr_read = INTERCEPT_CR0_MASK |
539 INTERCEPT_CR3_MASK |
649d6864 540 INTERCEPT_CR4_MASK;
6aa8b732
AK		 541
542 control->intercept_cr_write = INTERCEPT_CR0_MASK |
543 INTERCEPT_CR3_MASK |
80a8119c
AK		 544 INTERCEPT_CR4_MASK |
545 INTERCEPT_CR8_MASK;
6aa8b732
AK		 546
547 control->intercept_dr_read = INTERCEPT_DR0_MASK |
548 INTERCEPT_DR1_MASK |
549 INTERCEPT_DR2_MASK |
550 INTERCEPT_DR3_MASK;
551
552 control->intercept_dr_write = INTERCEPT_DR0_MASK |
553 INTERCEPT_DR1_MASK |
554 INTERCEPT_DR2_MASK |
555 INTERCEPT_DR3_MASK |
556 INTERCEPT_DR5_MASK |
557 INTERCEPT_DR7_MASK;
558
7aa81cc0 559 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 560 (1 << UD_VECTOR) |
561 (1 << MC_VECTOR);
6aa8b732
AK		 562
563
564 control->intercept = (1ULL << INTERCEPT_INTR) |
565 (1ULL << INTERCEPT_NMI) |
0152527b 566 (1ULL << INTERCEPT_SMI) |
6aa8b732 567 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 568 (1ULL << INTERCEPT_INVD) |
6aa8b732 569 (1ULL << INTERCEPT_HLT) |
a7052897 570 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 571 (1ULL << INTERCEPT_INVLPGA) |
572 (1ULL << INTERCEPT_IOIO_PROT) |
573 (1ULL << INTERCEPT_MSR_PROT) |
574 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 575 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 576 (1ULL << INTERCEPT_VMRUN) |
577 (1ULL << INTERCEPT_VMMCALL) |
578 (1ULL << INTERCEPT_VMLOAD) |
579 (1ULL << INTERCEPT_VMSAVE) |
580 (1ULL << INTERCEPT_STGI) |
581 (1ULL << INTERCEPT_CLGI) |
916ce236 582 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 583 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 584 (1ULL << INTERCEPT_MONITOR) |
585 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 586
587 control->iopm_base_pa = iopm_base;
f65c229c 588 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 589 control->tsc_offset = 0;
6aa8b732
AK		 590 control->int_ctl = V_INTR_MASKING_MASK;
591
592 init_seg(&save->es);
593 init_seg(&save->ss);
594 init_seg(&save->ds);
595 init_seg(&save->fs);
596 init_seg(&save->gs);
597
598 save->cs.selector = 0xf000;
599 /* Executable/Readable Code Segment */
600 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
601 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
602 save->cs.limit = 0xffff;
d92899a0
AK		 603 /*
604 * cs.base should really be 0xffff0000, but vmx can't handle that, so
605 * be consistent with it.
606 *
607 * Replace when we have real mode working for vmx.
608 */
609 save->cs.base = 0xf0000;
6aa8b732
AK		 610
611 save->gdtr.limit = 0xffff;
612 save->idtr.limit = 0xffff;
613
614 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
615 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
616
9962d032 617 save->efer = EFER_SVME;
d77c26fc 618 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 619 save->dr7 = 0x400;
620 save->rflags = 2;
621 save->rip = 0x0000fff0;
5fdbf976 622 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 623
624 /*
625 * cr0 val on cpu init should be 0x60000010, we enable cpu
626 * cache by default. the orderly way is to enable cache in bios.
627 */
707d92fa 628 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 629 save->cr4 = X86_CR4_PAE;
6aa8b732 630 /* rdx = ?? */
709ddebf
JR		 631
632 if (npt_enabled) {
633 /* Setup VMCB for Nested Paging */
634 control->nested_ctl = 1;
a7052897
MT		 635 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
636 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 637 control->intercept_exceptions &= ~(1 << PF_VECTOR);
638 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
639 INTERCEPT_CR3_MASK);
640 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
641 INTERCEPT_CR3_MASK);
642 save->g_pat = 0x0007040600070406ULL;
643 /* enable caching because the QEMU Bios doesn't enable it */
644 save->cr0 = X86_CR0_ET;
645 save->cr3 = 0;
646 save->cr4 = 0;
647 }
a79d2f18 648 force_new_asid(&svm->vcpu);
1371d904 649
e6aa9abd 650 svm->nested.vmcb = 0;
2af9194d
JR		 651 svm->vcpu.arch.hflags = 0;
652
653 enable_gif(svm);
6aa8b732
AK		 654}
655
e00c8cf2 656static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 657{
658 struct vcpu_svm *svm = to_svm(vcpu);
659
e6101a96 660 init_vmcb(svm);
70433389 661
c5af89b6 662 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 663 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 664 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
665 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 666 }
5fdbf976
MT		 667 vcpu->arch.regs_avail = ~0;
668 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 669
670 return 0;
04d2cc77
AK		 671}
672
fb3f0f51 673static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 674{
a2fa3e9f 675 struct vcpu_svm *svm;
6aa8b732 676 struct page *page;
f65c229c 677 struct page *msrpm_pages;
b286d5d8 678 struct page *hsave_page;
3d6368ef 679 struct page *nested_msrpm_pages;
fb3f0f51 680 int err;
6aa8b732 681
c16f862d 682 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 683 if (!svm) {
684 err = -ENOMEM;
685 goto out;
686 }
687
688 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
689 if (err)
690 goto free_svm;
691
6aa8b732 692 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 693 if (!page) {
694 err = -ENOMEM;
695 goto uninit;
696 }
6aa8b732 697
f65c229c
JR		 698 err = -ENOMEM;
699 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
700 if (!msrpm_pages)
701 goto uninit;
3d6368ef
AG		 702
703 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
704 if (!nested_msrpm_pages)
705 goto uninit;
706
f65c229c
JR		 707 svm->msrpm = page_address(msrpm_pages);
708 svm_vcpu_init_msrpm(svm->msrpm);
709
b286d5d8
AG		 710 hsave_page = alloc_page(GFP_KERNEL);
711 if (!hsave_page)
712 goto uninit;
e6aa9abd 713 svm->nested.hsave = page_address(hsave_page);
b286d5d8 714
e6aa9abd 715 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 716
a2fa3e9f
GH		 717 svm->vmcb = page_address(page);
718 clear_page(svm->vmcb);
719 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
720 svm->asid_generation = 0;
e6101a96 721 init_vmcb(svm);
a2fa3e9f 722
fb3f0f51
RR		 723 fx_init(&svm->vcpu);
724 svm->vcpu.fpu_active = 1;
ad312c7c 725 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 726 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 727 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 728
fb3f0f51 729 return &svm->vcpu;
36241b8c 730
fb3f0f51
RR		 731uninit:
732 kvm_vcpu_uninit(&svm->vcpu);
733free_svm:
a4770347 734 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 735out:
736 return ERR_PTR(err);
6aa8b732
AK		 737}
738
739static void svm_free_vcpu(struct kvm_vcpu *vcpu)
740{
a2fa3e9f
GH		 741 struct vcpu_svm *svm = to_svm(vcpu);
742
fb3f0f51 743 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 744 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 745 __free_page(virt_to_page(svm->nested.hsave));
746 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 747 kvm_vcpu_uninit(vcpu);
a4770347 748 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 749}
750
15ad7146 751static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 752{
a2fa3e9f 753 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 754 int i;
0cc5064d 755
0cc5064d
AK		 756 if (unlikely(cpu != vcpu->cpu)) {
757 u64 tsc_this, delta;
758
759 /*
760 * Make sure that the guest sees a monotonically
761 * increasing TSC.
762 */
763 rdtscll(tsc_this);
ad312c7c 764 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 765 svm->vmcb->control.tsc_offset += delta;
0cc5064d 766 vcpu->cpu = cpu;
2f599714 767 kvm_migrate_timers(vcpu);
4b656b12 768 svm->asid_generation = 0;
0cc5064d 769 }
94dfbdb3
AL		 770
771 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 772 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 773}
774
775static void svm_vcpu_put(struct kvm_vcpu *vcpu)
776{
a2fa3e9f 777 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 778 int i;
779
e1beb1d3 780 ++vcpu->stat.host_state_reload;
94dfbdb3 781 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 782 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 783
ad312c7c 784 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 785}
786
6aa8b732
AK		 787static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
788{
a2fa3e9f 789 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 790}
791
792static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
793{
a2fa3e9f 794 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 795}
796
6de4f3ad
AK		 797static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
798{
799 switch (reg) {
800 case VCPU_EXREG_PDPTR:
801 BUG_ON(!npt_enabled);
802 load_pdptrs(vcpu, vcpu->arch.cr3);
803 break;
804 default:
805 BUG();
806 }
807}
808
f0b85051
AG		 809static void svm_set_vintr(struct vcpu_svm *svm)
810{
811 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
812}
813
814static void svm_clear_vintr(struct vcpu_svm *svm)
815{
816 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
817}
818
6aa8b732
AK		 819static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
820{
a2fa3e9f 821 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 822
823 switch (seg) {
824 case VCPU_SREG_CS: return &save->cs;
825 case VCPU_SREG_DS: return &save->ds;
826 case VCPU_SREG_ES: return &save->es;
827 case VCPU_SREG_FS: return &save->fs;
828 case VCPU_SREG_GS: return &save->gs;
829 case VCPU_SREG_SS: return &save->ss;
830 case VCPU_SREG_TR: return &save->tr;
831 case VCPU_SREG_LDTR: return &save->ldtr;
832 }
833 BUG();
8b6d44c7 834 return NULL;
6aa8b732
AK		 835}
836
837static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
838{
839 struct vmcb_seg *s = svm_seg(vcpu, seg);
840
841 return s->base;
842}
843
844static void svm_get_segment(struct kvm_vcpu *vcpu,
845 struct kvm_segment *var, int seg)
846{
847 struct vmcb_seg *s = svm_seg(vcpu, seg);
848
849 var->base = s->base;
850 var->limit = s->limit;
851 var->selector = s->selector;
852 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
853 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
854 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
855 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
856 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
857 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
858 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
859 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 860
19bca6ab
AP		 861 /* AMD's VMCB does not have an explicit unusable field, so emulate it
862 * for cross vendor migration purposes by "not present"
863 */
864 var->unusable = !var->present || (var->type == 0);
865
1fbdc7a5
AP		 866 switch (seg) {
867 case VCPU_SREG_CS:
868 /*
869 * SVM always stores 0 for the 'G' bit in the CS selector in
870 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
871 * Intel's VMENTRY has a check on the 'G' bit.
872 */
25022acc 873 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 874 break;
875 case VCPU_SREG_TR:
876 /*
877 * Work around a bug where the busy flag in the tr selector
878 * isn't exposed
879 */
c0d09828 880 var->type |= 0x2;
1fbdc7a5
AP		 881 break;
882 case VCPU_SREG_DS:
883 case VCPU_SREG_ES:
884 case VCPU_SREG_FS:
885 case VCPU_SREG_GS:
886 /*
887 * The accessed bit must always be set in the segment
888 * descriptor cache, although it can be cleared in the
889 * descriptor, the cached bit always remains at 1. Since
890 * Intel has a check on this, set it here to support
891 * cross-vendor migration.
892 */
893 if (!var->unusable)
894 var->type |= 0x1;
895 break;
b586eb02
AP		 896 case VCPU_SREG_SS:
897 /* On AMD CPUs sometimes the DB bit in the segment
898 * descriptor is left as 1, although the whole segment has
899 * been made unusable. Clear it here to pass an Intel VMX
900 * entry check when cross vendor migrating.
901 */
902 if (var->unusable)
903 var->db = 0;
904 break;
1fbdc7a5 905 }
6aa8b732
AK		 906}
907
2e4d2653
IE		 908static int svm_get_cpl(struct kvm_vcpu *vcpu)
909{
910 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
911
912 return save->cpl;
913}
914
6aa8b732
AK		 915static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
916{
a2fa3e9f
GH		 917 struct vcpu_svm *svm = to_svm(vcpu);
918
919 dt->limit = svm->vmcb->save.idtr.limit;
920 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 921}
922
923static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
924{
a2fa3e9f
GH		 925 struct vcpu_svm *svm = to_svm(vcpu);
926
927 svm->vmcb->save.idtr.limit = dt->limit;
928 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 929}
930
931static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
932{
a2fa3e9f
GH		 933 struct vcpu_svm *svm = to_svm(vcpu);
934
935 dt->limit = svm->vmcb->save.gdtr.limit;
936 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 937}
938
939static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
940{
a2fa3e9f
GH		 941 struct vcpu_svm *svm = to_svm(vcpu);
942
943 svm->vmcb->save.gdtr.limit = dt->limit;
944 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 945}
946
25c4c276 947static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 948{
949}
950
6aa8b732
AK		 951static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
952{
a2fa3e9f
GH		 953 struct vcpu_svm *svm = to_svm(vcpu);
954
05b3e0c2 955#ifdef CONFIG_X86_64
ad312c7c 956 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 957 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 958 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 959 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 960 }
961
d77c26fc 962 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 963 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 964 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 965 }
966 }
967#endif
709ddebf
JR		 968 if (npt_enabled)
969 goto set;
970
ad312c7c 971 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 972 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 973 vcpu->fpu_active = 1;
974 }
975
ad312c7c 976 vcpu->arch.cr0 = cr0;
707d92fa 977 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 978 if (!vcpu->fpu_active) {
979 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 980 cr0 |= X86_CR0_TS;
6b390b63 981 }
709ddebf
JR		 982set:
983 /*
984 * re-enable caching here because the QEMU bios
985 * does not do it - this results in some delay at
986 * reboot
987 */
988 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 989 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 990}
991
992static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
993{
6394b649 994 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 995 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
996
997 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
998 force_new_asid(vcpu);
6394b649 999
ec077263
JR		 1000 vcpu->arch.cr4 = cr4;
1001 if (!npt_enabled)
1002 cr4 |= X86_CR4_PAE;
6394b649 1003 cr4 |= host_cr4_mce;
ec077263 1004 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1005}
1006
1007static void svm_set_segment(struct kvm_vcpu *vcpu,
1008 struct kvm_segment *var, int seg)
1009{
a2fa3e9f 1010 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1011 struct vmcb_seg *s = svm_seg(vcpu, seg);
1012
1013 s->base = var->base;
1014 s->limit = var->limit;
1015 s->selector = var->selector;
1016 if (var->unusable)
1017 s->attrib = 0;
1018 else {
1019 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1020 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1021 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1022 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1023 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1024 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1025 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1026 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1027 }
1028 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1029 svm->vmcb->save.cpl
1030 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1031 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1032
1033}
1034
44c11430 1035static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1036{
d0bfb940
JK		 1037 struct vcpu_svm *svm = to_svm(vcpu);
1038
d0bfb940
JK		 1039 svm->vmcb->control.intercept_exceptions &=
1040 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1041
1042 if (vcpu->arch.singlestep)
1043 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1044
d0bfb940
JK		 1045 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1046 if (vcpu->guest_debug &
1047 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1048 svm->vmcb->control.intercept_exceptions |=
1049 1 << DB_VECTOR;
1050 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1051 svm->vmcb->control.intercept_exceptions |=
1052 1 << BP_VECTOR;
1053 } else
1054 vcpu->guest_debug = 0;
44c11430
GN		 1055}
1056
1057static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1058{
1059 int old_debug = vcpu->guest_debug;
1060 struct vcpu_svm *svm = to_svm(vcpu);
1061
1062 vcpu->guest_debug = dbg->control;
1063
1064 update_db_intercept(vcpu);
d0bfb940 1065
ae675ef0
JK		 1066 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1067 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1068 else
1069 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1070
d0bfb940
JK		 1071 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1072 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1073 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1074 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1075
1076 return 0;
6aa8b732
AK		 1077}
1078
1079static void load_host_msrs(struct kvm_vcpu *vcpu)
1080{
94dfbdb3 1081#ifdef CONFIG_X86_64
a2fa3e9f 1082 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1083#endif
6aa8b732
AK		 1084}
1085
1086static void save_host_msrs(struct kvm_vcpu *vcpu)
1087{
94dfbdb3 1088#ifdef CONFIG_X86_64
a2fa3e9f 1089 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1090#endif
6aa8b732
AK		 1091}
1092
e756fc62 1093static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1094{
1095 if (svm_data->next_asid > svm_data->max_asid) {
1096 ++svm_data->asid_generation;
1097 svm_data->next_asid = 1;
a2fa3e9f 1098 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1099 }
1100
a2fa3e9f
GH		 1101 svm->asid_generation = svm_data->asid_generation;
1102 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1103}
1104
6aa8b732
AK		 1105static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1106{
42dbaa5a
JK		 1107 struct vcpu_svm *svm = to_svm(vcpu);
1108 unsigned long val;
1109
1110 switch (dr) {
1111 case 0 ... 3:
1112 val = vcpu->arch.db[dr];
1113 break;
1114 case 6:
1115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116 val = vcpu->arch.dr6;
1117 else
1118 val = svm->vmcb->save.dr6;
1119 break;
1120 case 7:
1121 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122 val = vcpu->arch.dr7;
1123 else
1124 val = svm->vmcb->save.dr7;
1125 break;
1126 default:
1127 val = 0;
1128 }
1129
af9ca2d7 1130 return val;
6aa8b732
AK		 1131}
1132
1133static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1134 int *exception)
1135{
a2fa3e9f
GH		 1136 struct vcpu_svm *svm = to_svm(vcpu);
1137
42dbaa5a 1138 *exception = 0;
6aa8b732
AK		 1139
1140 switch (dr) {
1141 case 0 ... 3:
42dbaa5a
JK		 1142 vcpu->arch.db[dr] = value;
1143 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1144 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1145 return;
1146 case 4 ... 5:
42dbaa5a 1147 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1148 *exception = UD_VECTOR;
42dbaa5a
JK		 1149 return;
1150 case 6:
1151 if (value & 0xffffffff00000000ULL) {
1152 *exception = GP_VECTOR;
6aa8b732
AK		 1153 return;
1154 }
42dbaa5a
JK		 1155 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1156 return;
1157 case 7:
1158 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1159 *exception = GP_VECTOR;
1160 return;
1161 }
42dbaa5a
JK		 1162 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1163 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1164 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1165 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1166 }
6aa8b732 1167 return;
6aa8b732 1168 default:
42dbaa5a 1169 /* FIXME: Possible case? */
6aa8b732 1170 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1171 __func__, dr);
6aa8b732
AK		 1172 *exception = UD_VECTOR;
1173 return;
1174 }
1175}
1176
e756fc62 1177static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1178{
6aa8b732
AK		 1179 u64 fault_address;
1180 u32 error_code;
6aa8b732 1181
a2fa3e9f
GH		 1182 fault_address = svm->vmcb->control.exit_info_2;
1183 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1184
229456fc 1185 trace_kvm_page_fault(fault_address, error_code);
44874f84
JR		 1186 /*
1187 * FIXME: Tis shouldn't be necessary here, but there is a flush
1188 * missing in the MMU code. Until we find this bug, flush the
1189 * complete TLB here on an NPF
1190 */
1191 if (npt_enabled)
1192 svm_flush_tlb(&svm->vcpu);
9222be18 1193 else {
3298b75c 1194 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1195 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1196 }
3067714c 1197 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1198}
1199
d0bfb940
JK		 1200static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1201{
1202 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1203 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1204 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1205 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1206 return 1;
1207 }
44c11430
GN		 1208
1209 if (svm->vcpu.arch.singlestep) {
1210 svm->vcpu.arch.singlestep = false;
1211 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1212 svm->vmcb->save.rflags &=
1213 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1214 update_db_intercept(&svm->vcpu);
1215 }
1216
1217 if (svm->vcpu.guest_debug &
1218 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1219 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1220 kvm_run->debug.arch.pc =
1221 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1222 kvm_run->debug.arch.exception = DB_VECTOR;
1223 return 0;
1224 }
1225
1226 return 1;
d0bfb940
JK		 1227}
1228
1229static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230{
1231 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1232 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1233 kvm_run->debug.arch.exception = BP_VECTOR;
1234 return 0;
1235}
1236
7aa81cc0
AL		 1237static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1238{
1239 int er;
1240
571008da 1241 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1242 if (er != EMULATE_DONE)
7ee5d940 1243 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1244 return 1;
1245}
1246
e756fc62 1247static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1248{
a2fa3e9f 1249 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1250 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1251 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1252 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1253
1254 return 1;
7807fa6c
AL		 1255}
1256
53371b50
JR		 1257static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1258{
1259 /*
1260 * On an #MC intercept the MCE handler is not called automatically in
1261 * the host. So do it by hand here.
1262 */
1263 asm volatile (
1264 "int $0x12\n");
1265 /* not sure if we ever come back to this point */
1266
1267 return 1;
1268}
1269
e756fc62 1270static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1271{
1272 /*
1273 * VMCB is undefined after a SHUTDOWN intercept
1274 * so reinitialize it.
1275 */
a2fa3e9f 1276 clear_page(svm->vmcb);
e6101a96 1277 init_vmcb(svm);
46fe4ddd
JR		 1278
1279 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1280 return 0;
1281}
1282
e756fc62 1283static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1284{
d77c26fc 1285 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1286 int size, in, string;
039576c0 1287 unsigned port;
6aa8b732 1288
e756fc62 1289 ++svm->vcpu.stat.io_exits;
6aa8b732 1290
a2fa3e9f 1291 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1292
e70669ab
LV		 1293 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1294
1295 if (string) {
3427318f
LV		 1296 if (emulate_instruction(&svm->vcpu,
1297 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1298 return 0;
1299 return 1;
1300 }
1301
039576c0
AK		 1302 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1303 port = io_info >> 16;
1304 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1305
e93f36bc 1306 skip_emulated_instruction(&svm->vcpu);
3090dd73 1307 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1308}
1309
c47f098d
JR		 1310static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1311{
1312 return 1;
1313}
1314
a0698055
JR		 1315static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1316{
1317 ++svm->vcpu.stat.irq_exits;
1318 return 1;
1319}
1320
e756fc62 1321static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1322{
1323 return 1;
1324}
1325
e756fc62 1326static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1327{
5fdbf976 1328 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1329 skip_emulated_instruction(&svm->vcpu);
1330 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1331}
1332
e756fc62 1333static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1334{
5fdbf976 1335 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1336 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1337 kvm_emulate_hypercall(&svm->vcpu);
1338 return 1;
02e235bc
AK		 1339}
1340
c0725420
AG		 1341static int nested_svm_check_permissions(struct vcpu_svm *svm)
1342{
1343 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1344 || !is_paging(&svm->vcpu)) {
1345 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1346 return 1;
1347 }
1348
1349 if (svm->vmcb->save.cpl) {
1350 kvm_inject_gp(&svm->vcpu, 0);
1351 return 1;
1352 }
1353
1354 return 0;
1355}
1356
cf74a78b
AG		 1357static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1358 bool has_error_code, u32 error_code)
1359{
0295ad7d
JR		 1360 if (!is_nested(svm))
1361 return 0;
cf74a78b 1362
0295ad7d
JR		 1363 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1364 svm->vmcb->control.exit_code_hi = 0;
1365 svm->vmcb->control.exit_info_1 = error_code;
1366 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1367
1368 return nested_svm_exit_handled(svm, false);
cf74a78b
AG		 1369}
1370
1371static inline int nested_svm_intr(struct vcpu_svm *svm)
1372{
1373 if (is_nested(svm)) {
1374 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1375 return 0;
1376
1377 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1378 return 0;
1379
1380 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1381
1382 if (nested_svm_exit_handled(svm, false)) {
1383 nsvm_printk("VMexit -> INTR\n");
cf74a78b
AG		 1384 return 1;
1385 }
1386 }
1387
1388 return 0;
1389}
1390
34f80cfa
JR		 1391static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1392{
1393 struct page *page;
1394
1395 down_read(&current->mm->mmap_sem);
1396 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1397 up_read(&current->mm->mmap_sem);
1398
1399 if (is_error_page(page))
1400 goto error;
1401
1402 return kmap_atomic(page, idx);
1403
1404error:
1405 kvm_release_page_clean(page);
1406 kvm_inject_gp(&svm->vcpu, 0);
1407
1408 return NULL;
1409}
1410
1411static void nested_svm_unmap(void *addr, enum km_type idx)
1412{
1413 struct page *page;
1414
1415 if (!addr)
1416 return;
1417
1418 page = kmap_atomic_to_page(addr);
1419
1420 kunmap_atomic(addr, idx);
1421 kvm_release_page_dirty(page);
1422}
1423
c0725420
AG		 1424static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1425{
1426 struct page *page;
1427
1428 down_read(&current->mm->mmap_sem);
1429 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1430 up_read(&current->mm->mmap_sem);
1431
1432 if (is_error_page(page)) {
1433 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1434 __func__, gpa);
1435 kvm_release_page_clean(page);
1436 kvm_inject_gp(&svm->vcpu, 0);
1437 return NULL;
1438 }
1439 return page;
1440}
1441
1442static int nested_svm_do(struct vcpu_svm *svm,
1443 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1444 int (*handler)(struct vcpu_svm *svm,
1445 void *arg1,
1446 void *arg2,
1447 void *opaque))
1448{
1449 struct page *arg1_page;
1450 struct page *arg2_page = NULL;
1451 void *arg1;
1452 void *arg2 = NULL;
1453 int retval;
1454
1455 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1456 if(arg1_page == NULL)
1457 return 1;
1458
1459 if (arg2_gpa) {
1460 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1461 if(arg2_page == NULL) {
1462 kvm_release_page_clean(arg1_page);
1463 return 1;
1464 }
1465 }
1466
1467 arg1 = kmap_atomic(arg1_page, KM_USER0);
1468 if (arg2_gpa)
1469 arg2 = kmap_atomic(arg2_page, KM_USER1);
1470
1471 retval = handler(svm, arg1, arg2, opaque);
1472
1473 kunmap_atomic(arg1, KM_USER0);
1474 if (arg2_gpa)
1475 kunmap_atomic(arg2, KM_USER1);
1476
1477 kvm_release_page_dirty(arg1_page);
1478 if (arg2_gpa)
1479 kvm_release_page_dirty(arg2_page);
1480
1481 return retval;
1482}
1483
3d62d9aa 1484static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1485{
4c2161ae 1486 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1487 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1488 bool ret = false;
1489 u32 t0, t1;
1490 u8 *msrpm;
4c2161ae 1491
3d62d9aa
JR		 1492 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1493 return false;
1494
1495 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1496
1497 if (!msrpm)
1498 goto out;
4c2161ae
JR		 1499
1500 switch (msr) {
1501 case 0 ... 0x1fff:
1502 t0 = (msr * 2) % 8;
1503 t1 = msr / 8;
1504 break;
1505 case 0xc0000000 ... 0xc0001fff:
1506 t0 = (8192 + msr - 0xc0000000) * 2;
1507 t1 = (t0 / 8);
1508 t0 %= 8;
1509 break;
1510 case 0xc0010000 ... 0xc0011fff:
1511 t0 = (16384 + msr - 0xc0010000) * 2;
1512 t1 = (t0 / 8);
1513 t0 %= 8;
1514 break;
1515 default:
3d62d9aa
JR		 1516 ret = true;
1517 goto out;
4c2161ae 1518 }
4c2161ae 1519
3d62d9aa
JR		 1520 ret = msrpm[t1] & ((1 << param) << t0);
1521
1522out:
1523 nested_svm_unmap(msrpm, KM_USER0);
1524
1525 return ret;
4c2161ae
JR		 1526}
1527
1528static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
cf74a78b 1529{
cf74a78b 1530 u32 exit_code = svm->vmcb->control.exit_code;
9c4e40b9 1531 bool vmexit = false;
4c2161ae
JR		 1532
1533 if (kvm_override) {
cf74a78b
AG		 1534 switch (exit_code) {
1535 case SVM_EXIT_INTR:
1536 case SVM_EXIT_NMI:
1537 return 0;
1538 /* For now we are always handling NPFs when using them */
1539 case SVM_EXIT_NPF:
1540 if (npt_enabled)
1541 return 0;
1542 break;
1543 /* When we're shadowing, trap PFs */
1544 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1545 if (!npt_enabled)
1546 return 0;
1547 break;
1548 default:
1549 break;
1550 }
1551 }
1552
1553 switch (exit_code) {
9c4e40b9 1554 case SVM_EXIT_MSR:
3d62d9aa 1555 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1556 break;
cf74a78b
AG		 1557 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1558 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1559 if (svm->nested.intercept_cr_read & cr_bits)
9c4e40b9 1560 vmexit = true;
cf74a78b
AG		 1561 break;
1562 }
1563 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1564 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1565 if (svm->nested.intercept_cr_write & cr_bits)
9c4e40b9 1566 vmexit = true;
cf74a78b
AG		 1567 break;
1568 }
1569 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1570 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1571 if (svm->nested.intercept_dr_read & dr_bits)
9c4e40b9 1572 vmexit = true;
cf74a78b
AG		 1573 break;
1574 }
1575 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1576 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1577 if (svm->nested.intercept_dr_write & dr_bits)
9c4e40b9 1578 vmexit = true;
cf74a78b
AG		 1579 break;
1580 }
1581 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1582 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1583 if (svm->nested.intercept_exceptions & excp_bits)
9c4e40b9 1584 vmexit = true;
cf74a78b
AG		 1585 break;
1586 }
1587 default: {
1588 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1589 nsvm_printk("exit code: 0x%x\n", exit_code);
aad42c64 1590 if (svm->nested.intercept & exit_bits)
9c4e40b9 1591 vmexit = true;
cf74a78b
AG		 1592 }
1593 }
1594
9c4e40b9
JR		 1595 if (vmexit) {
1596 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1597 nested_svm_vmexit(svm);
1598 }
1599
1600 return vmexit;
cf74a78b
AG		 1601}
1602
0460a979
JR		 1603static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1604{
1605 struct vmcb_control_area *dst = &dst_vmcb->control;
1606 struct vmcb_control_area *from = &from_vmcb->control;
1607
1608 dst->intercept_cr_read = from->intercept_cr_read;
1609 dst->intercept_cr_write = from->intercept_cr_write;
1610 dst->intercept_dr_read = from->intercept_dr_read;
1611 dst->intercept_dr_write = from->intercept_dr_write;
1612 dst->intercept_exceptions = from->intercept_exceptions;
1613 dst->intercept = from->intercept;
1614 dst->iopm_base_pa = from->iopm_base_pa;
1615 dst->msrpm_base_pa = from->msrpm_base_pa;
1616 dst->tsc_offset = from->tsc_offset;
1617 dst->asid = from->asid;
1618 dst->tlb_ctl = from->tlb_ctl;
1619 dst->int_ctl = from->int_ctl;
1620 dst->int_vector = from->int_vector;
1621 dst->int_state = from->int_state;
1622 dst->exit_code = from->exit_code;
1623 dst->exit_code_hi = from->exit_code_hi;
1624 dst->exit_info_1 = from->exit_info_1;
1625 dst->exit_info_2 = from->exit_info_2;
1626 dst->exit_int_info = from->exit_int_info;
1627 dst->exit_int_info_err = from->exit_int_info_err;
1628 dst->nested_ctl = from->nested_ctl;
1629 dst->event_inj = from->event_inj;
1630 dst->event_inj_err = from->event_inj_err;
1631 dst->nested_cr3 = from->nested_cr3;
1632 dst->lbr_ctl = from->lbr_ctl;
1633}
1634
34f80cfa 1635static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1636{
34f80cfa 1637 struct vmcb *nested_vmcb;
e6aa9abd 1638 struct vmcb *hsave = svm->nested.hsave;
33740e40 1639 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1640
34f80cfa
JR		 1641 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1642 if (!nested_vmcb)
1643 return 1;
1644
cf74a78b 1645 /* Give the current vmcb to the guest */
33740e40
JR		 1646 disable_gif(svm);
1647
1648 nested_vmcb->save.es = vmcb->save.es;
1649 nested_vmcb->save.cs = vmcb->save.cs;
1650 nested_vmcb->save.ss = vmcb->save.ss;
1651 nested_vmcb->save.ds = vmcb->save.ds;
1652 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1653 nested_vmcb->save.idtr = vmcb->save.idtr;
1654 if (npt_enabled)
1655 nested_vmcb->save.cr3 = vmcb->save.cr3;
1656 nested_vmcb->save.cr2 = vmcb->save.cr2;
1657 nested_vmcb->save.rflags = vmcb->save.rflags;
1658 nested_vmcb->save.rip = vmcb->save.rip;
1659 nested_vmcb->save.rsp = vmcb->save.rsp;
1660 nested_vmcb->save.rax = vmcb->save.rax;
1661 nested_vmcb->save.dr7 = vmcb->save.dr7;
1662 nested_vmcb->save.dr6 = vmcb->save.dr6;
1663 nested_vmcb->save.cpl = vmcb->save.cpl;
1664
1665 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1666 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1667 nested_vmcb->control.int_state = vmcb->control.int_state;
1668 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1669 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1670 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1671 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1672 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1673 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1674 nested_vmcb->control.tlb_ctl = 0;
1675 nested_vmcb->control.event_inj = 0;
1676 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1677
1678 /* We always set V_INTR_MASKING and remember the old value in hflags */
1679 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1680 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1681
cf74a78b 1682 /* Restore the original control entries */
0460a979 1683 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1684
1685 /* Kill any pending exceptions */
1686 if (svm->vcpu.arch.exception.pending == true)
1687 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1688
219b65dc
AG		 1689 kvm_clear_exception_queue(&svm->vcpu);
1690 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1691
1692 /* Restore selected save entries */
1693 svm->vmcb->save.es = hsave->save.es;
1694 svm->vmcb->save.cs = hsave->save.cs;
1695 svm->vmcb->save.ss = hsave->save.ss;
1696 svm->vmcb->save.ds = hsave->save.ds;
1697 svm->vmcb->save.gdtr = hsave->save.gdtr;
1698 svm->vmcb->save.idtr = hsave->save.idtr;
1699 svm->vmcb->save.rflags = hsave->save.rflags;
1700 svm_set_efer(&svm->vcpu, hsave->save.efer);
1701 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1702 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1703 if (npt_enabled) {
1704 svm->vmcb->save.cr3 = hsave->save.cr3;
1705 svm->vcpu.arch.cr3 = hsave->save.cr3;
1706 } else {
1707 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1708 }
1709 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1710 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1711 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1712 svm->vmcb->save.dr7 = 0;
1713 svm->vmcb->save.cpl = 0;
1714 svm->vmcb->control.exit_int_info = 0;
1715
cf74a78b 1716 /* Exit nested SVM mode */
e6aa9abd 1717 svm->nested.vmcb = 0;
cf74a78b 1718
34f80cfa 1719 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1720
1721 kvm_mmu_reset_context(&svm->vcpu);
1722 kvm_mmu_load(&svm->vcpu);
1723
1724 return 0;
1725}
3d6368ef
AG		 1726
1727static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1728 void *arg2, void *opaque)
1729{
1730 int i;
1731 u32 *nested_msrpm = (u32*)arg1;
1732 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd
JR		 1733 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1734 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef
AG		 1735
1736 return 0;
1737}
1738
1739static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1740 void *arg2, void *opaque)
1741{
1742 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
e6aa9abd 1743 struct vmcb *hsave = svm->nested.hsave;
defbba56 1744 struct vmcb *vmcb = svm->vmcb;
3d6368ef
AG		 1745
1746 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1747 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef
AG		 1748
1749 /* Clear internal status */
219b65dc
AG		 1750 kvm_clear_exception_queue(&svm->vcpu);
1751 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1752
1753 /* Save the old vmcb, so we don't need to pick what we save, but
1754 can restore everything when a VMEXIT occurs */
defbba56
JR		 1755 hsave->save.es = vmcb->save.es;
1756 hsave->save.cs = vmcb->save.cs;
1757 hsave->save.ss = vmcb->save.ss;
1758 hsave->save.ds = vmcb->save.ds;
1759 hsave->save.gdtr = vmcb->save.gdtr;
1760 hsave->save.idtr = vmcb->save.idtr;
1761 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1762 hsave->save.cr0 = svm->vcpu.arch.cr0;
1763 hsave->save.cr4 = svm->vcpu.arch.cr4;
1764 hsave->save.rflags = vmcb->save.rflags;
1765 hsave->save.rip = svm->next_rip;
1766 hsave->save.rsp = vmcb->save.rsp;
1767 hsave->save.rax = vmcb->save.rax;
1768 if (npt_enabled)
1769 hsave->save.cr3 = vmcb->save.cr3;
1770 else
1771 hsave->save.cr3 = svm->vcpu.arch.cr3;
1772
0460a979 1773 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1774
1775 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1776 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1777 else
1778 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1779
1780 /* Load the nested guest state */
1781 svm->vmcb->save.es = nested_vmcb->save.es;
1782 svm->vmcb->save.cs = nested_vmcb->save.cs;
1783 svm->vmcb->save.ss = nested_vmcb->save.ss;
1784 svm->vmcb->save.ds = nested_vmcb->save.ds;
1785 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1786 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1787 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1788 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1789 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1790 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1791 if (npt_enabled) {
1792 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1793 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1794 } else {
1795 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1796 kvm_mmu_reset_context(&svm->vcpu);
1797 }
defbba56 1798 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1799 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1800 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1801 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1802 /* In case we don't even reach vcpu_run, the fields are not updated */
1803 svm->vmcb->save.rax = nested_vmcb->save.rax;
1804 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1805 svm->vmcb->save.rip = nested_vmcb->save.rip;
1806 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1807 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1808 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1809
1810 /* We don't want a nested guest to be more powerful than the guest,
1811 so all intercepts are ORed */
1812 svm->vmcb->control.intercept_cr_read |=
1813 nested_vmcb->control.intercept_cr_read;
1814 svm->vmcb->control.intercept_cr_write |=
1815 nested_vmcb->control.intercept_cr_write;
1816 svm->vmcb->control.intercept_dr_read |=
1817 nested_vmcb->control.intercept_dr_read;
1818 svm->vmcb->control.intercept_dr_write |=
1819 nested_vmcb->control.intercept_dr_write;
1820 svm->vmcb->control.intercept_exceptions |=
1821 nested_vmcb->control.intercept_exceptions;
1822
1823 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1824
e6aa9abd 1825 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1826
aad42c64
JR		 1827 /* cache intercepts */
1828 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1829 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1830 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1831 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1832 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1833 svm->nested.intercept = nested_vmcb->control.intercept;
1834
3d6368ef
AG		 1835 force_new_asid(&svm->vcpu);
1836 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1837 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1838 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1839 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1840 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1841 nested_vmcb->control.int_ctl);
1842 }
1843 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1844 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1845 else
1846 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1847
1848 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1849 nested_vmcb->control.exit_int_info,
1850 nested_vmcb->control.int_state);
1851
1852 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1853 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1854 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1855 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1856 nsvm_printk("Injecting Event: 0x%x\n",
1857 nested_vmcb->control.event_inj);
1858 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1859 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1860
2af9194d 1861 enable_gif(svm);
3d6368ef
AG		 1862
1863 return 0;
1864}
1865
9966bf68 1866static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1867{
1868 to_vmcb->save.fs = from_vmcb->save.fs;
1869 to_vmcb->save.gs = from_vmcb->save.gs;
1870 to_vmcb->save.tr = from_vmcb->save.tr;
1871 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1872 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1873 to_vmcb->save.star = from_vmcb->save.star;
1874 to_vmcb->save.lstar = from_vmcb->save.lstar;
1875 to_vmcb->save.cstar = from_vmcb->save.cstar;
1876 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1877 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1878 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1879 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1880}
1881
1882static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1883{
9966bf68
JR		 1884 struct vmcb *nested_vmcb;
1885
5542675b
AG		 1886 if (nested_svm_check_permissions(svm))
1887 return 1;
1888
1889 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1890 skip_emulated_instruction(&svm->vcpu);
1891
9966bf68
JR		 1892 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1893 if (!nested_vmcb)
1894 return 1;
1895
1896 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1897 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1898
1899 return 1;
1900}
1901
1902static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1903{
9966bf68
JR		 1904 struct vmcb *nested_vmcb;
1905
5542675b
AG		 1906 if (nested_svm_check_permissions(svm))
1907 return 1;
1908
1909 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1910 skip_emulated_instruction(&svm->vcpu);
1911
9966bf68
JR		 1912 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1913 if (!nested_vmcb)
1914 return 1;
1915
1916 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1917 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1918
1919 return 1;
1920}
1921
3d6368ef
AG		 1922static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1923{
1924 nsvm_printk("VMrun\n");
1925 if (nested_svm_check_permissions(svm))
1926 return 1;
1927
1928 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1929 skip_emulated_instruction(&svm->vcpu);
1930
1931 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1932 NULL, nested_svm_vmrun))
1933 return 1;
1934
e6aa9abd 1935 if (nested_svm_do(svm, svm->nested.vmcb_msrpm, 0,
3d6368ef
AG		 1936 NULL, nested_svm_vmrun_msrpm))
1937 return 1;
1938
1939 return 1;
1940}
1941
1371d904
AG		 1942static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1943{
1944 if (nested_svm_check_permissions(svm))
1945 return 1;
1946
1947 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1948 skip_emulated_instruction(&svm->vcpu);
1949
2af9194d 1950 enable_gif(svm);
1371d904
AG		 1951
1952 return 1;
1953}
1954
1955static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1956{
1957 if (nested_svm_check_permissions(svm))
1958 return 1;
1959
1960 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1961 skip_emulated_instruction(&svm->vcpu);
1962
2af9194d 1963 disable_gif(svm);
1371d904
AG		 1964
1965 /* After a CLGI no interrupts should come */
1966 svm_clear_vintr(svm);
1967 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1968
1969 return 1;
1970}
1971
ff092385
AG		 1972static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1973{
1974 struct kvm_vcpu *vcpu = &svm->vcpu;
1975 nsvm_printk("INVLPGA\n");
1976
1977 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1978 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1979
1980 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1981 skip_emulated_instruction(&svm->vcpu);
1982 return 1;
1983}
1984
e756fc62
RR		 1985static int invalid_op_interception(struct vcpu_svm *svm,
1986 struct kvm_run *kvm_run)
6aa8b732 1987{
7ee5d940 1988 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1989 return 1;
1990}
1991
e756fc62
RR		 1992static int task_switch_interception(struct vcpu_svm *svm,
1993 struct kvm_run *kvm_run)
6aa8b732 1994{
37817f29 1995 u16 tss_selector;
64a7ec06
GN		 1996 int reason;
1997 int int_type = svm->vmcb->control.exit_int_info &
1998 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1999 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2000 uint32_t type =
2001 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2002 uint32_t idt_v =
2003 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2004
2005 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2006
37817f29
IE		 2007 if (svm->vmcb->control.exit_info_2 &
2008 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2009 reason = TASK_SWITCH_IRET;
2010 else if (svm->vmcb->control.exit_info_2 &
2011 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2012 reason = TASK_SWITCH_JMP;
fe8e7f83 2013 else if (idt_v)
64a7ec06
GN		 2014 reason = TASK_SWITCH_GATE;
2015 else
2016 reason = TASK_SWITCH_CALL;
2017
fe8e7f83
GN		 2018 if (reason == TASK_SWITCH_GATE) {
2019 switch (type) {
2020 case SVM_EXITINTINFO_TYPE_NMI:
2021 svm->vcpu.arch.nmi_injected = false;
2022 break;
2023 case SVM_EXITINTINFO_TYPE_EXEPT:
2024 kvm_clear_exception_queue(&svm->vcpu);
2025 break;
2026 case SVM_EXITINTINFO_TYPE_INTR:
2027 kvm_clear_interrupt_queue(&svm->vcpu);
2028 break;
2029 default:
2030 break;
2031 }
2032 }
64a7ec06 2033
8317c298
GN		 2034 if (reason != TASK_SWITCH_GATE ||
2035 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2036 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2037 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2038 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2039
2040 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2041}
2042
e756fc62 2043static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2044{
5fdbf976 2045 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2046 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2047 return 1;
6aa8b732
AK		 2048}
2049
95ba8273
GN		 2050static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2051{
2052 ++svm->vcpu.stat.nmi_window_exits;
2053 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2054 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2055 return 1;
2056}
2057
a7052897
MT		 2058static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2059{
2060 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2061 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2062 return 1;
2063}
2064
e756fc62
RR		 2065static int emulate_on_interception(struct vcpu_svm *svm,
2066 struct kvm_run *kvm_run)
6aa8b732 2067{
3427318f 2068 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 2069 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2070 return 1;
2071}
2072
1d075434
JR		 2073static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2074{
0a5fff19
GN		 2075 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2076 /* instruction emulation calls kvm_set_cr8() */
1d075434 2077 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 2078 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2079 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2080 return 1;
95ba8273 2081 }
0a5fff19
GN		 2082 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2083 return 1;
1d075434
JR		 2084 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2085 return 0;
2086}
2087
6aa8b732
AK		 2088static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2089{
a2fa3e9f
GH		 2090 struct vcpu_svm *svm = to_svm(vcpu);
2091
6aa8b732 2092 switch (ecx) {
af24a4e4 2093 case MSR_IA32_TSC: {
6aa8b732
AK		 2094 u64 tsc;
2095
2096 rdtscll(tsc);
a2fa3e9f 2097 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2098 break;
2099 }
0e859cac 2100 case MSR_K6_STAR:
a2fa3e9f 2101 *data = svm->vmcb->save.star;
6aa8b732 2102 break;
0e859cac 2103#ifdef CONFIG_X86_64
6aa8b732 2104 case MSR_LSTAR:
a2fa3e9f 2105 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2106 break;
2107 case MSR_CSTAR:
a2fa3e9f 2108 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2109 break;
2110 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2111 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2112 break;
2113 case MSR_SYSCALL_MASK:
a2fa3e9f 2114 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2115 break;
2116#endif
2117 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2118 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2119 break;
2120 case MSR_IA32_SYSENTER_EIP:
017cb99e 2121 *data = svm->sysenter_eip;
6aa8b732
AK		 2122 break;
2123 case MSR_IA32_SYSENTER_ESP:
017cb99e 2124 *data = svm->sysenter_esp;
6aa8b732 2125 break;
a2938c80
JR		 2126 /* Nobody will change the following 5 values in the VMCB so
2127 we can safely return them on rdmsr. They will always be 0
2128 until LBRV is implemented. */
2129 case MSR_IA32_DEBUGCTLMSR:
2130 *data = svm->vmcb->save.dbgctl;
2131 break;
2132 case MSR_IA32_LASTBRANCHFROMIP:
2133 *data = svm->vmcb->save.br_from;
2134 break;
2135 case MSR_IA32_LASTBRANCHTOIP:
2136 *data = svm->vmcb->save.br_to;
2137 break;
2138 case MSR_IA32_LASTINTFROMIP:
2139 *data = svm->vmcb->save.last_excp_from;
2140 break;
2141 case MSR_IA32_LASTINTTOIP:
2142 *data = svm->vmcb->save.last_excp_to;
2143 break;
b286d5d8 2144 case MSR_VM_HSAVE_PA:
e6aa9abd 2145 *data = svm->nested.hsave_msr;
b286d5d8 2146 break;
eb6f302e
JR		 2147 case MSR_VM_CR:
2148 *data = 0;
2149 break;
c8a73f18
AG		 2150 case MSR_IA32_UCODE_REV:
2151 *data = 0x01000065;
2152 break;
6aa8b732 2153 default:
3bab1f5d 2154 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2155 }
2156 return 0;
2157}
2158
e756fc62 2159static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2160{
ad312c7c 2161 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2162 u64 data;
2163
e756fc62 2164 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2165 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2166 else {
229456fc 2167 trace_kvm_msr_read(ecx, data);
af9ca2d7 2168
5fdbf976 2169 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2170 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2171 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2172 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2173 }
2174 return 1;
2175}
2176
2177static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2178{
a2fa3e9f
GH		 2179 struct vcpu_svm *svm = to_svm(vcpu);
2180
6aa8b732 2181 switch (ecx) {
af24a4e4 2182 case MSR_IA32_TSC: {
6aa8b732
AK		 2183 u64 tsc;
2184
2185 rdtscll(tsc);
a2fa3e9f 2186 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2187 break;
2188 }
0e859cac 2189 case MSR_K6_STAR:
a2fa3e9f 2190 svm->vmcb->save.star = data;
6aa8b732 2191 break;
49b14f24 2192#ifdef CONFIG_X86_64
6aa8b732 2193 case MSR_LSTAR:
a2fa3e9f 2194 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2195 break;
2196 case MSR_CSTAR:
a2fa3e9f 2197 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2198 break;
2199 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2200 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2201 break;
2202 case MSR_SYSCALL_MASK:
a2fa3e9f 2203 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2204 break;
2205#endif
2206 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2207 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2208 break;
2209 case MSR_IA32_SYSENTER_EIP:
017cb99e 2210 svm->sysenter_eip = data;
a2fa3e9f 2211 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2212 break;
2213 case MSR_IA32_SYSENTER_ESP:
017cb99e 2214 svm->sysenter_esp = data;
a2fa3e9f 2215 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2216 break;
a2938c80 2217 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2218 if (!svm_has(SVM_FEATURE_LBRV)) {
2219 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2220 __func__, data);
24e09cbf
JR		 2221 break;
2222 }
2223 if (data & DEBUGCTL_RESERVED_BITS)
2224 return 1;
2225
2226 svm->vmcb->save.dbgctl = data;
2227 if (data & (1ULL<<0))
2228 svm_enable_lbrv(svm);
2229 else
2230 svm_disable_lbrv(svm);
a2938c80 2231 break;
b286d5d8 2232 case MSR_VM_HSAVE_PA:
e6aa9abd 2233 svm->nested.hsave_msr = data;
62b9abaa 2234 break;
3c5d0a44
AG		 2235 case MSR_VM_CR:
2236 case MSR_VM_IGNNE:
3c5d0a44
AG		 2237 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2238 break;
6aa8b732 2239 default:
3bab1f5d 2240 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2241 }
2242 return 0;
2243}
2244
e756fc62 2245static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2246{
ad312c7c 2247 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2248 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2249 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2250
229456fc 2251 trace_kvm_msr_write(ecx, data);
af9ca2d7 2252
5fdbf976 2253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2254 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2255 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2256 else
e756fc62 2257 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2258 return 1;
2259}
2260
e756fc62 2261static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2262{
e756fc62
RR		 2263 if (svm->vmcb->control.exit_info_1)
2264 return wrmsr_interception(svm, kvm_run);
6aa8b732 2265 else
e756fc62 2266 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2267}
2268
e756fc62 2269static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2270 struct kvm_run *kvm_run)
2271{
f0b85051 2272 svm_clear_vintr(svm);
85f455f7 2273 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2274 /*
2275 * If the user space waits to inject interrupts, exit as soon as
2276 * possible
2277 */
8061823a
GN		 2278 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2279 kvm_run->request_interrupt_window &&
2280 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2281 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2282 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2283 return 0;
2284 }
2285
2286 return 1;
2287}
2288
e756fc62 2289static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2290 struct kvm_run *kvm_run) = {
2291 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2292 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2293 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2294 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2295 /* for now: */
2296 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2297 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2298 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2299 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2300 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2301 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2302 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2303 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2304 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2305 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2306 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2307 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2308 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2309 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2310 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2311 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2312 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2313 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2314 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2315 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2316 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2317 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2318 [SVM_EXIT_SMI] = nop_on_interception,
2319 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2320 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2321 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2322 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2323 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2324 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2325 [SVM_EXIT_HLT] = halt_interception,
a7052897 2326 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2327 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2328 [SVM_EXIT_IOIO] = io_interception,
2329 [SVM_EXIT_MSR] = msr_interception,
2330 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2331 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2332 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2333 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2334 [SVM_EXIT_VMLOAD] = vmload_interception,
2335 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2336 [SVM_EXIT_STGI] = stgi_interception,
2337 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2338 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2339 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2340 [SVM_EXIT_MONITOR] = invalid_op_interception,
2341 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2342 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2343};
2344
04d2cc77 2345static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2346{
04d2cc77 2347 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2348 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2349
229456fc 2350 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2351
cf74a78b
AG		 2352 if (is_nested(svm)) {
2353 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2354 exit_code, svm->vmcb->control.exit_info_1,
2355 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
9c4e40b9 2356 if (nested_svm_exit_handled(svm, true))
cf74a78b 2357 return 1;
cf74a78b
AG		 2358 }
2359
a5c3832d
JR		 2360 svm_complete_interrupts(svm);
2361
709ddebf
JR		 2362 if (npt_enabled) {
2363 int mmu_reload = 0;
2364 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2365 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2366 mmu_reload = 1;
2367 }
2368 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2369 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2370 if (mmu_reload) {
2371 kvm_mmu_reset_context(vcpu);
2372 kvm_mmu_load(vcpu);
2373 }
2374 }
2375
04d2cc77
AK		 2376
2377 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2378 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2379 kvm_run->fail_entry.hardware_entry_failure_reason
2380 = svm->vmcb->control.exit_code;
2381 return 0;
2382 }
2383
a2fa3e9f 2384 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2385 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2386 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2387 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2388 "exit_code 0x%x\n",
b8688d51 2389 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2390 exit_code);
2391
9d8f549d 2392 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2393 || !svm_exit_handlers[exit_code]) {
6aa8b732 2394 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2395 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2396 return 0;
2397 }
2398
e756fc62 2399 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2400}
2401
2402static void reload_tss(struct kvm_vcpu *vcpu)
2403{
2404 int cpu = raw_smp_processor_id();
2405
2406 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2407 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2408 load_TR_desc();
2409}
2410
e756fc62 2411static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2412{
2413 int cpu = raw_smp_processor_id();
2414
2415 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2416
a2fa3e9f 2417 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2418 /* FIXME: handle wraparound of asid_generation */
2419 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2420 new_asid(svm, svm_data);
6aa8b732
AK		 2421}
2422
95ba8273
GN		 2423static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2424{
2425 struct vcpu_svm *svm = to_svm(vcpu);
2426
2427 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2428 vcpu->arch.hflags |= HF_NMI_MASK;
2429 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2430 ++vcpu->stat.nmi_injections;
2431}
6aa8b732 2432
85f455f7 2433static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2434{
2435 struct vmcb_control_area *control;
2436
229456fc 2437 trace_kvm_inj_virq(irq);
af9ca2d7 2438
fa89a817 2439 ++svm->vcpu.stat.irq_injections;
e756fc62 2440 control = &svm->vmcb->control;
85f455f7 2441 control->int_vector = irq;
6aa8b732
AK		 2442 control->int_ctl &= ~V_INTR_PRIO_MASK;
2443 control->int_ctl |= V_IRQ_MASK |
2444 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2445}
2446
66fd3f7f 2447static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2448{
2449 struct vcpu_svm *svm = to_svm(vcpu);
2450
2af9194d 2451 BUG_ON(!(gif_set(svm)));
cf74a78b 2452
219b65dc
AG		 2453 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2454 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2455}
2456
95ba8273 2457static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2458{
2459 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2460
95ba8273 2461 if (irr == -1)
aaacfc9a
JR		 2462 return;
2463
95ba8273
GN		 2464 if (tpr >= irr)
2465 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2466}
aaacfc9a 2467
95ba8273
GN		 2468static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2469{
2470 struct vcpu_svm *svm = to_svm(vcpu);
2471 struct vmcb *vmcb = svm->vmcb;
2472 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2473 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2474}
2475
78646121
GN		 2476static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2477{
2478 struct vcpu_svm *svm = to_svm(vcpu);
2479 struct vmcb *vmcb = svm->vmcb;
2480 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2481 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2482 gif_set(svm) &&
219b65dc 2483 !is_nested(svm);
78646121
GN		 2484}
2485
9222be18 2486static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2487{
219b65dc
AG		 2488 struct vcpu_svm *svm = to_svm(vcpu);
2489 nsvm_printk("Trying to open IRQ window\n");
2490
2491 nested_svm_intr(svm);
2492
2493 /* In case GIF=0 we can't rely on the CPU to tell us when
2494 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2495 * The next time we get that intercept, this function will be
2496 * called again though and we'll get the vintr intercept. */
2af9194d 2497 if (gif_set(svm)) {
219b65dc
AG		 2498 svm_set_vintr(svm);
2499 svm_inject_irq(svm, 0x0);
2500 }
85f455f7
ED		 2501}
2502
95ba8273 2503static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2504{
04d2cc77 2505 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2506
44c11430
GN		 2507 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2508 == HF_NMI_MASK)
2509 return; /* IRET will cause a vm exit */
2510
2511 /* Something prevents NMI from been injected. Single step over
2512 possible problem (IRET or exception injection or interrupt
2513 shadow) */
2514 vcpu->arch.singlestep = true;
2515 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2516 update_db_intercept(vcpu);
c1150d8c
DL		 2517}
2518
cbc94022
IE		 2519static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2520{
2521 return 0;
2522}
2523
d9e368d6
AK		 2524static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2525{
2526 force_new_asid(vcpu);
2527}
2528
04d2cc77
AK		 2529static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2530{
2531}
2532
d7bf8221
JR		 2533static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2534{
2535 struct vcpu_svm *svm = to_svm(vcpu);
2536
2537 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2538 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2539 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2540 }
2541}
2542
649d6864
JR		 2543static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2544{
2545 struct vcpu_svm *svm = to_svm(vcpu);
2546 u64 cr8;
2547
649d6864
JR		 2548 cr8 = kvm_get_cr8(vcpu);
2549 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2550 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2551}
2552
9222be18
GN		 2553static void svm_complete_interrupts(struct vcpu_svm *svm)
2554{
2555 u8 vector;
2556 int type;
2557 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2558
44c11430
GN		 2559 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2560 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2561
9222be18
GN		 2562 svm->vcpu.arch.nmi_injected = false;
2563 kvm_clear_exception_queue(&svm->vcpu);
2564 kvm_clear_interrupt_queue(&svm->vcpu);
2565
2566 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2567 return;
2568
2569 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2570 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2571
2572 switch (type) {
2573 case SVM_EXITINTINFO_TYPE_NMI:
2574 svm->vcpu.arch.nmi_injected = true;
2575 break;
2576 case SVM_EXITINTINFO_TYPE_EXEPT:
2577 /* In case of software exception do not reinject an exception
2578 vector, but re-execute and instruction instead */
219b65dc
AG		 2579 if (is_nested(svm))
2580 break;
66fd3f7f 2581 if (kvm_exception_is_soft(vector))
9222be18
GN		 2582 break;
2583 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2584 u32 err = svm->vmcb->control.exit_int_info_err;
2585 kvm_queue_exception_e(&svm->vcpu, vector, err);
2586
2587 } else
2588 kvm_queue_exception(&svm->vcpu, vector);
2589 break;
2590 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2591 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2592 break;
2593 default:
2594 break;
2595 }
2596}
2597
80e31d4f
AK		 2598#ifdef CONFIG_X86_64
2599#define R "r"
2600#else
2601#define R "e"
2602#endif
2603
04d2cc77 2604static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2605{
a2fa3e9f 2606 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2607 u16 fs_selector;
2608 u16 gs_selector;
2609 u16 ldt_selector;
d9e368d6 2610
5fdbf976
MT		 2611 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2612 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2613 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2614
e756fc62 2615 pre_svm_run(svm);
6aa8b732 2616
649d6864
JR		 2617 sync_lapic_to_cr8(vcpu);
2618
6aa8b732 2619 save_host_msrs(vcpu);
d6e88aec
AK		 2620 fs_selector = kvm_read_fs();
2621 gs_selector = kvm_read_gs();
2622 ldt_selector = kvm_read_ldt();
3d6368ef
AG		 2623 if (!is_nested(svm))
2624 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2625 /* required for live migration with NPT */
2626 if (npt_enabled)
2627 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2628
04d2cc77
AK		 2629 clgi();
2630
2631 local_irq_enable();
36241b8c 2632
6aa8b732 2633 asm volatile (
80e31d4f
AK		 2634 "push %%"R"bp; \n\t"
2635 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2636 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2637 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2638 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2639 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2640 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2641#ifdef CONFIG_X86_64
fb3f0f51
RR		 2642 "mov %c[r8](%[svm]), %%r8 \n\t"
2643 "mov %c[r9](%[svm]), %%r9 \n\t"
2644 "mov %c[r10](%[svm]), %%r10 \n\t"
2645 "mov %c[r11](%[svm]), %%r11 \n\t"
2646 "mov %c[r12](%[svm]), %%r12 \n\t"
2647 "mov %c[r13](%[svm]), %%r13 \n\t"
2648 "mov %c[r14](%[svm]), %%r14 \n\t"
2649 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2650#endif
2651
6aa8b732 2652 /* Enter guest mode */
80e31d4f
AK		 2653 "push %%"R"ax \n\t"
2654 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2655 __ex(SVM_VMLOAD) "\n\t"
2656 __ex(SVM_VMRUN) "\n\t"
2657 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2658 "pop %%"R"ax \n\t"
6aa8b732
AK		 2659
2660 /* Save guest registers, load host registers */
80e31d4f
AK		 2661 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2662 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2663 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2664 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2665 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2666 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2667#ifdef CONFIG_X86_64
fb3f0f51
RR		 2668 "mov %%r8, %c[r8](%[svm]) \n\t"
2669 "mov %%r9, %c[r9](%[svm]) \n\t"
2670 "mov %%r10, %c[r10](%[svm]) \n\t"
2671 "mov %%r11, %c[r11](%[svm]) \n\t"
2672 "mov %%r12, %c[r12](%[svm]) \n\t"
2673 "mov %%r13, %c[r13](%[svm]) \n\t"
2674 "mov %%r14, %c[r14](%[svm]) \n\t"
2675 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2676#endif
80e31d4f 2677 "pop %%"R"bp"
6aa8b732 2678 :
fb3f0f51 2679 : [svm]"a"(svm),
6aa8b732 2680 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2681 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2682 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2683 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2684 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2685 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2686 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2687#ifdef CONFIG_X86_64
ad312c7c
ZX		 2688 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2689 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2690 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2691 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2692 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2693 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2694 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2695 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2696#endif
54a08c04 2697 : "cc", "memory"
80e31d4f 2698 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2699#ifdef CONFIG_X86_64
54a08c04
LV		 2700 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2701#endif
2702 );
6aa8b732 2703
ad312c7c 2704 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2705 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2706 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2707 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2708
d6e88aec
AK		 2709 kvm_load_fs(fs_selector);
2710 kvm_load_gs(gs_selector);
2711 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2712 load_host_msrs(vcpu);
2713
2714 reload_tss(vcpu);
2715
56ba47dd
AK		 2716 local_irq_disable();
2717
2718 stgi();
2719
d7bf8221
JR		 2720 sync_cr8_to_lapic(vcpu);
2721
a2fa3e9f 2722 svm->next_rip = 0;
9222be18 2723
6de4f3ad
AK		 2724 if (npt_enabled) {
2725 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2726 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2727 }
6aa8b732
AK		 2728}
2729
80e31d4f
AK		 2730#undef R
2731
6aa8b732
AK		 2732static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2733{
a2fa3e9f
GH		 2734 struct vcpu_svm *svm = to_svm(vcpu);
2735
709ddebf
JR		 2736 if (npt_enabled) {
2737 svm->vmcb->control.nested_cr3 = root;
2738 force_new_asid(vcpu);
2739 return;
2740 }
2741
a2fa3e9f 2742 svm->vmcb->save.cr3 = root;
6aa8b732 2743 force_new_asid(vcpu);
7807fa6c
AL		 2744
2745 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2746 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2747 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2748 vcpu->fpu_active = 0;
2749 }
6aa8b732
AK		 2750}
2751
6aa8b732
AK		 2752static int is_disabled(void)
2753{
6031a61c
JR		 2754 u64 vm_cr;
2755
2756 rdmsrl(MSR_VM_CR, vm_cr);
2757 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2758 return 1;
2759
6aa8b732
AK		 2760 return 0;
2761}
2762
102d8325
IM		 2763static void
2764svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2765{
2766 /*
2767 * Patch in the VMMCALL instruction:
2768 */
2769 hypercall[0] = 0x0f;
2770 hypercall[1] = 0x01;
2771 hypercall[2] = 0xd9;
102d8325
IM		 2772}
2773
002c7f7c
YS		 2774static void svm_check_processor_compat(void *rtn)
2775{
2776 *(int *)rtn = 0;
2777}
2778
774ead3a
AK		 2779static bool svm_cpu_has_accelerated_tpr(void)
2780{
2781 return false;
2782}
2783
67253af5
SY		 2784static int get_npt_level(void)
2785{
2786#ifdef CONFIG_X86_64
2787 return PT64_ROOT_LEVEL;
2788#else
2789 return PT32E_ROOT_LEVEL;
2790#endif
2791}
2792
4b12f0de 2793static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2794{
2795 return 0;
2796}
2797
229456fc
MT		 2798static const struct trace_print_flags svm_exit_reasons_str[] = {
2799 { SVM_EXIT_READ_CR0, "read_cr0" },
2800 { SVM_EXIT_READ_CR3, "read_cr3" },
2801 { SVM_EXIT_READ_CR4, "read_cr4" },
2802 { SVM_EXIT_READ_CR8, "read_cr8" },
2803 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2804 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2805 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2806 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2807 { SVM_EXIT_READ_DR0, "read_dr0" },
2808 { SVM_EXIT_READ_DR1, "read_dr1" },
2809 { SVM_EXIT_READ_DR2, "read_dr2" },
2810 { SVM_EXIT_READ_DR3, "read_dr3" },
2811 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2812 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2813 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2814 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2815 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2816 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2817 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2818 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2819 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2820 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2821 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2822 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2823 { SVM_EXIT_INTR, "interrupt" },
2824 { SVM_EXIT_NMI, "nmi" },
2825 { SVM_EXIT_SMI, "smi" },
2826 { SVM_EXIT_INIT, "init" },
2827 { SVM_EXIT_VINTR, "vintr" },
2828 { SVM_EXIT_CPUID, "cpuid" },
2829 { SVM_EXIT_INVD, "invd" },
2830 { SVM_EXIT_HLT, "hlt" },
2831 { SVM_EXIT_INVLPG, "invlpg" },
2832 { SVM_EXIT_INVLPGA, "invlpga" },
2833 { SVM_EXIT_IOIO, "io" },
2834 { SVM_EXIT_MSR, "msr" },
2835 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2836 { SVM_EXIT_SHUTDOWN, "shutdown" },
2837 { SVM_EXIT_VMRUN, "vmrun" },
2838 { SVM_EXIT_VMMCALL, "hypercall" },
2839 { SVM_EXIT_VMLOAD, "vmload" },
2840 { SVM_EXIT_VMSAVE, "vmsave" },
2841 { SVM_EXIT_STGI, "stgi" },
2842 { SVM_EXIT_CLGI, "clgi" },
2843 { SVM_EXIT_SKINIT, "skinit" },
2844 { SVM_EXIT_WBINVD, "wbinvd" },
2845 { SVM_EXIT_MONITOR, "monitor" },
2846 { SVM_EXIT_MWAIT, "mwait" },
2847 { SVM_EXIT_NPF, "npf" },
2848 { -1, NULL }
2849};
2850
344f414f
JR		 2851static bool svm_gb_page_enable(void)
2852{
2853 return true;
2854}
2855
cbdd1bea 2856static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2857 .cpu_has_kvm_support = has_svm,
2858 .disabled_by_bios = is_disabled,
2859 .hardware_setup = svm_hardware_setup,
2860 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2861 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2862 .hardware_enable = svm_hardware_enable,
2863 .hardware_disable = svm_hardware_disable,
774ead3a 2864 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2865
2866 .vcpu_create = svm_create_vcpu,
2867 .vcpu_free = svm_free_vcpu,
04d2cc77 2868 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2869
04d2cc77 2870 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2871 .vcpu_load = svm_vcpu_load,
2872 .vcpu_put = svm_vcpu_put,
2873
2874 .set_guest_debug = svm_guest_debug,
2875 .get_msr = svm_get_msr,
2876 .set_msr = svm_set_msr,
2877 .get_segment_base = svm_get_segment_base,
2878 .get_segment = svm_get_segment,
2879 .set_segment = svm_set_segment,
2e4d2653 2880 .get_cpl = svm_get_cpl,
1747fb71 2881 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2882 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2883 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2884 .set_cr3 = svm_set_cr3,
2885 .set_cr4 = svm_set_cr4,
2886 .set_efer = svm_set_efer,
2887 .get_idt = svm_get_idt,
2888 .set_idt = svm_set_idt,
2889 .get_gdt = svm_get_gdt,
2890 .set_gdt = svm_set_gdt,
2891 .get_dr = svm_get_dr,
2892 .set_dr = svm_set_dr,
6de4f3ad 2893 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2894 .get_rflags = svm_get_rflags,
2895 .set_rflags = svm_set_rflags,
2896
6aa8b732 2897 .tlb_flush = svm_flush_tlb,
6aa8b732 2898
6aa8b732 2899 .run = svm_vcpu_run,
04d2cc77 2900 .handle_exit = handle_exit,
6aa8b732 2901 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2902 .set_interrupt_shadow = svm_set_interrupt_shadow,
2903 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2904 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2905 .set_irq = svm_set_irq,
95ba8273 2906 .set_nmi = svm_inject_nmi,
298101da 2907 .queue_exception = svm_queue_exception,
78646121 2908 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2909 .nmi_allowed = svm_nmi_allowed,
2910 .enable_nmi_window = enable_nmi_window,
2911 .enable_irq_window = enable_irq_window,
2912 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2913
2914 .set_tss_addr = svm_set_tss_addr,
67253af5 2915 .get_tdp_level = get_npt_level,
4b12f0de 2916 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2917
2918 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2919 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2920};
2921
2922static int __init svm_init(void)
2923{
cb498ea2 2924 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2925 THIS_MODULE);
6aa8b732
AK		 2926}
2927
2928static void __exit svm_exit(void)
2929{
cb498ea2 2930 kvm_exit();
6aa8b732
AK		 2931}
2932
2933module_init(svm_init)
2934module_exit(svm_exit)
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